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  2. Hi Graham, Thanks! Curiously, when I add that line I get the same result as before: synthesis completes, but the entire fast clock pipeline is missing form the synthesized result. I wonder why the difference? Best, Allan
  3. Today
  4. Hi Allan Also, It did pass Synthesis after I added set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets HAM_IN_IBUF]; into the xdc (not a recommended thing to do) Kind Regards Graham
  5. Hi Allan Ugly is fine, but it will mess with the syntheses quite a lot, using a clock buffer with an enable would do the trick. Kind Regards Graham
  6. Hi Graham, Thanks, and agreed that's ugly. Originally had it as below, treating the signals as signals and clocks as clocks, same results (sim fine, synth not). Went to simple AND while tearing code apart trying to understand behavior. Best, Allan ham_process : process(clk_cycles) begin if rising_edge(clk_cycles) then HAM_OUT <= HAM_IN; end if; if falling_edge(clk_cycles) then HAM_OUT <= '0'; end if; end process ham_process;
  7. Hi Allan, I think the first thing you should do with the project is stop gateing HAM_IN with a clock. (cycles_raw <= HAM_IN and clk_cycles). Kind Regards Graham
  8. I'm having a problem with synthesizing a project built around a fast clock for a Cmod A7. The code attached (main file RAD_counter, based on Mike Field's "fast_freq_counter", thanks Mike!) creates a 450MHz clock from the on-board 12MHz clock using two MMCMs (12->250, 250->450). It then uses the fast clock to modulate a signal input via pin; this modulated signal is sent into a fast counter to approximate area under the curve of the input signal. A second pipeline counts edges in the original input signal. Both counts are output over a single 16-bit bus using a 2-state mux. The code behaves precisely as expected in the Vivado simulator. Synthesis, however, fails: the synthesizer claims that the output from the clock is not used and leaves the pin dangling; the rest of the modulated-signal chain then simply disappears. I'm new to FPGAs & VHDL -- this is my first significant project -- so no doubt I'm making a very simple mistake. That said, I've spent a lot of time trying to track it down (including replacing the MMCM code with IP from the clock wizard, rewriting basically every file in the project from scratch) and no luck. If anyone has guidance (for this problem, for debugging in general) I'd very much appreciate it. Thanks, Allan sampler_gray4.vhd RAD_Testbench.vhd RAD_Counter.xdc RAD_counter.vhd rad_clock.vhd prescaler_3.vhd output_mux.vhd gray_to_bin_4.vhd counter_gray4.vhd accumulator.vhd
  9. Yesterday
  10. There are two general approaches to dealing with the Soft processor or ARM processor flows when these are embedded into a design. One is to do the whole design within the framework of the tools, in VIvado the board design flow. I've done that using Xilinx IP and creating and packaging my own IP. I much prefer the other approach which is to constrain the whole IP stuff into a "black box". I use interfaces that have external pins exposed that are easy to connect to HDL. BRAMs are useful or sometimes it makes sense to package my own interface IP. Once the board design is complete and generated I have Vivado create an HDL file encapsulating the entire mess and then instantiate that as a component in my own toplevel HDL. Make sure to let Vivado know that you want to control the heirarchy not Vivado. There's no right way to do it; it depends on you own preferences and convenience. A good general rule, in my experience, is that letting the tools control things is never as good as having the tools let me control things. In the end the price of convenience usually results in unwanted constraint. Also, vendor IP is happy to use up resources with functionality that I don't need. I still use ARM based FPGAs but can't remember that last time I felt the need to use a MicroBlaze or Nios. [edit] Oh... and most important is that vendor IP is prone to being broken with new tools versions. Upgrading old IP, especially for soft processors, is rarely as simple or trivial as the vendors want you to believe that it is. Just yesterday I was testing a demo release for the Project Vault by rebuilding it on another host. The design was created in Vivado 2016.2 and the test build was created in Vivado 2019.1. There were only two IP, an MMCM and a FIFO and Vivado 2019.1 choked on both because it has restructured it's internal IP handling. This was the first time in quite a while that basic FPGA resource IP got trashed by a tool version; but it happens. For most of the other IP this happens a lot more frequently. If the SDK is involved then schedule a few days or more to figure out how to resurrect old designs created by past tool versions.
  11. Good Day, I have followed the Nexys 4 DDR tutorial - getting started with microblaze servers: I have however run into an issue. I have managed to set up the hardware, and export to the SDK. However running tera term I am met with "connection refused" or "connection timed out". I have managed to accomplish all steps with exception of 12.2 (STDIO) as it is not available in 2018.3. Would there be any suggestions or advice how to remedy this issue? Regards, Luke Abela
  12. Hi, How to change the digital voltage and drive of the output pins dIO31-24 with a python script driving a digital discovery ? How to read the current of the vIO with a python script ? And how to turn it on ? Thank you, Laurent
  13. So you have working fixed point RTL (sounds like quite an achievement BTW) and want to hook it up to the Microblaze. I'd look for info how to implement an AXI lite slave. Vivado has several built-in options to help with that - not necessarily the best way, depending who you ask, but it did work for me. For example "Tools / Create and package new IP / create a new AXI4 peripheral". Finish the wizard, then take the Verilog file with its implemented dummy registers and continue editing it by hand. My first step would be - plain registers for input data - a write-sensitive registers for the final input data word or a dedicated "control / start" word that resets/starts the processing state machine and clears an "output-is-valid" bit - a register for the first result that blocks on read for "output-is-valid" from the state machine - plain read-only registers for the remaining output data The control flow of the program is simply "write data, read results, repeat". I'd sell this as "minimum-size approach"... It can be improved in many ways (e.g. output-side FIFO, input-side FIFO, pipelined processing in RTL, full AXI / stream, ...) depending on your specific requirements e.g. throughput, bus utilization, avoid blocking the CPU.
  14. Hi, I'm a beginner of FPGA. I'm trying to print some messages on PmodOLED when pressed a key on PmodKPD. For example, when I pressed key "1" on PmodKPD, the Pmod OLED displays, "You pressed key #1", when I pressed key "9" on PmodKPD, the Pmod OLED displays, "You pressed key #9", and so on. I don't know how to program in Xilinx SDK, in particular, how to map Pmod interface or pins. Any sample code available? I'm using PYNQ-Z1 board, PmodKYPD for PMODA port, and PmodOLED for PMODB port. Thank you, in advance, for your great help.
  15. Last week
  16. Kaitlyn, Its good that you responded as you are the face of the AD2 as there's no one better to talk to. It comes down to knowing your users and what their needs are. I do prototyping and my needs varies. I bought the AD2 because it covers the full gambit of potential test features I could be faced with. For me everything is short duration in learning new tools to complete a project is important. Being able to find general information, principles and logic helps to ease the learning curve. Tutorial makes it easier. Sometimes a few tweaks on a tutorial is all that's needed. If it were me, I would create a list of expected uses for each feature operation (Scope, Wavegen,Supplies......etc ]) Within each of those feature operations I would pick the most common uses and then divide them in to 3 levels of complexity. That way a user can manage their learning curve. Get a hold of Microsoft Viso and use the flowchart to create a visual procedure of the tutorial. Use the flowchart it to create your video and refine it. The flowchart should have every step wire, connection, setting performed. When you are ready have co-workers to test the tutorial and identify potential roadblocks. This is the most important step. Observe their test as any trouble they encounter will most likely be encountered by an actual user. Resolve and note the roadblocks in the tutorial and release. Your objective is to have anyone at any level carry out the tutorial to completion. We all want easy....... Complaints without solutions is called crying. I've got to get back to work.... Good luck Inobu
  17. Hi OvidiuD, Yes, that works very well, thanks. Dave
  18. Hey Inobu, Thanks for the feedback on the videos! There is some additional documentation on the resource center here that you might find useful: Do you have any specific ideas on videos or documentation that you think might be helpful? I want to create the most useful documentation possible so I love to get requests and feedback directly from users. Kaitlyn
  19. Hello, I am working on lwip webserver in vivado 2018.1. The code for the webserver is in C language. I want to create a dynamic webpage that displays the value of the 32-bit system register according to my application. I came across the lwip documentation that uses an example for the web server. However, it is in 2014.3 and that creates a problem when I use it in 2018.1! Also, there is memfs folder in it that contains the .js, .css files and all! The example creates some image.mfs in ddr memory location! In my case, I have created a const char [ ] that has html code inside and I pass it in tcp_write( ) and the web page gets displayed! It works. I have also created javascript code in the html code itself that dynamically changes the content on the webpage through button onclick event. However, I want this to be change using the C variable in my code. So, how do I link the C global variable or local variable to the javascript? In simpler way, I tried to declare a global variable say UINT a=10. Then, on button onclick event, when javascript is executed, I tried to change the content on webpage using the variable "a". But it doesn't work! Does anyone knows how to make my C code and javascript code work together? For reference, I am attaching the html and javascript code below: const char testdata[]= "<html> <body> <button onclick=\"start()\"> Start the countdown </button> <p id=\"demo\"> This the main page for the test application of the web server...</p> <p id=\"ch1\"> Change me with variable a...</p> <div id=\"bip\"> </div> <script> var counter = 10; var intervalId = null; function finish() { clearInterval(intervalId); document.getElementById(\"bip\").innerHTML = \"THE END!\"; if(counter == 0) { var xhttp = new XMLHttpRequest(); xhttp.onreadystatechange = function(){ if(this.readyState == 4 && this.status == 200){ document.getElementById(\"demo\").innerHTML = this.responseText; }} }\"GET\", \"ajaxinfo.txt\", true); xhttp.send(); } function bip() { if(counter == 0) finish(); else { document.getElementById(\"bip\").innerHTML = counter + \" seconds remaining\"; } counter--; } function start() { intervalId = setInterval(bip, 1000);} </script> </body> </html>"; I want to replace any <p> element with a global variable that will be declared in the C code that has this html code inside a const char array as shown above. Any help is highly appreciated. Thanks,
  20. Attila, this seems fine so far and thank you for this great work. The "all files" button in the search bar executes a "replace all" across all open script files. I discovered this when I had the letter "i" as the Find argument and nothing as the Replace argument. Clicking 'All Files' deleted all instances of the letter "i" in both my script files. Logical, but yikes. Perhaps both "Replace All" and "All Files" should include a "Confirm?" interaction? Nothing seems to be broken in this latest rev. I'll be using this every day for the next while. Thanks again!
  21. Time to expound on the support video. Specifically the AD2. Search "analog discovery 2 tutorial" on youtube and the results yields your quick start videos. Those videos are basically a verbal mouse overs. The AD2 is on the Higher end of the price spectrum so user created videos are limited. The only way to increase users/sales is product awareness associated with easy of operation. The tutorial tasks should be at lower mid level complexity as this product users is not going to spend $300 to test a blinking LED. Its all about support and how easy it is accessed. Inobu
  22. Before attaching any FMC mezzanine card to any carrier, particularly yours, the first step is to know what Vadj IO Bank voltages are supported by your carrier board. Then, you have to go through the schematics of board boards to make sure that pin assignments will support whatever IOSTANDARD you need. Never assume that the FMC standard or connectors indicate compatibility of carrier and mezzanine cards. Even if someone tells you that they've used a carrier and mezzanine board combination the onus is on you to verify everything. Again, the fact that the connectors on two boards can mate doesn't imply functional compatibility.
  23. JColvin, Thanks for the response. I am using the Arty Z7 -20. I would like to apply this to other Xilinx Zynq boards that I have here at work like the ZC706. I will take a look at the tutorials. Thanks. Tim
  24. Hi @elodg, I know you're a lot more familiar with the physical and electrical aspects of the MIPI CSI-2 interface; could you clarify with more accuracy than I can provide about the physical layer? Thanks, JColvin
  25. Hi @timseverance77, I'm not sure which board you are using, but did you look at the tutorial Jon linked here as well as this tutorial here? Thanks, JColvin
  26. JColvin

    DMC60c CAN Bus

    Hi @opethmc, The engineer who wrote the firmware is out of the office until next week; we will be able to let you know then if that is something that can be readily done. Thanks, JColvin
  27. @rivermoon, Go for it, and good luck! I've found that wireshark was very useful when debugging network interactions. Let me take a moment and suggest you look into it and try it out. Also, I'd love to hear back from you regarding your success when everything works like it should. So often these forum posts only discuss problems and we never hear successes here. That said, it's your call what you want to share. Dan
  28. @Jess, While I've done VHDL before, it's really not my strong suit so I'd love to see some VHDL designers step in at this point. That said, you should never need to instantiate a flip-flop (FF) on your own. The tools should "just do it" for you. In particular, your code snippet (below) does exactly this: divisor : process(elclock) variable div_cont : integer := 0; begin if (rising_edge(elclock)) then if (div_cont = max) then temporal <= not temporal; div_cont := 0; else div_cont := div_cont + 1; end if; end if; end process divisor; Both div_cont and temporal will be implemented with FF's. That said, I'm not familiar enough with VHDL to catch the subtleties here. For example, I've never seen something set *after* the end of the if (rising_edge(clock)) block but still within the process. This might be a bad thing, or might not, I'm not sure. The other thing to be aware of is that in spite of its name s_clock *IS* *NOT* *A* *CLOCK* *SIGNAL*! Sorry for yelling so loud, but I feel like a broken record when discussing this--it seems like every new HDL designer tries to use something like this to make a clock. Do not use s_clock like a c,lock. It is not a clock. It is a logic generated signal. Most FPGAs have dedicated clock logic, both PLLs and MMCMs as well as special clock buffers and routing networks, used to handle clocks. Logic generated "clocks", like this one, don't get access to this special purpose hardware. As a result, you are often queuing up for yourself a disaster when your code actually meets real hardware. The problem specifically comes to play when you try to do something like: broken: process (s_clock) begin if (rising_edge(s_clock)) then // Your design is now broken end if end process The correct way to do this is to use some form of clock enable signal, such as, divisor : process(elclock) variable div_cont : integer := 0; // This should probably also be limited in width begin if (rising_edge(elclock)) if (div_cont = max-1) then ce := 1; div_cont := 0; else ce := 0; div_cont := div_cont + 1; end if; end if; end process; process (elclock) begin if (rising_edge(elclock)) then if (ce) then // Now you can put your rate limited logic here // ... without worrying (as much) about simulation // vs synthesis bugs, or the synthesis tool doing // something unexpected end if; end if; end process; That said, nothing prevents you from calling s_clock a clock or outputting it on an output pin to examine with a scope. It's just that, using it's rising edge within your design will cause problems. Also, my apologies to all of the real VHDL designer out there for bugs I might be missing, but this is the basic concept of what you need to do. Finally, don't forget to make sure the name elclock matches the name of the incoming clock within your XDC file. It should be on the same pin that a hardware-clock comes in on. Dan
  29. If you run the rootfs config first without running a build before the rootfs config, it should build fine. mrproper is mentioned in the following Petalinux docs from Xilinx:
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