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  3. Hi @Dareamol This is actual for me too. Could you send for me tupical project of "Hello world" ? uart from procesor MIO or EMIO you receive? I wank to look your xdc file and Zynq core settings. Best regards
  4. I am getting this warning [Synth 8-6040] Register i_reg_rep driving address of a ROM cannot be packed in BRAM/URAM because of presence of initial value.
  5. I am trying to run the "Hello world" program on my Zynq 7000 family board. The issue which is happening is i am not able to see the output of the program on my Terminal. I am using the SDK terminal for seeing the output. I have already gone through some videos from xilinx on SDK and i am following the same steps as they did. One day before, it was working fine but, i am really unable to figure out what is the issue now. I am a kind of a newbee in using Viavado and SDK, so it will be really great if some one can help me out. I am using Vivado 2019.1. So these are the steps which i am following: 1) Created a block diagram in Vivado and generated the bitstream. We can see that i am using UART1 and GPIO in peripherals. 2) Then I launched SDK from Viavdo and Created a new Application project. Then i used the "Hello world" template and created the BSP. 3) I created a "Run configuration", connected my terminal, Programmed my FPGA and then Launched the program on Hardware. Please let me know if any other information is needed. Thanks Amol
  6. Hello, I'm following this video on how to interface a pmod wifi onto my board, but the error (around 8:35) still persists even after following every step. Does anyone have any idea what to do? Thank you.
  7. Hi @jpeyron Could you send for me tupical project only Zynq (without Microblaze) based of "Hello world" ? uart from procesor. I wank to look your xdc file and Zynq core settings. Best regards
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  9. I am attempting to use an Arduino uno reading 3 pots to control the Frequency Amplitude and Symmetry sliders in the Waveform generator on waveforms with the analog discovery 2. I would also like to to use a PmodKYPD to select the waveform type if possible. Is this possible and if so how might i go about doing so? Thank you!
  10. Sounds like Digilent couldn't care less about finishing what they started. I'll certainly think twice before supporting another Digilent project - if this one is anything to go by. You get half of what was promised. OpenLogger is about a useful as tits on a bull if you can't read the data you've collected.
  11. Hello, I'm trying to emulate a sync pulse from the wave gen to trigger the mso on. I tried syncing off of the start of the wave gen (fgen start) however the trigger isn't stable. Anyone have any advice on how to do this?
  12. >>thus i have a tendency to over-pipeline my design read the warnings. If a DSP48 has pipeline registers it cannot utilize, it will complain. Similar for BRAM - it needs to absorb some levels of registers to reach nominal performance. I'd check the timing report. At 100 MHz you are are maybe at 25..30 % of the nominal DSP performance of an Artix, but I wouldn't aim much higher without good reason (200 MHz may still be realistic but the task gets much harder). A typical number I'd expect could be four cycles for a multiplication in a loop (e.g. IIR). Try to predict resource usage - if FFs are abundant, I'd make that "4" an "8" to leave some margin for register rebalancing: An "optimal" design will become problematic in P&R when utilization goes up (but obviously, FF count is only a small fraction of BRAM bits so I wouldn't overdo it)
  13. Last week
  14. Hi @jpeyron That idea of Tom Taylor is good, but quality of images in article is bad, i could not to see what connector be connected( I wrote a letter to him few days ago, but don,t get any answer yet(( Best regards
  15. And what about true definition in XDC of external CLOCK and RESET, because my bitstream fall down in this two moments?
  16. Hi @andre19, I tried getting a microblaze only project going on the zedboard with it failing to launch on hardware in SDK due to issues with the reset multiple times with different block designs in vivado. I would suggest using the zynq processor with the microblaze processor for the beginning step. The hacker.io project linked above is a good example of how to get both the microblaze and zynq processor working. best regards, Jon
  17. Hi @RFtmi, You can add the HDL using the add a module function on the block design and connect the output to the input of an AXI-GPIO IP Core. Here is a forum thread that discusses doing this with another best regards, Jon
  18. The Zynq FPGA that I am looking at for an application has a processor unit and a programmable logic unit. I know how you can write a HDL code to use the logic part. For the processor part it seems that I need to use the IP integrator to get the CPU, peripherals, and interface properly configured and then generate the HDL code for it. In the generated HDL code, "HDL wrapper", the blocks are defined as modules. Then I need to use SDK to program the bit stream and program a C code for the processor (for example). My question is, if I want to have a logic (let's say an 8 bit counter) on the logic part, and then the processor and the XADC that is controlled by the processor, how can I access the output of the 8-bit counter via processors and transfer it to the PC through the USB UART port? Do I need to define another top level HDL file and instantiate the HDL wrapper plus my 8-bit counter code? My question is sort of general for now, so any example or comment would be helpful.
  19. First off you are clearly working with a board that I am unfamiliar with. Regardless, I have no way to provide a decently helpful answer to your question. I have been in the situation where I had to make architectural changes to a design ( including a completely approach ) to meet timing; especially one that needs to be incorporated into a larger overall design That uses most of the logic and memory resources and runs at a high clock rate and has multiple clock domains.. A big factor is how much of the device resources your design will use, how the logic interconnect works, how the clock routing works for your device etc. What I can say with some confidence is that you should experiment with a slower clock and scaled back design. Simulate it. Get a bitstream and look over the timing report to get an idea of path delays. Figure out how may LUTs are needed for the basic design elements. Then start scaling things up. Do timing simulation for each step as you go. It is not uncommon when working on an ambitious project to get to a conclusion faster by starting off with a few simpler preliminary design projects that help you get answers to unknowns. In engineering the shortest path (in time) between two points (start and finish) is not necessarily a straight line. It's not been my experience that you can 'fix' a design that doesn't run properly at a certain clock rate by adding a few registers here or there. Pipelining strategies, in my experience are more of an architectural holistic effort that starts with the basic elements and continues as they are grouped into larger entities.
  20. Hi @HasanWAVE Pin 14 won't work with the Arty Z7, as it corresponds to MIO 14, which is connected to the UART on the Arty Z7, rather than a button or switch. The Arty Z7 doesn't have any switches/buttons/LEDs connected to the Zynq's MIO pins. This means that to use the PS GPIO, you need to enable GPIO EMIO (extended MIO), which routes its signals through the PL. This allows you to connect and constrain the EMIO GPIO pins as you would any other GPIO interface in the IP Integrator. Unfortunately the EMIO can't be connected to the components in the board files, however, you can still make the EMIO GPIO bus external and constrain its pins with an XDC file. The EMIO GPIO is enabled through the Peripheral I/O Pins screen when re-customizing the Zynq block. You can then set the width of the bus through the MIO Configuration screen, under I/O Peripherals / GPIO. For SDK, the xgpiops pin numbers associated with the EMIO pins are assigned in ascending order above all of the MIO pin numbers - so, in the case of having only an EMIO GPIO interface with a width of 4, the pin numbers are 54, 55, 56, and 57. Note that the first 32 EMIO pins use the bank number 2, and that the way that the interrupt example creates the interrupt enable bit mask passed to XGpioPs_IntrEnable doesn't work with pin numbers greater than 31. I've attached a modified version of xgpiops_intr_example.c in the spoiler below that works with button 0 of the 4-button GPIO EMIO as described above. If you want more depth, there's some more information and references to Xilinx documentation in this thread from the Xilinx forums. Thanks for the question! -Arthur
  21. jpeyron

    JTAG-SMT3-NC UART usage

    Hi @tgvho, The FTDI drivers for the JTAG-SMT3 automatically download and enumerate as a virtual com port that can be used with standard OS's. Most terminal applications have a configuration menu for setting baud rate, flow control, etc. If not, in Windows you would open and select properties of the associated com port in the device manager. You can then set the baud rate as shown in the attached screen shot below. In Linux or OSX the driver is automatically loaded and that usage is just like any other COM port in those operating systems. best regards, Jon
  22. Thanks Zygot, I use an Axoloti board and C code my algorithm to test them and evaluate the different options (quantification, polynomial waveshaping vs sine in RAM etc...). It really helps to know how it should sound. I decomposed the pipeline in smaller entities. The architecture of each component already include fine pipelining. I try to track the clock delays involved by each architecture so that the result will be consistent. With all the elements i plan, i would say that the pipeline will consist in 20 to 30 registers. I think it will be possible to add extra pipeline registers between the components if the internal ones are not enough. Or should i implement different architectures for the same entities with different pipelining ?
  23. Hello @PrasadK, You will need to use a newer version of ISE. As per this page on our store, the JTAG HS2 is only supported in ISE 13.2 and later as well as only have Xilinx Plug-in support from ISE 12.1 and later. Thank you, JColvin
  24. The only rule of thumb that I know of for pipelining is that when the delays associated with the combinational logic and routing path delays approach the period of your clock you should add a clocked register between that stage and the next. And here is the dilemma; Until the design is synthesized, placed and routed there are a lot of unknowns. Even if stages are dependent solely on the outputs of the previous stage and not a lot of 'global' signals controlling a bunch of stages there are differences in clock edges from LUT to LUT. This might be insignificant or likely not. When trying to pipeline a very large design as you are doing things get messy. One option is to manually place logic rather than let the P&R tools do it. This optimizes delays and routing plus adds consistency from build to build. I'd suggest starting off with a clock and sub-set of the target design to see how things are going. Then scale up incrementally addressing timing closure issues are you go. As you've no doubt already found out adding registers improves performance but also adds latencies that can make identifying the scope ( in time ) of any signal relative to other stages of a design problematic. A bit of C coding might help. I would definitely suggest working out the data flow in advance rather than as a 'seat of the pants' exercise. Diagrams hep to a point. A problem with using hard multipliers in the DSP blocks is that they are scattered throughout the device and can incur substantial path delays if your design needs a lot of them. It never hurts to pore over the complicated DSP48E literature to see what Vivado handles i the background for most usages. You can use macro instantiations but be prepared to work hard. If that's what your design requires then that what you will have to do.
  25. Hello, I am really enjoying my Basys3. I already VHDL coded/simulated/tested a little SPI and a little I2S controller (connected to a AdaFruit DAC, but i will try/compare it with the I2S2 soon). Thanks to many threads on this forum (double flop...), clock domains were not such a big problem I am designing a formant/phase modulation synthesizer. It will be based on 1024 "operators" (oscillators with phase modulation, phase hard sync and many other delicacies). I use a dual port BRAM connected to a SPI controller for input parameters (frequencies and gains) and another set of BRAM for state variables (for example the phase of each operator). I am designing the "operator" processor as a pipeline (so that it will calculate the equivalent of 1024 oscillators at the I2S 96kHz sample rate). I'd like to have a rule of thumb for the granularity of the pipeline for a targeted clock frequency. (for example the number of adders or multiplexers between two pipeline registers at 100MHz or 200MHz) I browsed many documents and i did not find such a rule of thumb... thus i have a tendency to over-pipeline my design... and it makes it quite confusing. Is there some Xilinx document that gives some advice/good practice ?
  26. Hi @jpeyron I followed the procedure as you mentioned in the link https://miscircuitos.com/sinus-wave-generation-with-verilog-using-vivado-for-a-fpga/?_ga=2.106154691.1163116266.1566581309-2054910748.1538715088. But still it is working only in simulation phase but not in Hardware platform. The top module of my verilog code and XDC files are attatched. 1.txt 2.txt
  27. Hi @attila, Wow! That is really great, thanks a lot. We will directly use this on Tuesday and I will thank you with some photos and figures Best, osti
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