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  2. Hi @DomDV, Have you changed anything about your setup between when it used to work and now? Can you also enable console logging in the Settings page underneath the Advanced section, open your browser's developer tools and then include a copy of the console output in your reply of you trying to connect to the OpenScope? What is the IP address you mentioned? AndrewHolzer
  3. Hi @Joao Fragoso, We do not have a tutorial for this; the Pmod ports (at least for Digilent made boards) are tied to 3.3V logic so a normal Pmod port would not work for this. There are a couple of threads that discuss the hardware requirements here and here, with the takeaway being that you will need the LVDS capability (which at least the dedicated XADCs on the Digilent boards do not do). So it may be possible, but not likely and not straightforward to do. Thanks, JColvin
  4. Attila, thank you, this works. And thanks for pointing out the script hints in the status bar; all this time and I didn't notice them. Two additional things would make this coding environment sufficiently "complete" IMO: Within the script editor, please give us a hot key to sequence between different script tabs. CTRL+TAB would be consistent across the app. OR: If possible, provide separate simultaneous instances of the script editor so one can view and edit all script files at once. Of course, a search and replace would be great to have. It's the one editor function I truly miss. I cut, paste to notepad, and do search and replace there as a workaround. Helpful things: A way to clear the output window, other than quitting and restarting. If user accidentally closes a plot window, say PLOT1, it seems there is no way to bring back PLOT1. You have to instantiate a new plot, which will be automatically PLOT2, and manually set the axis as they were, and manually change any references from PLOT1 to PLOT2. The "safest" practice is to save everything: the individual scripts as .js, the script project, the scope project, waveform project, etc. This way, if user closes some child windows and saves the whole waveforms project that way, everything can be reassembled. Backups are good practice but one can still lose one's current post-backup work with a couple of thoughtless clicks perhaps to make screen space for multitasking. I'm saving individual things now manually whenever I've edited something. A "SAVE ALL" command would be great. Even without any of this, Waveforms + AD2 has about doubled my productivity as a consultant. And I have only begun to leverage it. So: Thank you for this great product! Two heads are useful:
  5. Today
  6. Hi @TomF, I apologize for the delay. We don't have any specific advice for you regarding merging these two Xilinx made demos; as you have found and as this particular forum user on the Xilinx forums found, changing the order in which the interrupts are initialized can help things (though why this is the case I am uncertain of since all interrupts should be disabled while you are specifically enabling interrupts...). Xilinx will be better able to address this for you. Thanks, JColvin
  7. Hi @youngpark Looks like the AXI GPIO (axi_gpio_0) connected to the module's key input is set to input only. This should be changed to output only. the connection between led and axi_gpio_1 is also a potential issue. When you connect only some pins of an interface to a module, it disables the board interface's version of those pins. What this means in your design is that clock_divider_0's output is not going to be reflected on the LEDs. From the point of view of the processor, when it reads from the GPIO, it will see the clock_divider module's output, and when it writes, it writes directly to the board's LEDs. If the intended behavior is to have the counter output to the LEDs and for the processor to be able to read the state of the LEDs, then you would probably need to use a port that is not from the board file and an XDC file to constrain it. See the images below (microblaze etc. not included). EDIT: I missed that the push buttons were also connected. They also have the same issue that the LEDs do. I have changed my screenshots to reflect how to solve the issue for both. Thanks -Arthur
  8. opethmc

    DMC60c CAN Bus

    @tom21091 is it possible to have a firmware image of the DMC60c that is not at 1MBps?
  9. Hi @wooky, I apologize for the delay. Those of us at Digilent have not specificially looked into the compatibility of the FMC Pcam Adapter with the ZCU106. I would recommend reading the compatibility sections within the FMC Pcam Adapter Reference Manual, https://reference.digilentinc.com/reference/add-ons/fmc-pcam-adapter/reference-manual#carrier_card_compatibility, to see if the ZCU106 has been designed to meet it's specific needs or not. It may be possible to port the demo design, though the material we have was designed fairly specifically to the compatible Digilent boards (Zybo Z7) at least for the single Pcam demo (I haven't gotten to look into what is available for the FMC Pcam demo) as well as one of the IP's used being tied to specific versions of Vivado and SDK, so it would not be trivial. Thanks, JColvin
  10. MIG configuration that comes from the board file only runs DDR3 at 400 MHz, while the memory can run as fast as 933 MHz, but due to the way clocking is implemented on a board I was only able to achieve approximately 900 MHz (1111 ps period). DDR3 section of the board reference page contains everything you need to know to create a MIG project yourself, or to modify pre-generated one to run memory faster. I wish the board would contain another clock source so that it would be possible to run the memory at full speed (1866 MT/s). I've used MIG a lot for my own custom FPGA boards, so I don't have any problems using it.
  11. @DanK, When I was in a similar situation, I opened the .prj files and found them to be (fairly) readable XML. From there I was able to figure out how to configure the MIG. Dan
  12. No. Unfortunately the MIG tools is a pain in the "" to use. You can't modify a design. You have almost always have to slog though every step for each iteration of a design. As I recall it does let you import pin assignments from another project. I don't know of any easy way to use the tool.
  13. Hi @ssm For such you can use the wait-run timing, like here: AnalogOut_Pulse.py You could also use the funcSquare, funcPulse or custom with this the duty will be limited by the device buffer size, like 0.025% The wait-run can have arbitrary timing, like run for 10ns and wait for 1day. dwf.FDwfAnalogOutNodeEnableSet(hdwf, channel, AnalogOutNodeCarrier, c_bool(True)) dwf.FDwfAnalogOutIdleSet(hdwf, channel, DwfAnalogOutIdleOffset) dwf.FDwfAnalogOutNodeFunctionSet(hdwf, channel, AnalogOutNodeCarrier, funcSquare) dwf.FDwfAnalogOutNodeFrequencySet(hdwf, channel, AnalogOutNodeCarrier, c_double(0)) # low frequency dwf.FDwfAnalogOutNodeAmplitudeSet(hdwf, channel, AnalogOutNodeCarrier, c_double(3.3)) dwf.FDwfAnalogOutNodeOffsetSet(hdwf, channel, AnalogOutNodeCarrier, c_double(0)) dwf.FDwfAnalogOutRunSet(hdwf, channel, c_double(pulse)) # pulse length dwf.FDwfAnalogOutWaitSet(hdwf, channel, c_double(0)) # wait length dwf.FDwfAnalogOutRepeatSet(hdwf, channel, c_int(1)) # repeat once dwf.FDwfAnalogOutConfigure(hdwf, channel, c_bool(True))
  14. zygot

    Verilog Simulator

    I've worked as a consultant or employee for a lot of companies that have years of accrued experience developing programmable logic based products that have been deployed by customers. All of them use the standard logic simulator tools. Some only use the free tools that come with the FPGA vendors' toolset. Some buy the full versions of ModelSim or other logic simulators. This isn't by accident or lack of sophistication. It's true that only a subset of Verilog and VHDL are supported by programmable logic synthesis tools. Verilog and VHDL were developed to do simulation long before the IEEE added standard libraries to them so that programmable logic vendors would adapt them for use as a synthesis source. All FPGA vendors provide documentation on what exactly their synthesis tools support for these languages. Logic simulators, even Xilinx's home grown one, support most of Verilog and VHDL. After all they are simulators! All of my testbenches use non-synthesizable Verilog or VHDL. Beginners and self-taught people often get into FPGA development with a lot of bad assumptions and conceptualizations. They also don't read the documentation provided by the vendors of the products that they want to use. I'd agree that finding good guidance on how to write a testbench is hard to come by. Beginners should start off using the minimal features of Verilog or VHDL until they've mastered those and then add to their repertoire as the gain experience. Verilator is a cycle based simulator. That makes if fast; but it's fast because it simulates a greatly simplified model of digital logic. If you're simulating a PDP11 it's a good tool. If you're simulating the latest Intel Xenon processor I'm pretty sure that you don't have a tool that has complete code or behavioral coverage. I strongly disagree that sub-clock timing isn't important to beginners. I would argue that simplifying logic design into a cycle based conceptualization is more confusing and counter-productive. There certainly are valid reason to use a cycle based simulator; even for logic design. These types of simulators are not preferred nor should they be the first option though. They are simply not capable of performing all of the simulator duties required for a complete programmable logic design flow. Use the simulator provided by your FPGA vendor. Learn basic simulator language concepts. Learn about limits of FPGA device resources and support for whatever source format you choose to submit to their syntheses tools. Most importantly, take some time to develop a basic understanding of digital design using real devices and real wires. I realize that LUT based programmable logic devices aren't a bunch of gates but the same concepts important to designing circuits with LSI and MSI devices on a PCB apply to FPGA design. If you find that ModelSim or Vivado simulator is taking too long you can adjust the sample unit of time to speed things up. A one pico-second timescale isn't necessary for most designs. You can finds ways to work around a lot of simulation time that isn't important to your analysis. All of the applications that you mention above are relatively simple designs in terms of timing analysis. At some point you may want to do something more challenging and will have to provide proper timing and even placement constraints in order to get the vendor's tools to properly synthesize and place logic so that your design will work. at some point sub-clock timing considerations will dominate the timing analysis of a high clock rate design. Verilator and SymbiYosys can't help you do that. Time based simulators can. You can only go so far with simple models of real things. My advice is to become reasonably expert with the tools recommended by the vendors who make the devices and make the tools to develop designs for. Once you have a level competence with those logic simulation tools then branch out and try other options. I would agree with anyone suggesting that Intel and Xilinx have done a poor job with code coverage, as you say, formal analysis of HDL source code. This is one area that needs to be addressed. There are companies that address this shortcoming. [edit] I forgot to mention that a lot of people resist post-route timing simulation because it often involves a bit more work. In the commercial environment where teams are working in parallel to make integration and delivery schedules having this analysis is vital to success. You need traditional logic time based simulators like the one that comes with your vendor's tools to do this. One more reason to become adept at using them.
  15. For data communications, look for a USB to DB-25 Parallel cable. (eg. link1, link2, link3) There is somewhat of a chance that Adept would recognize such a cable and you would be able to also program the FPGA through it, but we can't guarantee that. If Adept doesn't recognize that cable, you'll need to get one of our JTAG programming cables: JTAG-USB, JTAG-HS2 or JTAG-HS3 Here is a table indicating which software supports which cable.
  16. thank you Attila for the help, I am trying to generate a pulse using FDwfAnalogOutNodeFunctionSet but I did not find a function for that like funcSine, is there a way to do that other than customizing a square wave? the length of the pulse is variable calculated in the code.
  17. D@n

    Verilog Simulator

    @xc6lx45, This is a valid question, and a common response I get when recommending Verilator. Let's examine a couple of points here. Verilog is a very large language, consisting of both synthesizable and non-synthesizable subsets. I've seen more than one student get these two subsets mixed up, using constructs like "always @* clk <= #4 !clk;" and struggling to figure out why their design either doesn't work or fails to synthesize. I've seen a lot of student/beginners try to use these non-synthesizable constructs to generate "programs" rather than "designs". Things like "if (reset) for(k=0; k<MEMSIZE; k=k+1) mem[k] = 0;", or "always @(*) sum = 0; @(posedge clk) if (A[0]) sum = B; @(posedge clk) if (A[1]) sum = sum + (B<<1)", etc. Since verilator doesn't support #delay's, nor does it support 'x values, in many ways it does a better job matching what the synthesizer and the hardware will do together, leaving less room for confusion. C++ Verilator based wrappers can be used just as easily as Verilog for bench testing components. That said, ... The Verilog simulation language is a fairly poor scripting language for finding bugs in a module when compared to formal methods. There's been more than once that I've been deceived into thinking my design works, only to find a couple cases (or twenty) once I get to hardware where it didn't work. Indeed, both Xilinx and Intel messed up their AXI demonstration designs--designs that passed simulation but not a formal verification check. As a result, many individuals have posted unsolved bugs on the forums, complained about design quality, etc. (Xilinx has been deleting posts that aren't flattering to their methodology. I'm not yet sure about Intel in this regard) Formal methods tend not to have this problem. Why waste a student's time teaching a broken design methodology? So, if you aren't using Verilog for your bench test, then what other simulation based testing do you need? Integration testing where all the modules come together to interact with the hardware in some (potentially) very complex ways. At this point, you need hardware emulation, and Verilator provides a much better environment for integrating C/C++ hardware emulators into your design. My favorite example of this is building a VGA. VGA's are classically debugged using a scope and a probe since the definition of "working" tends to be "what my monitor will accept." The problem with this is that you lose access to all of the internal signals when abandoning your simulation environment. On one project I was working on, this one for the Basys3 where there was a paucity of memory for a video framebuffer, I chose to use the flash and to place prior compressed frames onto the flash. I would then decompress these frames on the fly as they were being displayed. My struggle was then how to debug decompression failures, since I could only "see" them when the design ran from hardware. Verilator fixes this, by allowing you to integrate a display emulator with your design making it easier to find where in the VCD/trace output file the bug lies. Another example would be a flash simulation. Most of my designs include a 16MB flash emulation as part of their simulation. This allows me to debug flash interactions in a way that I doubt you could using iverilog. This allows me to simulate things like reading from flash, erasing and programming flash--even before I ever get to actual hardware, or perhaps after I've taken my design to hardware and then discovered a nasty bug. More than once is the time where I've found a bug after reading through all 16MB of flash memory, or in the middle of programming and something doesn't read back properly. I'm not sure how I would do debug this with iverilog. A third example would be SD-card simulation. I'm currently working with a Nexys Video design with an integrated SD card. It's not a challenge to create a 32GB FAT based image on my hard drive and then serve sectors from it to my running Verilator simulation, but I'm not sure how I would do this from iverilog. So far in this project, I've been able to demonstrate an ability to read a file from the SD card--FAT system and all, and my next step will be writing data files to it via the FATFS library. I find this to be an important simulation requirement, something provided by Verilator and quite valuable. Finally, I tend to interact with many of my designs over the serial port. I find it valuable to interact with the simulation in (roughly) the same way as with hardware, and so I use a program to forward the serial port over a TCP/IP link. I can do the same from Verilator (try that with iverilog), and so all of the programs that interact with my designs can do so in the same fashion regardless of whether the design is running in simulation or in hardware. Yes, there are downsides to using Verilator. It doesn't support non-synthesizable parts of the language. This is the price you pay for getting access to the fastest simulator on the market--even beating out the various commercial simulators out there. Verilator is an open source simulator, and so it doesn't have the encryption keys necessary to run encrypted designs--such as the Vivado's FFT or even the FIFO generator that's a core component of their S2MM, MM2S, and their interconnect ... and probably quite a few other components as well. This is one of the reasons why I've written alternative, open source designs to many of these common components. [FFT, S2MM, MM2S, AXI interconect, etc.] As to which components are "better", it's a mixed bag--but that's another longer story for another day. Verilator does not support sub-clock timing simulations, although it can support multi-clock simulations. At the same time, most students don't need to know the details of sub-clock timing in their first course. (I'm not referring to clock-domain crossing issues here, since those are rarely simulated properly anyway.) Still, I find Verilator to be quite a valuable choice and one I highly recommend learning early on in the learning process. This is the reason why my beginners Verilog tutorial centers around using both Verilator and SymbiYosys. Dan
  18. Hi @P. Fiery Thank you for the observations.
  19. @HonzaMat, May I ask if there's something in particular you need to do for which you wanted these pins? Perhaps there's another way to do it. If it's high speed communication with a host, that can be done via the network. The Arty does have a nice network port you can use. Dan
  20. Hi @P. Fiery 1. The loading of undocked window position seems to be working. The size might be adjusted from too small window to preferred dimension. This adjustment will be removed in the next version. 2. Solved. 3. Yes, open/save file is like import/export. 4. When there is only one file in the Script the tab-bar is hidden, like it was in earlier versions with no multiple file option. This, to simplify the interface, to have more space for editing. The next app version will notice when any modification is made to the script code and ask to save changes or not. The script is kept in the workspace (project) since is intended to be used to automate the instruments. It is likely to be usable only with the given instrument setup. The workspace can contain everything that is needed for a project in one portable file: instrument setup, imported audio files, custom waveforms, reference waveforms, instructions in rich text View/Notes, scripts, notes on plot... It is always a good practice to have regular backups with any project (software, document, WF workspace...) If you want to load and run external script you can use the "-script" argument: > "C:\Program Files (x86)\Digilent\WaveForms3\WaveForms.exe" -script myscript.js The script editor is not too powerful, but you can use the Ctrl+Space or have View/ Code completion activated, to browse the available objects-functions.
  21. @Ana-Maria Balas, thank you for your reply. I believe this thread can be marked as "solved", then. Not sure if I can do that myself or only moderators do.
  22. Did you press the PROG button to flush out the data to the SD card before removing it as described here?
  23. Hello @zygot, I asked my colleagues from PCB design about this issue and as soon as they give me an answer I will get back to you. Ana-Maria
  24. Thanks for the quick answer. I completely missed that option. It now works as expected.
  25. Hello @HonzaMat, Yes, that part of the circuit is proprietary design. However I can say that pins BDBUS2 and BDBUS3 are not connected, so unfortunately you can't access them. Cheers, Ana-Maria
  26. Hello @TeslaCrytpo, Here is the step file for CMOD S7 : CmodS7.step However you need to compare it with a physical board to see if it's 100% accurate. Some of the components from the step file may not have the real dimensions as the ones that are physical placed on the board. Have a great day, Ana-Maria
  27. Hi @FRESI Notice that the "Relative to Channel 1" is by default checked, which means Oscilloscope Channel 2 is measured relative to Ch1 reading. If you want to measure absolute (Vpeak/Vrms) or referenced (dB,X,%) to Wavegen amplitude value uncheck this option.
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