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  3. Hi J, Thanks for your prompt response. I assume that would be a cable like so: https://store.digilentinc.com/2x6-pin-to-dual-6-pin-pmod-splitter-cable/ I've never programmed a MCU before. I assume it shouldn't be too hard to write code to bind the peripherals to the MCU pins, I hope.
  4. Yacov Cohen

    AD7193

    Please let me know if there is a solution to work with 8 inputs on AD7193. In the past you tried to find a solution
  5. Hai, bitstream generation is successfully completed when i add few lines of code in my previous xdc to the latest one you provided. And i got output on display. but i m not sure whether this is the correct one.
  6. Last week
  7. I believe that there is a bug in that particular version of the dvi2rgb decoder. A workaround would be to just set the TMDS clock range parameter to ">= 120 MHz". Alternatively, you could replace the core in the project's repo folder with the latest version of that IP, which has resolved that bug, found in this ZIP. Thanks, Arthur
  8. This error is likely related to the rgb2dvi IP. Please send a screenshot of its configuration (see below).
  9. thanks for the reply but now i got error while implementation error. error snapshot attached.
  10. I am interested in the digital pattern generation feature. Can it take data from an ascii test file, one byte per line and output/play it to the IO? If yes, can I specify the clock rate at which this data from the file will be played out? Thanks.
  11. Looks like the project was just missing constraints. I am unsure what the root cause of the problem is, but I managed to generate a bitstream. Download the attached XDC file and add it to your project. Thanks, Arthur Zybo-Z7-Master.xdc
  12. Is it possible to decode scope data using one of the "protocols"? I often need to analyze scope data as inverted UART data (e.g an RS-232 async serial signal).
  13. I will update this thread as I find any other software issues when using the Analog Discovery2 with the Cora board. I expect that I will continue to have Cora programming issues and if I find any resolution, I'll post.
  14. Hello! Just tested it with simplest settings (attenuation 1X, 50 ns/div, zero signal). Only offset on the screen is changed. Scope1 ... Scope3. 1. It happens only with second channel. 2. When offset is [-2.34V ... -1.76V]. 3. At the borders noise is like a rare peaks. At the center like as an ADC input is overloaded. 4. Peaks values are -7.6V & +7.6V. Scope4. 1. Offset -4V 2. But signal is not zero, it is +2V. So it became to the same "- div from the center". Peaks are -5.6V & + 9.6V -> shifted +2.0V. 1V/div, 2V/div, 5V/div - the same situation. Why I am so cycled about calibration. Scope1 LG offset is -0.325 V. Scope1 HG offset is -0.0296 V. Scope2 LG offset is -0.300 V. Scope2 HG offset is -0.0274 V. So signal -2V can be on the edge between "Low Gain" & "High Gain". But because offset is quite big (15% of ADC input, may be damaged?), algorithm can not choose the right gain and generates peaks on switching. By this theory lowest border of the noise is -2.35 V - 0.3 V = - 2.65 V. If signal lower then this it works fine with "Low Gain". A bit upper there is "gray, turbulent zone". And greater than -1.76V the stable zone of "High Gain". With best regards, Mikhail. peaks.dwf3work
  15. Hi @GeorgeMina, Yes, you may attach one Pmod to the top row of the 2x6 header and the other Pmod to the bottom row of the 2x6 Pmod host port; you will need to use a cable of some kind though since the Pmods won't both physically fit on top of each other, but there is nothing electrically preventing you from doing this. I am not familiar with the Nebula board you mentioned, but you should be able to program it such that each Pmod is controlled separately. I don't know if there are any nuances with this particular board that you would have to consider (such as the Pmod port is only compatible with SPI Pmods). Thanks, JColvin
  16. Most connectors have very short insertion cycle specifications; unless they are expensive and specifically made to endure a high number of insertions. Having made that statement I will say that I have to maintain at least 4 tower and 2 laptops to support all of the obsolete tools and drivers that I've accumulated and still need; and I have yet to identify 1 USB port that has gone bad. My main Win7 delvelopment PC is as old as, well.. Windows 7 is. It's not a bad idea to invest in a few USB hubs. They are a lot cheaper than PCs. There are reasons for doing this even if you aren't worried about connectors going bad. I recently destroyed ( well I haven't bothered to take the time to figure out what the problem is ) a USB HUB while developing a FT232H project ( this is a lot easier to do than you might think) ; glad that it wasn't one of my motherboard USB Host Controllers... I generally keep USB cables plugged into development boards when not being used. I've had a number of USB connectors rip off of such boards. In particular, if you have any development board with a USB connector lacking thru-hole shield ground tabs I guarantee that sooner or later it will come off with the end of your cable. One way to mitigate this is to apply some epoxy around the connector before using such a connector. I do this as a habit. I've found that most USB micro or mini cable connectors require a high insertion force, and that's if you are trying to plug it in correctly; some are worse than others. Zygot rule for the day: "Break cheap stuff, not expensive stuff". Corollary: "You are going to break something sooner or later". [edit] I should have specified that by USB HUB I mean self-powered USB HUB.
  17. Hi @PaulW Good to hear it is working and thank you for posting the solution. The problem could have been with the Adept Runtime version. The Xilinx SDK installing/downgrading to an older version of this. The WaveForms also installs/uses this Runtime and due to frequent releases contains the latest version. The Xilinx processes may remain in background, blocking access to devices. In this case you could kill the hanging process from TaskManager or reboot.
  18. Well, I'm back up and running. For what its worth, this is what I did: 1. Uninstall Waveforms, then reboot PC 2. Re-install Waveforms 64bit, then reboot PC 3. Start Waveforms in safe mode - it worked. Then started Waveforms in normal mode - it still worked. Not sure what the problem was but I'm back up and running.
  19. hi, the link for the project attached https://drive.google.com/open?id=1hlaMs-wpVEnfhxweX5hLNWDSwtAgCoI8 As i have only the licencse of vivado 2017.4, so I can't do it in 2018.2. Thanks,
  20. I have been using Analog Discovery2 and Digital Discovery for over a year now with Waveforms and it has always worked as expected. Recently we started an embedded project using one of the Cora boards. I have noticed sporadic problems with Waveforms when I have both the Analog Discovery2 plugged in and the Cora board plugged in (to USB.) Problems such as the Xilinx SDK not being able to program the Cora board and Waveforms not being able to see the Analog Discovery2 module. Now, I have gotten to the point where I cannot even launch Waveforms at all. It just hangs, I don't even get to the demo mode screen. I have tried uninstalling and then re-installing both the 32-bit Windows version and the 64-bit Windows versions of Waveforms and neither works - they both hang, not allowing me to even see the demo screen. I don't even have any hardware (Cora or Analog Discovery2) plugged into the computer. It seems that perhaps my registry has been messed up. Do you have any app notes or suggestions on what I can do at this point? I sure would like to use Waveforms My system specs: Intel i7-7700HQ CPU at 2.8GHz, 16GB RAM, 64-bit operating system, x64 based processor Windows 10 Pro, version 1709, OS Build 16299.1087 Any help is much appreciated. Been searching the forums for similar topic and have not found any yet.
  21. Hi, I have a Nebula Rev 2.0 board, which has an on board pmod host (2x6 pin). Is it possible to connect 2 pmod modules to it? These are the modules of interest: https://store.digilentinc.com/pmod-amp2-audio-amplifier/ https://store.digilentinc.com/pmod-mic3-mems-microphone-with-adjustable-gain/
  22. Hello, I have been trying for a while to run this PCAM 5c demo example that is provided by Digilent on a Zybo z7-20 board: https://github.com/Digilent/Zybo-Z7-20-pcam-5c The demo uses Vivado 2018.2 version, however I have been trying to execute it on the 2019.1 version. I am very new to FPGA and VHDL. I followed all the steps mentioned in the demo perfectly and did not receive any error. Although, after opening the project in the 3rd step, a pop-up window informs that the project is of the older version and I checked the option of automatically upgrading the project to current version. After the project opens, there is another pop-up to Report IP, I tried both the options individually i.e. Report IP and Ignore. It did not give any error in any of the following steps. But, the screen displays just a moving colour pattern and I am not able to communicate to camera module via UART as suggested in the demo. To summarise, all the steps mentioned in the demo were performed but the camera module is not working. I am unable to see the UART communication channel. I also tried following the instructions to use digilent github demo projects: https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start However, this uses the 2016.4 version. I used the SDK Handoff method and again faced the same problem. Kindly suggest possible solutions to make this demo work on 2019.1 version or tell me what have I been doing wrong. Thanks.
  23. Ely4

    pmodBLE

    Hello, I want to use a pmodBLE with another pmodBLE. I understand it doesn't need software configuration of the Bluetooth link. For this, I have to enter a command mode while connected to the PmodBLE through UART with the pmodBLE's first 6 pinouts, haven't I? Once in command mode, the device can connect to any BLE address using the “C,0,<address>” command. But how can I know the address of the pmodBLE? Does anyone have an example? Can you help me? Thanks and sorry for my english, Ely.
  24. Have you verified that DDR is working properly? https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Problems-about-XAPP1026-on-KC705/td-p/698600
  25. Hi @rwodnick Pulses might be hidden by sampling with any capture device. Like a 10ns pulse will be rarely visible with 1MHz (1us) sampling, 1% chance to catch. Select the Noise option to use half of the buffer to store pulses/glitches that might be hidden by the current sampling rate. See DIO 24 below. This option is supported by each device: Analog Discovery 1, 2, AD Studio, Digital Discovery, Electronics Explorer. With Repeated and Scan capture modes the sample rate is adjusted automatically based on time base. These modes are intended for scope-like operation, like timing analysis. Use the Record mode for traditional logic analyzer usage, to capture more samples and analyze data/protocols.
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