All Activity

This stream auto-updates     

  1. Past hour
  2. Hi @hmd, I'm glad to hear that the command which vivado helped you find the path needed to complete the installation. Thank you for sharing what you did. best regards, Jon
  3. Today
  4. I bought an Analog Discovery 2 on 8/23/17. I used it my first year for labs. I stopped using it from December ,2018 till April 2019. When I went to go use it a week or two ago, it would not work. Waveform would not recognize it. The led would not light up when plugged in. I tried using different cables and on different computers to test out if it was just a connection issue. Any feedback on what can be done to help fix this issue is greatly appreciated.
  5. Dear friends! I solved the problem. To me everything was competently explained by the great expert Mikhail Korobkov. He is an employee of СTС "INLAYN GRUP". Problem reason: the name of the computer cannot be written with the Russian letters. The subject is closed.
  6. It's hard to tell why the files aren't being added without seeing your exact setup (recipes, config files, etc). One of the causes for "not a dynamic executable" is some missing libraries, but there could be other causes. I saw you also posted on Xilinx's forum. The fact that it works in 2015 but not in 2017 indicates some changes were made in how Petalinux deals with adding components. Have you checked the differences in the user guides between 2015.4 and 2017.4? Check the sections about adding components and Appendix G: Obsolete Features. Other than that, Xinlinx devs can comment better on why it wouldn't work in 2017.
  7. bogdan.deac

    OpenCV and Pcam5-c

    Hi @Esti.A, If you clone the repo you obtain the "source code" for the platform and you have to generate the platform by yourself. This is a time consuming and complicated task and is not recommended if you do not understand SDSoC very well. I advise you to download the last SDSoC platform release from here. You will obtain a zip file that contains the SDSoC platform already build. After that, you can follow these steps to create your first project.
  8. Esti.A

    OpenCV and Pcam5-c

    Hi @bogdan.deac, 1.The version I am using is 2017.4. 2. I cloned from git directly from the link. I resolved the problem by manually defining the location of the bd. loading it again and introducing every line in the TCL console.
  9. Hi everyone, I am planning to use Pmod IA AD5933 with Arduino or raspberry pi for impedance measurement in single excitation frequency (50 kHz or 100 kHz) over time. before starting, I would like to know what is the fastest measurement speed (maximum impedance sampling rate) I can get with this board in a constant AC frequency. does anybody have experience doing this? best, Mahdi
  10. bogdan.deac

    OpenCV and Pcam5-c

    Hi @Esti.A, 1. What Xilinx tools version do you use? 2017.4 or 2018.2? 2. How did you obtain the SDSoC platform? Did you clone from here or did you download the archive from release tab?
  11. Hi @PeterFromSwe The Protocol /I2C accepts only 7bit address.
  12. I check if on the 3.10.9 wersion thanks for adding this functionality to the software Regards Roland
  13. I was poking around and seem to have found a solution, the correct path for me starts with /tools, not /opt. I found this by typing "which vivado" into the terminal (not sure why I didn't think to try that sooner). Once I found that I was able to complete the installation, and can now connect to the board. Thanks for the help!
  14. I ask to help! I have successfully no Synthesis in the environment of Vivado 2018.2. I need to study creation of projects for FPGA. I downloaded from the website xilinx.com a Vivado 2018.2 package for 30 days (for the Windows_7_64bit) and executed installation on the laptop. Chose WebPACK configuration. I create simple projects (the head module and the testbench module) and SUCCESSFULLY I carry out Simulation. But further I should do for the Synthesis project and then Implementation. But Synthesis is not carried out successfully. And, at start of the project on Synthesis, the following prevention appears: The proposed launch directory is non-default and will reduce the portability of this project. Do you wish to proceed anyway? I click OK, but quickly Synthesis comes to the end with the message about UNSUCCESSFUL performance. Still specification: I do not create the module of Restrictions. Also I tried to obtain the full license for 30 days, but as to make it on the website xilinx.com - unclear. But, maybe, at me not in the license business! I ask to explain to me: as to me to achieve performance of successful Synthesis.
  15. Jon, I think the USB UART bridge would work for me. I shouldn't need more than 1Mbaud. I'd use it to transfer the contents of block RAM to/from PC. A few seconds to transfer the data seems fine. As xc6lx45 suggests, it would be a good idea to transfer in Hexscii so I can add a simple command set to control the process. Looking at the Arty Z7, I see a different problem. That board doesn't have an FTDI controller. I see that instead the board has a TI USB Phy and uses the USB controller embedded in the Zynq 70x0. In that case, is there any way at all to transfer application data over USB with the PL? This isn't a show stopper for me. I don't think I'd benefit much from having ARM CPUs for this application. Thanks for all your help! Allan
  16. Yesterday
  17. Hi @kwilber, Thank you for sharing. This book looks awesome! cheers, Jon
  18. Hi @vttay03, I have not been able to be able to get the Hello world template to work with the QSPI flash with either the Arty-A7 35T or the Arty-A7-100T in Vivado 2018.3. I will keep looking into this issue with Vivado 2018.3. For now I would suggest using Vivado 2017.4. I was able to complete and verify the Hello world template project into the QSPI flash on the Arty-A7-100 using Vivado 2017.4. I attached some screen shots of the programming setting in SDK. Also the offset is 0x003D0900 since the HW platform size is the same as the Nexys 4 DDR which has the same FPGA. best regards, Jon
  19. Hi , I am using DDS IP core to visualize a 5 kHz sine wave signal. At first I simulated the IP core using Vivado simulator . I used 25 MHz clock signal. I got a sine wave signal as shown in the first attached picture. When I changed the Radix from "signed data type" to "unsigned data type" the sine wave will be like in the second attached picture. And when I implemented my design on my ARTY 7 , and connected the output of Pmod DA3 to the oscilloscope , I got a signal similar to that in the second attached picture ! As shown in the third attached picture . I changed all the intended data types in my program from u16 to s16 but the no thing is changed ! Pls , I am looking forward your help. How to visualize a DDS sine wave properly using Pmod DA3 ? Thanks.
  20. For those interested, Xilinx has just made a new Zynq MPSoC ebook available here.
  21. Hi @GMA, Yes, the standard micro USB cables will be sufficient, so long as they are not charging only cables. If you're looking to transfer data at high speeds, you may want to also look into getting a USB certified cable for better results. Those of us at Digilent have used standard cables (such as ones that come with phones to charge and connect to your PC) without issue though. Let me know if you have any other questions. Thanks, JColvin
  22. Hi Jon, Thanks for your quick response. Do you think a regular Cat5e would do it or it would need cross over?
  23. Hi @hmd, I opened my VM and looked opt/ from the root directory. It has the Xilinx/ directory. I think it would be best to uninstall and re-install Vivado an leave it to default settings. Make sure that you are root while installing Vivado to insure there is no issues with permissions. best regards, Jon
  24. Hi @PG_R, I do not have much experience connecting two FPGA's together through ethernet. Initially I do not see any reason that you would not be able to connecting these boards together through ethernet. I would suggest using the Petalinux project for the Zybo Z7 to facilitate the ethernet. best regards, Jon
  25. jpeyron

    Genesys 2 DDR Constraints

    Hi @SeanS, @JColvin response was also my thoughts based on the screen shot. The color scheme of the MIG page attached looks like ISE. I am glad that you are now able to get the MIG default setting to be pre-set by the board files. best regards, Jon
  26. Both ZCU102 and Zybo Z7 use RGMII protocol, can they be connected merely with a Cat5e? Any anticipated issues? Thanks,
  27. Hi @hmd, Change directory(CD) to the root directory and run the command s -l there. Its been a little bit since I have played around with Linux in my Virtual machine. I believe the OPT directory is there. Sorry about the mis-information. best regards, Jon
  1. Load more activity