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I write and maintain the ZipCPU blog. What questions do you have? Dan

@attila Would it be in the realm of possibility to be able to run more than 1 pattern generator at a time? If not, is there any way to make different signals in a single pattern generator have different durations. The screenshot below shows 2 different patterns that I would like to run for different durations. Both are triggered off the falling edge of the same signal, but there "Run" time needs to be different. If there is not a direct way to achieve this result, is there some sort of workaround or alternative method that you can think of?

exactly. I've read the different articles but I still have some grey areas, which is why I'd like to know if anyone has any ideas to shed some light on the subject.

I wouldn't do it differently. Just to make sure: You have selected the jumper JP5 for the JTAG boot, right? I have the Zybo Z7020 board and Vivado & Vitis 2023.2 installed. If you share here your Vivado and Vitis projects, I will try to run them on my board.

Hi, I am trying to track down the source of a spurious signal that seems to be present in the FFT that's just above 700kHz - that manifests regardless of whether the Wave Generator is looped to the Oscilloscope or it is left open circuit or even terminated in a short or 50hms (no probe) It does not seem to be related to anything in my lab - turned off every source I could think of - obviously the PC is still on, and USB is connected to the ADP3450. The spur looks suspiciously like a switch mode switching frequency of a smaller regulator. What is also telling is when I do add a signal into the mix - it looks like there are other products that pop up - almost like intermodulation products around it. Is there a switch mode in the AD3450 that could be to blame? Appreciate any suggestions before I go digging around. Cheers, Chris

Hi, I bought two ADP3450 units last year, and have some questions concerning performance. I have a couple of questions I am hoping people can help me with :-) 1) I am generating 100kHz sine wave, 2V (4Vpp) from the wave generator, with 0 V and then 2.5V DC Offset. When I look at the output with scope probes (1MOhm) in the same digilent - they look ok - effectively unterminated. When I load the Wave Generator to it's specified characteristic impedance - I get a half voltage drop across the source impedance, and the waveform looks correct with both 0V DC and 2.5V DC bias offsets set in the Wave Generator. However, when I load the output down with 50Ohms - the DC likewise is reduced BUT the sinewave clips so that the positive of the sine wave starts limiting. I interpret this as meaning the wave generator output does NOT support +/-5V? Is this performance correct - or have I got faulty units? 2) The Harmonic Distortion seems high - higher than I expected, with most products between 60-70dB down. The noise floor measured seems quite high too ... around 70-75dB. this is with a 100kHz sinewave. What performance should I be expecting - FFT noise floor wise - can someone send me some example figures or technical data concerning SFDR expectations, THD, and noise floor for the Units ... both for the wave generator and the scope? Thanks heaps in advance! cheers, Chris

THE FACTS: I just unboxed Digital Discovery, down loaded Waveforms, plugged in DD to USB. Waveforms recognizes DD in a New Workspace, but there are many buttons missing from the column on the left, including the Scope and Wavegen buttons. -The Digital Discovery's LED shines blue until Waveforms starts up the the LED turns green. -Waveforms shows DD in its device manager, and the Supplies, Logic, Patterns, Static IO, Protocol, and Script buttons all appear. -But the Scope, Wavegen, Logger, Network, and Spectrum buttons do not. I would greatly appreciate any thoughts. Are there versions of Digital Discovery that just don't have those features? Thanks in advance!

Hi @rpatel, You may leave the pins open and unconnected; the UART pins all have pull-resistors implemented so that they are not floating: Let me know if you have any questions. Thanks, JColvin

Yeah, you have to provide timing exceptions to Vivado. They belong in your XDC file. For example, consider this line: set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/GEN_ETHERNET_DECODE*u_netpath/rx_afifo/rgray_r*}] -to [get_cells -hier -filter {NAME=~ thedesign/GEN_ETHERNET_DECODE*u_netpath/rx_afifo/rgray_cross*}] 3.0 This is used to tell Vivado that the FIFO's read gray code will be read in a second clock domain into the signal rgray_cross (i.e., read gray code, but crossed clock domains). Rather than doing proper timing analysis on this signal--which would fail because the two clocks are unrelated--the statement instead tells Vivado to call this clock domain crossing "passing" if from the time it takes to set the first signal to the time it takes to set the second can be done in less than 3ns. There are other ways to do this as well. They all end up being timing exceptions that you have to declare in your XDC file though. You can let Vivado be the one to tell you which signals need exceptions like this--subject to your review. Dan

I have a device connected to my Digital Discovery device that is supposed to read SPI data. I am using it to verify the output from a debug console command that sends an address value (byte) and data (2 bytes). When I am reading back the data, the data is often missing values. I can often retrieve the values and "fill in the blanks" and get the correct values but at other times, the data is mangled to the point that it's not useful. For example, when an expected 0x23 for the address is presented, 50% of the time I am retrieving that correctly. The rest of the time, the incorrect values range from: 14, 22, 30, and 62 (0xe, 0x16, ox1e, ox3e) respectively. Similar slips are happening with the data. When sending 0x1234, I can often receive from the logic analyzer, 0x0934 . The retrieval is through python. The DUT's SPI clock is 15 MHz, and the Digilent's clock frequency is 80Mhz. Any suggestions? Thoughts?

Please see my attached vi below; it updates FirstPortA/D0. ULx boolean write.vi

Hello I'm now working on a project involving FPGA development, and I'm facing an issue with clock domain crossing. I'm trying to synchronize signals between different clock domains, and I'm facing timing violations. I've tried using synchronizer circuits, but I'm still having trouble there . Does anyone have suggestions for handling clock domain crossing in FPGA designs? Any advice would be greatly appreciated! Thank you

JRys - This example works - no errors. This example requires me to write a value for all DOs, is there a way to write a value to only a single DO?

I'm not familiar with LTL specifications. That said, there's some content on the ZipCPU website about formal verification of AXI interfaces that may help?

I think you may be misreading the XADC spec. It says that the XADC is powered by the 1.8V vccaux bus. That is not the same as saying the pins should be configured for 1.8V digital logic. It appears you have to give it the same digital IO standard as the other pins so the tools don't freak out, as in Viktor's example.

Hello @GSAS - Karthick. Thank you. The A/D channels will acquire synchronously based on the sync bus connection, but there is no guarantee of any loss of data based on the unique application described. Please elaborate more on the customer's concern. Regards, Fausto

Hello Fausto, I will get the sensor datasheet shortly. If the cable lengths are of the same length, can we guarantee there won't be any loss of data?

Hi Attila, Do you have an example of how to do this?

Hi Viktor, Yes,unfortunately. 1) Created Vivado project for Zybo z7020 2) Block Design added 3) Zynq processor added 4) block automation runned 5) FCLK_CLK0 -> M_AXI_GP0_ACLK connected 6) Design wrapped as HDL 7) Bitstream generated 8) Hardware design output generated ----------------- Vitis opened 1) Vivado project folder seletced as workspace 2) Create App Project 3) XSA file added as platform 4) Hello World application selected 5) Built platform 6) Built application 7) debug as hardware (I see the green LED on board lights up) ----Nothing happens---- I used putty to see if I can sent/recieve serial data

@attila That is a fantastic feature, just tested it and it works well!

Hello @Ludger Breil. What is your buffer size? Is it (2AIN + 1DIN) * 640,000 samples/sec = 1,920,000 samples/sec? Is the data processed on a different thread during the acquisition? Is the acquisition running continuously 24*365 or does the acquisition stop and restart periodically during each day? If the acquisition stops periodically during the day, is restarting the application an option? It is not possible to determine the root cause of your issue, since the error is sporadic. Based on the error message, the buffers are not cleared fast enough before the new data comes in, hence the overrun. Try increasing the number of buffers to 10. Regards, Fausto

I'm updating an old (2004) control system which used a 8051 processor and an Altera FPGA It was a single board bespoke design and I dont want to go through updating it with prototypes etc. all the external IGBT drivers and input conditioning would remain Basically I have 2 input bytes 0-255 that need to produce output pulses to switch some IGBT switches One is 10 microseconds per bit the other 20 microseconds per bit with a space between each of 5 microseconds So beasically producing a square wave. The FPGA needs to repond to faults and shut down the system no more than about 20 IO So looking for a single board that I can piggy back onto a redesigned main board It will be a steep learning curve for me but used to it Any suggestions please

Hello @GSAS - Karthick. All analog input channels of the four DT9857E devices can be synchronized using the Sync Bus. Note that the RJ45 cables connecting the Sync Bus on each device must be less than 1 foot in length. Therefore, all four devices should be at the middle point between compartments. All cable lengths between all four DT9857E devices to their connected sensors should be the same length. All channels will acquire data simultaneously at the set sampling rate. What is the application's sampling rate requirement? Given the number of analog input channels and high sampling rate capability, a new robust Windows system (i.e. latest processor, high RAM, minimum background processes running, USB 3.x) and a custom application developed with the Open Layers API is recommended. The maximum achievable sampling rate is dependent on the ability of the host system to process the data. What are the sensors to be used? Please provide their datasheets. Regards, Fausto

Hello, do you need additional information? Is it likely to be a hardware or a software problem? Could it possibly be fixed by upgrading Matlab and/or Open Layers? We require synchronous input/output channels for our research projects and can not sacrifice the second output channel. Kind regards, Domme

any one can help me invalid command name "ps7_init" error in sdk for above project