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  2. Is it possible to use digital signals in addition to analog channels with the data logger (Logger) tool in WaveForms? I know this is possible with the Scope tool. However, I want to use digital signals generated from a MCU to delimit windows in long-running captures. Is it possible to access digital channels from a script using a function?
  3. Today
  4. zygot

    PCIE on CMOD-A735T

    In general the T designator for Xilinx devices indicates that it has transceivers which are required for PCIe. This doesn't imply that all boards using a transceiver equipped part can implement PCIe or even use the transceivers. The CMOD products are not suitable for doing transceiver based designs. I have the Diligent Genesys board that has a Virtex 5 FPGA device with transceivers and they are unusable for a variety of reasons. You should read the reference manuals for Xilinx PCIe as well as the application notes and other information that they provide to learn about FPGA based PCIe.
  5. Szia @attila, Would you consider adding support for raw PCM or RIFF WAVE as export file formats? Both supports 32-bit floating point datapoints too if you preferred them.
  6. Hi @jpeyron, ok, thanks. Just let me know if you find out something. Best regards, Toni
  7. @AndrewHolzer Could carry all your instructions : 1. I am not running any VPN. 2. Work exclusively with WiFi only and no cable is plugged into the RJ45 Ethernet port. Yet went ahead and set the priority metrics for WiFi as 1 and Ethernet as 2. 3. Localhost pings fine with no issues. 4. Attaching the console out after doing above. Now I got a message saying No Response. ( In this i see a large chunk of warning in red. ) 5. As ever, could connect after I invoked the Airplane mode but of course only on default profile settings. Waiting for your further instructions. If its working with so many other people it should for me also !! Thanks for your time. Raghu
  8. Charles Li

    PCIE on CMOD-A735T

    Hello, I am trying to use the 7 Series FPGAs Integrated Block for PCI Express v3.3 ip on my CMOD A7-35T, which has a xc7a35tcpg236-1 on it, but the ip does not show up on the ip catalog. I speculated it was because the ip does not support this part, but the device seems to meet the Minimum Device Requirements listed in the ip documentation (albeit only x2 and Gen 1). Googled around a bit and didn't find anything. The documentation even specifies the xc7a35tcpg236. When I try out other devices, the ip shows up https://www.xilinx.com/support/documentation/ip_documentation/pcie_7x/v3_3/pg054-7series-pcie.pdf Thanks ahead of time!
  9. asd123

    Nexys A7 not working

    I tried connecting it to a desktop and with another USB cable but it still did not work. I don't have access to a power supply to see if turns on.
  10. I was trying to use the scope to measure the voltage drop across a resistor for a lab exercise and I was getting the strangest readings. I finally figured the problem might be with the AD2 and tried to measure the voltage across a 1.5V AAA battery. The AD2 indicated there was a -19 mV across the terminals of the brand new battery? Is it possible my scope is damaged? I tried using channel 1 and channel 2.
  11. Yesterday
  12. Hi @Kobi18210, Sorry for the delayed response. We do not have a project that directly transfers data through the ethernet. We have used the echo server project which should be similar process as with this tutorial here. I have attached an altered echo.c file as a potential reference. Another option would be to use an embedded linux platform like petalinux here. best regards, Jon echo.txt
  13. Hi @Sami Malik, Can you attach a screen shot of your bram IP Core setting and memory addresses for the bram. best regards, Jon
  14. Hi @Yacov Cohen, Unfortunately that is correct. I kept hoping that I would find time to be able to look into and debug this issue and be able to present a clean working project for the Pmod AD5. I did get it setup so that multiple AD5's could be used (by declaring different constructor name) in the same project. I'm sorry I could not be of more help. Thank you, JColvin AD7193.zip
  15. jpeyron

    SOUNDS WITH VHDL

    Hi @eray, @hamster's MPU6050/Basys 3 is a good start to an interesting project. I would suggest converting audio files to a coe file using something like matlab or a prython script. Then in vivado is a bram with the coe file. Here is a xilinx forum thread that discusses this. best regards, Jon
  16. Hi @birca123, I reached out to one of my co-workers which happens to be currently having a similar issue with the Video Timing Controller on their project. We will be looking into this further but currently havent found a cause. We also would suggest to reach out to Xilinx about the Video Timing Controller hanging as well. best regards, Jon
  17. Hi, I have a Zybo Zynq-Z7-10 board with PMOD PCam-5C I tried the steps in the replies: https://forum.digilentinc.com/topic/17074-pcam-elf-on-petalinux-from-sd-card/?do=findComment&comment=42504 https://forum.digilentinc.com/topic/17074-pcam-elf-on-petalinux-from-sd-card/?do=findComment&comment=42698 I setup as well a microSD card 8G using gParted: first partition 1GB type fat16 and the second partition 6.80GB type ext4. After inserting the card in Zybo's slot and switching the jumper to SD , the effect of switching on is that the board lights on the LED red LD13 PGOOD, the connected HDMI Monitor has not signal. I have some questions: which resolution has the HDMI output in Petalinux? The bitstream file of Z7-20 Vivado project with the modifications of the diagram and PWM https://github.com/Digilent/Zybo-Z7-20-base-linux - how does it get inserted in the Petalinux binaries that get on the SD card? I guess using this command --- petalinux-package --boot --force --fsbl images/linux/zynq_fsbl.elf --fpga images/linux/system_wrapper.bit --u-boot ---- but there is no interdependency set in the previous posts. Should the project run and the HDMI display connected to the output of the Zynq must run even without the bitstream ? The microsd card was formated with gParted, is compulsory using of a dedicated tool to write the rootfs, boot.bin files ? or the commands: cp BOOT.BIN image.ub /dev/sdd1/ is enough ? https://github.com/Digilent/Petalinux-Zybo-Z7-20?_ga=2.177147622.2104787184.1555966017-216103582.1546520870#configure-sd-rootfs sudo umount /dev/sdd2 sudo dd if=images/linux/rootfs.ext4 of=/dev/sdd2 sync sudo resize2fs /dev/sdd2 sync should be enough?
  18. Hi @benl, You should be able to determine what version of firmware you have on the OpenLogger, but going to the Device Manager (main page where you can select the actual OpenLogger or a simulated version), and going to the Configuration Menu for the actual OpenLogger and selecting the "Update Firmware" button under the Firmware section. There you will be able to see the current version as well as be able to select and download and update the OpenLogger to the latest version, which is currently 0.1807.0. I asked another one of our engineers more familiar with the WaveForms Live about this, and while it is technically working (I was able to get it to run for awhile before encountering the same errors as you), latencies introduced by the network cause WaveForms Live to fall behind, producing the errors that we are seeing. They let me know that this can be alleviated by throttling the sampling rate so less data needs to be transmitted between polls. In the future, they are thinking of adding a method to have WaveFormsLive resync with the OpenLogger, but they do not have the time to implement this right now. As for logging errors, you can do this by going into settings (in the upper left dropdown), open the advanced dropdown, change change the logging behavior to have the console log be stored on the console; by default it's set to none. You can then view the error log in the Chrome Dev tools (control shift J) and going to the console tab to view what is being printed to the log. Let me know if you have any questions about this. Thank you, JColvin
  19. Hi @SGY, You could realistically use any version of Vivado to program the Zynq chip on the Zedboard, though some of the projects will expect certain versions of Vivado and Xilinx SDK to be used in order for the projects to work the first time without any modifications. As for the pin requirements, it depends what GPIO functions you need. There are 4 Pmod ports on the Zedboard that are not constrained to any particular usage, but otherwise the Zedboard has 8 switches and 5 buttons as well. However, this only adds up to about 45 GPIO, so the other unassigned GPIO are present on the FMC connector. However, depending on what application you need for your GPIO, you may be hard pressed to find a FMC card that suits your needs. What sort of simple controls are you hoping to do? Thanks, JColvin
  20. Hi @sbellamy, If you are referring to the pins in the schematic, those names tend to be based on what Xilinx dictated the pin names for the Zynq. Otherwise, I would recommend looking at the Avent User Guide that is on the Zedboard Resource Center. Digilent doesn't make the KC705, but it has it's own user guide from Xilinx here that also explains the pin assignments here https://www.xilinx.com/support/documentation/boards_and_kits/kc705/ug810_KC705_Eval_Bd.pdf. Thanks, JColvin
  21. Hi @hearos, Are you using the SD card reader that is on the Nexys 4 DDR or a Pmod SD or Pmod MicroSD on pmod port JA? If you are trying to us the SD card reader on the Nexys 4 DDR then you will want to use the onboard Micro SD Slot under external memory on the board tab. I have attached a screen shot of this. If you are using a Pmod Sd or Pmod MicroSD on port JA you should not need a XDC to constrain these pins since the boards files along with the vivado library IP's configure this for you. best regards, Jon
  22. Hi @Cuikun LIN, Here is a forum thread that discusses Labview and AD2 sample code. Here is a forum thread that discusses the WaveForms Runtime/SDK which can be accessed from LabView directly without Python which is on hackster.io here. The provided examples in the SDK are mostly in Python which you might be helpful. best regards, Jon
  23. Hi @mikeWylie, Unfortunately we have not used the AD9114-DPG2-EBZ with the AD-DAC-FMC-ADP-ND adapter card. FMC's on our boards like the Nexys Video are designed to meet the 57.1 spec. The Nexys Video has a low pin count(LPC) FMC. I would also suggest contacting Analog Devices to get their input as well. best regards, Jon
  24. Thanks Jon - I was stuck and will give this a shot immediately! Reagards, >>Eric
  25. Hi @JColvin, I think I have the correct raster operation - ropScrPaint which 'ORs' the source and destination - as this works fine when both bitmaps are at the same bit depth. So, I think this is indeed expected behaviour. Thanks very much for looking in to it.
  26. @mikeWylie The DAC that you want to use is an older device and uses a DDR interface, so there's hope. I've posted on this type of question numerous times in answer to numerous questions similar to yours. You can see my list of EVM's that I've found useful in the Technical Off-Topic Useful EVMs for FPGA Development Boards post that I started ( I'll update or respond to posts to queries on that post as needed ). I've posted more specific guidance in answering other similar questions but don't have the time top track them all down.... unfortunately, it's difficult to steer people toward a previous post that might answer their questions. The short answer is that you have to trace though all of the signals from the EVM through any adapter boards and through the FPGA development board that you are using to make sure of connectivity. When there are no SERDES involved things are easier and more likely to be possible from a clocking point of view but you still need to make sure that your IO pins have compatible standards. The adapter will complicate timing closure, and depending on signal routing might make an interface much more complicated. Make sure to trace though all power and ground pin assignments. Lastly, and most importantly, make sure that clock signals into or out of your FPGA are assigned to clock capable pins. This commentary is not exhaustive. If you really need one or two channels of high speed DAC or ADC and don't have a big budget to work with I suggest looking a Cyclone based FPGA board with HSMC connectors. Terasic is a good place to look. Opal Kelly has a few Syzygy options for high speed ADC/DAC applications. Otherwise, options are bleak. Trust me that I'm always on the lookout for high sampling rate ( > 10 MHz ) analog <--> digital development platform options. In my post for using EVMs with FPGA development boards I mention the Terasic De0 Nano/LTC1668 board combo that I've found to be useful. Just because a mezzanine card uses an FMC connector that doesn;t mean that it's usable with any FPGA board having an FMC connector. There are two possibilities here that will work: Read the schematics and work out all of the details for yourself before buying anyting Use the advice of a trusted source who has successfully done what you want to do and then do option 1 anyway. You are ultimately responsible for everything. Keep in mind that since the FMC is a high speed interface there's no safety net for boo-boos.... you get it right or the odds are very high that you will destroy your FPGA board.
  27. Hi @mufasir_qureshi, Welcome to the Digilent Forums! Could you attach all of the HDL. Can you be more descriptive about your project. best regards, Jon PS- one of my first verilog SPI controller i missed assigning the signal as an inout. Instead I had assigned it as an input.
  28. I currently have the Nexys Video Artix-7 FPGA board. I can see that the board has the high speed connector that can plug into the AD9114-DPG2-EBZ (https://www.digikey.com/products/en?keywords= AD9114-DPG2-EBZ ) with an adapter card - AD-DAC-FMC-ADP-ND (https://www.digikey.com/product-detail/en/analog-devices-inc/AD-DAC-FMC-ADP/AD-DAC-FMC-ADP-ND/2700515). My question is, how do I find out if the evaluation card (AD9114) with adapter board is compatible with the development kit? Analog devices says the evaluation module will work with any DPG2 compatible board, but I can't seem to figure out if the Artix-7 development kit is DPG2 compatible.
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