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Hi @Mike4354 Here the Logic Analyzer detector is set to trigger on DIO 24 falling edge and Pattern Generator outputs a 100ns low pulse on DIO 25 with 200ns (20 cycles @ 100MHz) + Wait time delay. You could adjust the system frequency to change the delay, 250ns (20 @ 80MHz) + With ROM logic the delay is lower, 80ns at 100MHz (DIO 26 is used as state bit) Reducing the ROM frequency will result in delay uncertainty, but delay could be achieved with further state bits.

Do you mean that you didn't see any output on a terminal connected to the appropriate COM port? Have you tried debugging the program? If you are able to step over commands in the program, then the PS works, and the board is not kaput. Occasionally, I have problems seeing UART output from PS programs on my Windows 11. It's usually an intermittent problem and I wasn't able to pinpoint the root cause. Try PuTTY. For me, it's usually the most reliable terminal app.

I did the test with recv_buffer able to hold up to 4M words (still way below the theoretical limit of the DMA 26-bit max.). When I tried a single packet of words_per_packet==2,000,000 , only the first 1,805,843 words were transferred correctly. Then 16,248 zeroes followed, and then the correct values continued (although I did not check the very end of the 2M buffer; it's possible it was corrupted the way you experienced). I was surprised to see the very same behavior with packets==2, words_per_packet==1,000,000 , and with packets==4, words_per_packet==500,000. With packets==1, words_per_packet==1,805,843 , everything was transferred correctly. I did this test as part of my research for a project in which I want to try sampling a long series of data from Zynq 1 Msps XDAC. It seems, 1.8 seconds is the limit when using Xilinx AXI DMA IP.

If possible, could you plug it into another computer and make sure the power switch is set to 'on.' If nothing lights up, then the board is probably broken. It's hard to say what happened; it could be that a static shock took it out or that it simply failed. In this case, you can use the forum's private message and send me the serial number, purchase information such as an invoice or order number, and your shipping address.

Could you try our example? Open the Generate Values LLB library in \National Instruments\LabVIEW 2022\Examples\ULx\Digital\. The example's front panel has eight buttons, so select the eight lines of FirstPortA.

Detect falling edge of DIO. Drive another DIO low for Y cycles, X clock cycles later. For reference I am using the Waveforms software in conjunction with the Digital Discovery. I would like to perform the following using the digital pattern generator. Set up a DIO as an input and detect a falling edge on this signal. Once this falling edge is detected, I would like to drive another DIO low for Y clock cycles, X clock cycles later. This is depicted below. I couldn't figure out a way to set this up in hardware using the settings in the Waveforms software. Started going down the path of setting this up on the ROM logic, basically making a truth table to enter into the state machine when DIO 1 goes low and create X states using a binary counter that would result in still holding DIO 2 HIGH, followed by Y states using a binary counter that would result in holding DIO 2 LOW, then set it HIGH again until the next falling edge of DIO 1. I did use the SDK to try to achieve the same result, but running this logic through software seems much too slow. Would like a response within 100 to 200 ns if possible. Is this realistic? I'm hoping there is a simpler solution to this, so wanted to ask if there was an easier way to achieve this goal before heading down this path.

I suspect you forgot to constrain the pins used by the PmodAD1_01. Go to Sources, select Constraints, and add a constraints file. Open the file and copy the constraints below. Please pay close attention to the ja_pin#_io numbers, as they are not in order. ## Pmod Header JA set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja_pin1_io }]; #IO_L17P_T2_34 Sch=ja_p[1] set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja_pin2_io }]; #IO_L17N_T2_34 Sch=ja_n[1] set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ja_pin3_io }]; #IO_L7P_T1_34 Sch=ja_p[2] set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { ja_pin4_io }]; #IO_L7N_T1_34 Sch=ja_n[2] set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja_pin7_io }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3] set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja_pin8_io }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3] set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja_pin9_io }]; #IO_L22P_T3_34 Sch=ja_p[4] set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja_pin10_io }]; #IO_L22N_T3_34 Sch=ja_n[4]

Hi @SpinWizard 1. Adjust the format, channels and frequency according your hardware specs or requirements. The autodetection of this is not working due to the software abstraction layers. 2. Higher voltage rating would require different protection, certification, costs.... 10x probe increases the voltage range but above 50V with 1x can damage the device. 3. I'm not sure I understand what you are asking for. Do you need digital multimeter with USB and software support ?

Hi @fr.bernardo You can change the CS in SPI/Custom, but make sure to have pullup on these keep the unused ones idle, or you can control from Script tool the SPI and StaticIO. You could also have common CS/CLK and separate MISO, supported only by SPI/Spy. In SPI/Custom separate calls are needed like with different CS, eventually calling ReadQuad for 4 sensors and unpacking the bits.

Hey @SpinWizard This is actually supported out of the box, not as a separate instrument, but as a separate device that works with most of the non-digital instruments like Scope and Wavegen as-is. It's at the bottom of the device manager list: Thanks for the feedback! Arthur

I am using a PCI-DAS6025 and CIO-SERB-24/FD with LabVIEW 2022 on a Windows 10 machine. The AO seems to be working fine. The DO results in Error 42: ULx Write (Digital Bool 1Line 1Point).vi<ERR> Digital port not configured correctly for requested operation. Any advice would be greatly appreciated. Block diagram and InstaCal screenshots attached.

Hi @attila, I got the code and sensor working with the following code, returning status bits, raw value and pressure data from 1 sensor. I now want to move towards applying the sensors to its final place and for that i want to learn 2 things: As the code is prepared it returns the pressure everytime I click on 'Execute'. I want to be able to press something and it starts recording to a .txt or .csv file for a given amount of time (30s for example). I want to connect up to 5 sensors at the same time and write information from all into the file mentioned above. From what i understand i can do this by sharing the the GND, Vsupply, MISO and CLK pins, and have a different Slave Select for each sensor, activating 1 at a time. Can I do this in the 'Protocol Tab' under the 'SPI/Custom' tabs or do i have to use the 'Script' Tab or even some other software? If i can make this in the Waveforms software, where can i find an example of something similar working ? Thanks in advance!

Problem is now solved. The FPGA can be detected by the XPC USB II debugger. I am not using the USB2UART bridge. I just use a separate 5V DC power supply to ensure that the bridge is not activated and the debugger is directly connected to the JTAG signals at J13.

Additionally... If I change the Jumper at JP5 to set Programming Mode = JTAG (instead of default mode, QSPI Flash), will I be able to see the FPGA as device detected through the JTAG interface (J13) at Vivado Lab? Is this the way to do it?

Yes No, Don't own the higher end units. Yes No Yes No I'm actually a new user to Digilents offerings and haven't had a need yet to use an SDK. With respect to the last two questions: Right now I'm happy with the 2230 and its bandwidth, Sampling rates needs vary. As far as current and future needs there likely is a need in the future for more channels and even better isolated channels. Ideally more channels with out a significant loss of sampling rate. Realistically though my interests are more industrial so extremely high bandwidth / sampling rates are seldom needed. In any event more channels, including a trigger channel go a long ways. As for features or improvements, in all honesty I'm a new owner and have not had a lot of exposure yet. However that has never stopped me from making suggestions: (realize I'm a new owner / learner) PC's these days almost always come with some sort of "Sound Card", I'd like to see these used via another instrument that is always available and can handle basic oscillator duty. In fact you can literally call it an Oscillator instrument though most sound cards can do better. Now I realize that we have the WaveGen Instrument but I look at this as additional capability and frankly parallel capability that does not interfere with the channel to the Analog discovery. A higher voltage range on a per div spec. This would make the platform even more useful. Add supported external DVM's instead of or in cooperation with the Analog Discovery. These days that means a USB interfaced DVM's. The idea would be zero effort implementation on the part of the user, even if that means a limited number of DVM's. You can never have too many DVM's available and sometimes you need the safety of system multi meter. I will likely have more to add as I learn about the hardware and software. I'm especially interested i how the logic instrument works with slow electromechanics.

I pretty much have to agree with the first post in this thread, the need to have an account to install and keep up your installed software is Extremely anti consumer. It is unfortunate that Digilent has gone this way. In fact I'm going to suggest going in the opposite direction and make life even easier for your users. In this regard use Home Brew for Mac Software support. For Linux setup an RPM repository for Fedora and possibly some of the lesser distros. Why? Simply because it makes keeping a computer up to date and your customers will love you for it. I suspect that what Digilent and their marketing people, don't realize is that too much non sense drives people to other companies. This includes excessive marketing crap but also things that just get in the way like diving through hoops to update a piece of software. Keeping your software up to date on a computer should be effortless using accepted methods. Please realize I'm a new customer of Digilents, I'd like to be a long term customer but I'm left with the impression that the ownership by National Instruments has infected the company with BS that educated engineers and technicians don't want to deal with. Effectively the markets NI and Digilent server are not the same and what is good in one domain really sucks in another.

Interested if you could post your solution here. It would be helpful to maybe put an example of how to snoop on and analyze traffic on a can network. Thank you for your time

The only caveat being what you've said just above the quoted - just because you connect a device directly to a USB port of a motherboard, it doesn't mean that this is actually a root USB port and not merely one of ports from onboard USB hub. This is not so bad for USB 2.0 as most hub chipsets I've came across had no problems processing nearly full USB 2.0 bandwidth at line speed, but things get a lot dicier with USB 3.x hubs and multiple USB 3.x devices. But since USB 3.x hubs actually contain two separate hubs (one for USB 2.0 and below, and another one for USB 3.x), a USB 3.x device can coexist with USB 2.0 device(s) without any interference because these two standards use physically separate channels for communication (and two separate controllers inside chipset/port controller). Given the question in the OP - since UART doesn't come anywhere near saturating USB 2.0 bus, (infact it won't saturate even USB FS at 12 Mbps), I don't see the problem. Unfortunately there is another "but" - if you use some sort of UART over USB-JTAG adapter (like Digilent's HS2/HS3), there are known cases when they refuse to work when connected through certain hubs. I'm not entirely sure if it's a hardware problem or a software one (or a combination of two), but it does happen sometimes, and in this case user will need to connect those adapters directly to motherboard USB port.

Hi @NAOUZ, Unfortunately, Digilent does not have a version of the Nexys A7 that is able to be powered over both USB as well as being able to accept an external power supply in the 7 Vto 15 V range. Thanks, JColvin

Hi @Mohammad Alsmadi, I have zero experience with neural networks and don't know what kind of neural network you are thinking of (it sounds like some version of a PID controller), but I suppose in theory if you trained the neural network elsewhere and then fit it within into the Linux image for the ADP3450 and set up to either: - access either the WaveForms SDK API functions directly - access some script that separately runs the WaveForms SDK then feeds the received buffer data to the network and then in turn adjusts some parameter through the SDK API - read a saved file containing pre-recorded data then it could presumably work. The ADP3450 only has 512 MB of DDR RAM, so you'll probably be limited in the amount of processing you can do while also running the Linux OS and whatnot. Thanks, JColvin

Hi @linc With the 50 V range, the resolution decreases, so a larger hysteresis may be required to reject noise. Use the easier to use acqmodeSingle. The record is only required for streaming for captures longer than the device's buffer size. Use newer software version which provides simple capture up to 128M samples for ADP3X50

Hi @rjratnip See the manual and examples, like Device_Info.py

Hi @digility, A hub will only become a problem if the USB traffic back to the host computer (whether that's UART or JTAG or your keyboard/mouse or whatever) becomes congested and you end up losing samples (or if your hub cannot provide sufficient power to all of the connected devices). A lot of computer motherboards have internal USB hubs for their multiple USB ports (albeit potentially with controllers for each connection depending on the setup). I have two USB hubs (out of necessity) for the collection of Digilent devices that I have at my work station. If I know that I am going to be streaming a lot of data at a rate that can't afford to have dropped packets (or that is going to saturate the bandwidth of the hubs connection back to the host computer), I'll just make sure that I let that device have a direct connection to the host computer so it is not competing with other devices for bandwidth. But using a device with a USB 2.0 connection, a keyboard, and a mouse on some hub should realistically not be a problem, as keyboards and mice are pretty "light weight". I don't quite understand your use case of communicating with the FPGA over UART while also configuring the FPGA as that would reset the entire FPGA (unless you're doing partial reconfiguration that doesn't touch the UART portion?) Thanks, JColvin

I have a Rev D Arty Z7. After reading your post, I walked through the Zynq Server guide using Vivado 2023.1 and did not experience the same trouble. Older Arty Z7 boards use an older Rev Realtek PHY chip and should work as is with Vivado, whereas new boards require a patch to the LWIP Library. To patch your system, use the attached file and overwrite: C:\Xilinx\Vitis\2023.1\data\embeddedsw\ThirdParty\sw_services\lwip213_v1_0\src\contrib\ports\xilinx\netif\xemacpsif_physpeed.c, assuming you have 2023.1. Could you walk through the Zynq Server guide using one of your new boards to see if you can get the echo server working with the update to the LWIP Library? xemacpsif_physpeed.c