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  3. So you have working fixed point RTL (sounds like quite an achievement BTW) and want to hook it up to the Microblaze. I'd look for info how to implement an AXI lite slave. Vivado has several built-in options to help with that - not necessarily the best way, depending who you ask, but it did work for me. For example "Tools / Create and package new IP / create a new AXI4 peripheral". Finish the wizard, then take the Verilog file with its implemented dummy registers and continue editing it by hand. My first step would be - plain registers for input data - a write-sensitive registers for the final input data word or a dedicated "control / start" word that resets/starts the processing state machine and clears an "output-is-valid" bit - a register for the first result that blocks on read for "output-is-valid" from the state machine - plain read-only registers for the remaining output data The control flow of the program is simply "write data, read results, repeat". I'd sell this as "minimum-size approach"... It can be improved in many ways (e.g. output-side FIFO, input-side FIFO, pipelined processing in RTL, full AXI / stream, ...) depending on your specific requirements e.g. throughput, bus utilization, avoid blocking the CPU.
  4. Hi, I'm a beginner of FPGA. I'm trying to print some messages on PmodOLED when pressed a key on PmodKPD. For example, when I pressed key "1" on PmodKPD, the Pmod OLED displays, "You pressed key #1", when I pressed key "9" on PmodKPD, the Pmod OLED displays, "You pressed key #9", and so on. I don't know how to program in Xilinx SDK, in particular, how to map Pmod interface or pins. Any sample code available? I'm using PYNQ-Z1 board, PmodKYPD for PMODA port, and PmodOLED for PMODB port. Thank you, in advance, for your great help.
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  6. Kaitlyn, Its good that you responded as you are the face of the AD2 as there's no one better to talk to. It comes down to knowing your users and what their needs are. I do prototyping and my needs varies. I bought the AD2 because it covers the full gambit of potential test features I could be faced with. For me everything is short duration in learning new tools to complete a project is important. Being able to find general information, principles and logic helps to ease the learning curve. Tutorial makes it easier. Sometimes a few tweaks on a tutorial is all that's needed. If it were me, I would create a list of expected uses for each feature operation (Scope, Wavegen,Supplies......etc ]) Within each of those feature operations I would pick the most common uses and then divide them in to 3 levels of complexity. That way a user can manage their learning curve. Get a hold of Microsoft Viso and use the flowchart to create a visual procedure of the tutorial. Use the flowchart it to create your video and refine it. The flowchart should have every step wire, connection, setting performed. When you are ready have co-workers to test the tutorial and identify potential roadblocks. This is the most important step. Observe their test as any trouble they encounter will most likely be encountered by an actual user. Resolve and note the roadblocks in the tutorial and release. Your objective is to have anyone at any level carry out the tutorial to completion. We all want easy....... Complaints without solutions is called crying. I've got to get back to work.... Good luck Inobu
  7. Hi OvidiuD, Yes, that works very well, thanks. Dave
  8. Hey Inobu, Thanks for the feedback on the videos! There is some additional documentation on the resource center here that you might find useful: Do you have any specific ideas on videos or documentation that you think might be helpful? I want to create the most useful documentation possible so I love to get requests and feedback directly from users. Kaitlyn
  9. Hello, I am working on lwip webserver in vivado 2018.1. The code for the webserver is in C language. I want to create a dynamic webpage that displays the value of the 32-bit system register according to my application. I came across the lwip documentation that uses an example for the web server. However, it is in 2014.3 and that creates a problem when I use it in 2018.1! Also, there is memfs folder in it that contains the .js, .css files and all! The example creates some image.mfs in ddr memory location! In my case, I have created a const char [ ] that has html code inside and I pass it in tcp_write( ) and the web page gets displayed! It works. I have also created javascript code in the html code itself that dynamically changes the content on the webpage through button onclick event. However, I want this to be change using the C variable in my code. So, how do I link the C global variable or local variable to the javascript? In simpler way, I tried to declare a global variable say UINT a=10. Then, on button onclick event, when javascript is executed, I tried to change the content on webpage using the variable "a". But it doesn't work! Does anyone knows how to make my C code and javascript code work together? For reference, I am attaching the html and javascript code below: const char testdata[]= "<html> <body> <button onclick=\"start()\"> Start the countdown </button> <p id=\"demo\"> This the main page for the test application of the web server...</p> <p id=\"ch1\"> Change me with variable a...</p> <div id=\"bip\"> </div> <script> var counter = 10; var intervalId = null; function finish() { clearInterval(intervalId); document.getElementById(\"bip\").innerHTML = \"THE END!\"; if(counter == 0) { var xhttp = new XMLHttpRequest(); xhttp.onreadystatechange = function(){ if(this.readyState == 4 && this.status == 200){ document.getElementById(\"demo\").innerHTML = this.responseText; }} }\"GET\", \"ajaxinfo.txt\", true); xhttp.send(); } function bip() { if(counter == 0) finish(); else { document.getElementById(\"bip\").innerHTML = counter + \" seconds remaining\"; } counter--; } function start() { intervalId = setInterval(bip, 1000);} </script> </body> </html>"; I want to replace any <p> element with a global variable that will be declared in the C code that has this html code inside a const char array as shown above. Any help is highly appreciated. Thanks,
  10. Attila, this seems fine so far and thank you for this great work. The "all files" button in the search bar executes a "replace all" across all open script files. I discovered this when I had the letter "i" as the Find argument and nothing as the Replace argument. Clicking 'All Files' deleted all instances of the letter "i" in both my script files. Logical, but yikes. Perhaps both "Replace All" and "All Files" should include a "Confirm?" interaction? Nothing seems to be broken in this latest rev. I'll be using this every day for the next while. Thanks again!
  11. Time to expound on the support video. Specifically the AD2. Search "analog discovery 2 tutorial" on youtube and the results yields your quick start videos. Those videos are basically a verbal mouse overs. The AD2 is on the Higher end of the price spectrum so user created videos are limited. The only way to increase users/sales is product awareness associated with easy of operation. The tutorial tasks should be at lower mid level complexity as this product users is not going to spend $300 to test a blinking LED. Its all about support and how easy it is accessed. Inobu
  12. Before attaching any FMC mezzanine card to any carrier, particularly yours, the first step is to know what Vadj IO Bank voltages are supported by your carrier board. Then, you have to go through the schematics of board boards to make sure that pin assignments will support whatever IOSTANDARD you need. Never assume that the FMC standard or connectors indicate compatibility of carrier and mezzanine cards. Even if someone tells you that they've used a carrier and mezzanine board combination the onus is on you to verify everything. Again, the fact that the connectors on two boards can mate doesn't imply functional compatibility.
  13. JColvin, Thanks for the response. I am using the Arty Z7 -20. I would like to apply this to other Xilinx Zynq boards that I have here at work like the ZC706. I will take a look at the tutorials. Thanks. Tim
  14. Hi @elodg, I know you're a lot more familiar with the physical and electrical aspects of the MIPI CSI-2 interface; could you clarify with more accuracy than I can provide about the physical layer? Thanks, JColvin
  15. Hi @timseverance77, I'm not sure which board you are using, but did you look at the tutorial Jon linked here as well as this tutorial here? Thanks, JColvin
  16. JColvin

    DMC60c CAN Bus

    Hi @opethmc, The engineer who wrote the firmware is out of the office until next week; we will be able to let you know then if that is something that can be readily done. Thanks, JColvin
  17. @rivermoon, Go for it, and good luck! I've found that wireshark was very useful when debugging network interactions. Let me take a moment and suggest you look into it and try it out. Also, I'd love to hear back from you regarding your success when everything works like it should. So often these forum posts only discuss problems and we never hear successes here. That said, it's your call what you want to share. Dan
  18. @Jess, While I've done VHDL before, it's really not my strong suit so I'd love to see some VHDL designers step in at this point. That said, you should never need to instantiate a flip-flop (FF) on your own. The tools should "just do it" for you. In particular, your code snippet (below) does exactly this: divisor : process(elclock) variable div_cont : integer := 0; begin if (rising_edge(elclock)) then if (div_cont = max) then temporal <= not temporal; div_cont := 0; else div_cont := div_cont + 1; end if; end if; end process divisor; Both div_cont and temporal will be implemented with FF's. That said, I'm not familiar enough with VHDL to catch the subtleties here. For example, I've never seen something set *after* the end of the if (rising_edge(clock)) block but still within the process. This might be a bad thing, or might not, I'm not sure. The other thing to be aware of is that in spite of its name s_clock *IS* *NOT* *A* *CLOCK* *SIGNAL*! Sorry for yelling so loud, but I feel like a broken record when discussing this--it seems like every new HDL designer tries to use something like this to make a clock. Do not use s_clock like a c,lock. It is not a clock. It is a logic generated signal. Most FPGAs have dedicated clock logic, both PLLs and MMCMs as well as special clock buffers and routing networks, used to handle clocks. Logic generated "clocks", like this one, don't get access to this special purpose hardware. As a result, you are often queuing up for yourself a disaster when your code actually meets real hardware. The problem specifically comes to play when you try to do something like: broken: process (s_clock) begin if (rising_edge(s_clock)) then // Your design is now broken end if end process The correct way to do this is to use some form of clock enable signal, such as, divisor : process(elclock) variable div_cont : integer := 0; // This should probably also be limited in width begin if (rising_edge(elclock)) if (div_cont = max-1) then ce := 1; div_cont := 0; else ce := 0; div_cont := div_cont + 1; end if; end if; end process; process (elclock) begin if (rising_edge(elclock)) then if (ce) then // Now you can put your rate limited logic here // ... without worrying (as much) about simulation // vs synthesis bugs, or the synthesis tool doing // something unexpected end if; end if; end process; That said, nothing prevents you from calling s_clock a clock or outputting it on an output pin to examine with a scope. It's just that, using it's rising edge within your design will cause problems. Also, my apologies to all of the real VHDL designer out there for bugs I might be missing, but this is the basic concept of what you need to do. Finally, don't forget to make sure the name elclock matches the name of the incoming clock within your XDC file. It should be on the same pin that a hardware-clock comes in on. Dan
  19. If you run the rootfs config first without running a build before the rootfs config, it should build fine. mrproper is mentioned in the following Petalinux docs from Xilinx:
  20. Hi @P. Fiery The next version fixes some bugs and it is also available for 32bit WinXP:
  21. when you say D-PHY physical layer do you mean resistor R46 to R56 in page 2 of Zybo Z7 Schematic ( ?
  22. @D@n Thank you for that, but, the thing is, I don't really know how to write a code in VHDL. It is a school proyect and we are not really taught VHDL properly. This is what i've got so far. this for the clock divider this for the flip flop and I am stuck with the counter I want to call the flip flop, but i dont know what is wrong I want them all to share the clock divider, but i dont know how I don't even know if the flip flop actually needs the clock. If you could help me correct this i would be extremely grateful.
  23. @rivermoon You'll figure it out. Pouring through texts, on-line content and example code will help clarify what's involved. Once you figure this out you can step back and make a fresh analysis of what it is that you want to do and how to do it simply. I doubt that you need a full client server implementation on both boards; but since you mention website it sounds like you'll need to figure out a lot of stuff before you system meets your goals. As I mentioned before, if you can set rules for the conversation and limit the scope of the network only a few packet types and limited functionality need to be used. It's hard to make that assessment if the basic concepts are fuzzy. If you intend to expose your application to the web I hope that you'll educate yourself about security issues. The vast majority of companies that sell internet connected products do an extremely bad job at this, to everyone's detriment. Implementing most things for educational purposes is great. Deploying systems with some capabilities imposes a responsibility that not everyone is willing or able to accept. If your hardware operates in a limited universe you can have complete control over what it does. If you don't have complete control over what it's doing, well... I'll let you complete the thought.
  24. Bogdan, How would you modify your sequence above if I wanted to use the SPI FLASH instead of the SD card? Thanks. Tim
  25. Hi @zygot Thank you I will definitely follow your advice and looking for your help Best Regards Uzmeed
  26. Hi, I recently bought an OpenScope MZ. I understand that the buffer size which can be visualized is limited to 32640. I want to sample 70 ms of time. So I would need to buffer 210000 samples (at 3 MS/s), which is not possible, obviosly. Is it possible to readout the buffer several times programatically so that I can somehow read 70 ms of data at 3 MS/s? So I dont want to use Waveforms Live but write a program to do that myself (Python).
  27. Hi @josejose, There is a Digilent Design Contest project, the winners from this year. They made a project that controlled a Zybo Z7 over Internet. It was a platform for students to prototipe and test their HDL design. The project it's a bit more complex; they segmented the memory and allowed multiple users to access different peripherals of the board at the same time. It's very well documented so you might find some things to help you there. The project works and you can contact them over github if something is unclear. Here is the git repo and here is the documentation. Maybe it can help you. Bianca
  28. Attila, thanks again, this is just great. I'm sure everyone using script will welcome these features. I've used most of these new features for a few hours now. Within the Waveforms app itself everything seems to be fine, but saving and exiting exhibit the following misbehavior: The waveforms app crashes during exiting. I didn't check closely enough to see if it saves the project before crashing. The previous "save project" and "save .js" functionality works correctly. However, the new "save all" item does the following: It asks for a folder, and writes to this folder my two script tabs out under the names I'm using. No problem. However, the next time I do this, the result is shown below. "Functions" and "Main" are meant to be pairs within one code version so of course the copy suffix should match. Upon the third use of "save all", nothing at all seems to happen on disk. In the "bug or feature?" department, pasting text into the new Find: <text> search feature immediately causes the first instance of the text to be selected and highlights all other instances in the script tab window that has focus. Note that this first search occurs consequent to the paste, not due to clicking "Next". (Not really a problem, perhaps it's the more efficient behavior. ) Switching to the other tab again automatically selects the first and highlights the remaining instances of <text> found there. If user searches for something else in the 2nd tab window, this different text is found as expected. However, upon returning to the first tab the original <text> is still highlighted. This may be good and useful behavior. Initiating another search clears the highlight. Finally, the "All Files" toolbar item is part of the search suite, but it seems to do nothing at all, not even in the context I detailed just above. CTRL+F invokes "find" - great! And upon CTRL+F any text in one's copy buffer is pasted into Find and instantly found. Perfect! I discovered child windows in the script editor can be surfaced or hidden with a right-click in the upper menu area. Plot1 was there, unchecked so that's all good. Clearing the output window - ah, relief, thank you! With these features, I found working on a complex script to be fast and efficient. Oh: FYI. I'm running Windows 7 still. It's fully updated, but it's not Windows 10. I will be making this project portable soon on a Win 10 laptop. (I dread having to move my desktop to Win 10. I have so much software on this machine and it all works perfectly. Some is older XP engineering software that is second-nature to me now. Alas.)
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