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  2. Hello all, Needing some guidance, we integrated the DT-9847-3-1 analyzer in to our test systems but the DT-9847-3-1 is no longer manufactured. Was our understanding that this model was manufactured in Hungry, is it possible it is still available outside the US? We rely on the 24 bit 216 Ks/s specs on this analyzer for our testing as well as the quality signal and immunity to outside noise, is there an alternative to the DT-9847 still available? We have searched but cannot seem to locate one, we have tried other manufactures with the same specs only to find them inadequate, slow, addons required and inherent to unwanted noise. Please, Any support would be greatly appreciated.
  3. Today
  4. Does anyone have a technical resource with experience with TC and the Measurement Computing application that is willing to assist on site in Chula Vista / San Diego area? Please advise.
  5. Hi Arthur, I was able to generate the project following the example at https://digilent.com/reference/programmable-logic/guides/zynq-servers?_ga=2.132423246.1936083739.1710846565-1774928201.1710252575/. Cant test is as we just ordered the boards. One issue I keep thinking of is the fact that we have packets that are about 1400 bytes big coming in every 300 hz or so on a serial interface then we have to take them and send it out on the ethernet port. Same going the other say. In the above design it looks like the PS is able to receive a packet (which I am assuming is one character) and echo it back via the echo.c: err = tcp_write(tpcb, p->payload, p->len, 1); As the comment in the code says, we assume that the payload is < TCP_SND_BUF. I am not sure the PS can handle that kind of rate??? I was reading the Zynq 7000 SoC Technical Reference Manual (https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual) and in there it has the following block diagrams of the Ethernet Controller it seems I don't have access to the buffers but only to the GMII pins that interface, see diagrams below. What I need to do is grab the packet of data from the ethernet connection and send it to the PL so I can serially send it out. Going the other way, receive the serial data in the PL and send it to the host computer via the ethernet interface. It seems to do that I need to be able to access the AHB port (see diagram 2 below) or at least the buffers if they are big enough to put and grab data from? From what I can see in the second diagram the PL is not able to access that? Any help would be appreciated.
  6. Hi, I have what seems to be a working hardware design with the Zmod 1410 scope module (see below). My thought then was to modify the DDR example code removing all references to "triggering" (I don't care about that at this point) and recycle the multi S2MM_cyclic_transfer_test example. I created a new "helloworld" application in Vitis, copied the main.c from the above application and rebuilt the project. Then added what seemed to be relevant libraries in the main.c file. I did this 2 times and am having the same problem with the UserRegister path, I've built and cleaned the project, the cleaned version looks like it should run but then cannot find a valid platform when I try to launch from the Debug hardware option. Seems to be the same path issue for both versions, I was worried the "datatrans_" directory path was causing some problem so built the new "axidata" version. The scope below shows a 1MHz sine wave with 100MHz ADC sample from the Zmod and the lower sawtooth is a DSP accumulator. These seem ok before the AXI stuff happens is why I claim the hardware design is ok. Any ideas on what could be the problem? Thanks, Error: Error while launching program: The platform 'C:/GitHub/WN_Zmod/Vitis_notrig/design_1_wrapper_1/export/design_1_wrapper_1/design_1_wrapper_1.xpfm' used by the system project 'axidata_system' is not valid. The platform 'C:/GitHub/WN_Zmod/Vitis_notrig/design_1_wrapper_1/export/design_1_wrapper_1/design_1_wrapper_1.xpfm' used by the system project 'axidata_system' is not valid. Description Resource Path Location Type Invalid project path: Include path not found (C:\..\GitHub\WN_Zmod\Vitis_notrig\datatrans_\Debug\_sdk\bsp\ps7_cortexa9_0\include). datatrans_ pathentry Path Entry Problem Description Resource Path Location Type Invalid project path: Include path not found (C:\..\GitHub\WN_Zmod\Vitis_notrig\design_1_wrapper_1\export\design_1_wrapper_1\sw\design_1_wrapper_1\standalone_ps7_cortexa9_0\bspinclude\include). axidata pathentry Path Entry Problem
  7. Hi all, I created a script (below) using the Waveforms SDK to use an Analog Discovery 3 to sweep gate and drain voltages over a mosfet and generate IV curves. The plots look right but they seem to be limited by current and aren't showing the full plot. I was wondering if anyone knows why this is? The plots: This is the script I am runing: from WF_SDK import device, scope, wavegen # import instruments import matplotlib.pyplot as plt # needed for plotting import csv #needed for generating CSV files for graphing later """-----------------------------------------------------------------------""" #resistance = float(input("Enter the resistance in Ohms of the resistor in series with the mosfet: ")) TODO user inputs later resistance = 100 gate_voltages = [0, 1, 2, 3, 4, 5] #gate voltages to sweep across # name of csv files filename_currents = "chip_currents.csv" filename_voltages = "chip_voltages.csv" # connect to the device device_data = device.open() #TODO open again to get second device """-----------------------------------""" # writing to csv file for filename in [filename_currents, filename_voltages]: with open(filename, 'w') as csvfile: # opens csv files csvwriter = csv.writer(csvfile) # creating a csv writer object csvwriter.writerow(gate_voltages) # writes header row (gate voltages) # initialize the scope with default settings scope.open(device_data, sampling_frequency=10e5) # generate a 10KHz sine signal with 2V amplitude on channel 1 current_dict = {} volt_dict = {} for VG in gate_voltages: wavegen.generate(device_data, channel=2, function=wavegen.function.dc, offset=VG, frequency=10e2, amplitude=1) #generate dc signal to gate voltage at voltage i wavegen.generate(device_data, channel=1, function=wavegen.function.sine, offset=2.5, frequency=10e2, amplitude=2.5) #generation sine waveform to drain [mosfet_voltages, resistor_voltages] = scope.record2(device_data) # get data with AD3 oscilloscope mosfet_currents = [] for v in resistor_voltages: mosfet_currents.append(v/resistance) # calculate current with ohms law for filename in [filename_currents, filename_voltages]: #outputs currents and voltages to csv with open(filename,'a') as csvfile: writer = csv.writer(csvfile) if "current" in filename: writer.writerow(mosfet_currents) elif "voltage" in filename: writer.writerow(mosfet_voltages) plt.plot(mosfet_voltages, mosfet_currents) #plot curve of mosfet voltages vs. mosfet currrents #plot labels and show plt.xlabel("Voltage (V_DS) [V]") plt.ylabel("Current (I_D) [A]") plt.show() # reset the scope scope.close(device_data) # reset the wavegen wavegen.close(device_data) # close the connection device.close(device_data) In case anyone asks, record2 which I use to record data from the oscilloscope is just a modified scope.record function in order to get data from both channels at the same time. Even if I use record, I still see current limiting graphs but they are also just wrong because of the time offset so I don't think that is the problem. Regardless, the code for record2 in scope.py looks like this: def record2(device_data): """ record an analog signal parameters: - device data - the selected oscilloscope channel (1-2, or 1-4) returns: - a list with the recorded voltages """ # set up the instrument if dwf.FDwfAnalogInConfigure(device_data.handle, ctypes.c_bool(False), ctypes.c_bool(True)) == 0: check_error() # read data to an internal buffer while True: status = ctypes.c_byte() # variable to store buffer status if dwf.FDwfAnalogInStatus(device_data.handle, ctypes.c_bool(True), ctypes.byref(status)) == 0: check_error() # check internal buffer status if status.value == constants.DwfStateDone.value: # exit loop when ready break # copy buffer buffer = (ctypes.c_double * data.buffer_size)() # create an empty buffer buffer2 = (ctypes.c_double * data.buffer_size)() # create an empty buffer if dwf.FDwfAnalogInStatusData(device_data.handle, ctypes.c_int(0), buffer, ctypes.c_int(data.buffer_size)) == 0: check_error() if dwf.FDwfAnalogInStatusData(device_data.handle, ctypes.c_int(1), buffer2, ctypes.c_int(data.buffer_size)) == 0: check_error() # convert into list buffer = [float(element) for element in buffer] buffer2 = [float(element) for element in buffer2] return [buffer, buffer2] Thank you so much!
  8. Hi, I would have to make small changes and "wire" UART0 resource to the PMOD header ( all within ARM-PS domain) . Then I would have to generate the simple fsbl. Then make the SD card bin file to kick off QNX. At this time only one UART is exposed via USB-UART chip.... Thank you. Any help is appreciated.
  9. Are these addresses constant for the Eclypse Z7 platform or do you need to look at this file each time when wanting to get data? I was wondering how these came about, does building an application in Vitis automatically assign the values or properly route existing hardware values? or other magic? Thanks,
  10. The error indicates that your ODBC database is missing. Get the database from the computer that ran DASYLab 13. Once you have it, use the ODBC Data Sources (32-bit) tool (in the Windows Control Panel Administrative Tools) to make it visible to the DASYLab ODBC module. If it's an Excel worksheet, select Excel Files and press Add.
  11. Please take a look at the attached PDFs. RoHS_Statement_AI-EXP32_20240328.pdf RoHS_Statement_USB-2416-4AO_20240328.pdf
  12. Hi @Takashi "The Yaka mein", I have sent you a PM with some additional information. Thanks, JColvin
  13. (I posted over at the Xilinx fora as well). I'm in need of some design assistance with PCB layout and config of a XC7Z010-1CLG400C (the same Zynq part used on the Zybo Z7-10). We use Altium. I believe I can work out a contracting arrangement as necessary. Anyone here have such experience? (this is for an in-house electronics, a substantial update to one of our systems and is in no way competing with Digilent nor Xilinx)
  14. We currently use an analog data acquisition board that we would like to replace with a Digilent product. The board we are currently using is from National Instruments which is also an Emerson company, so I’m hoping that the following request can be supported by Digilent. My company has internal quality requirements that require that replacements have specifications that at least meet those of what we are replacing. Although I see by comparing the following 2 devices that the specs of the Digilent product are better, I have been asked to get confirmation from the manufacturer that the analog input specs of the MCC USB-1608G at least meet if not exceed those of the National Instruments Pci-6053E. Any help is greatly appreciated. -Mike-
  15. We recommend the DASYLab software for applications that capture over a million scans. An XOR gate module could be used for your application to check the data while it is being saved. You would connect one input to the USB-DIO32HS input and the other to a global variable, which is set to the ideal response. The module will set its output to TRUE if the two are different. For example, if the global variable is set to 255 and the response from the device is 254, the gate's output will be set to TRUE. A Counter module could be used to count the number of times the gate transitions from FALSE to TRUE. DASYLab BASIC is the minimum package for this kind of application.
  16. Hello everyone, I am receiving 56 million bit per minute to my fifo generator and i need to store the data in a big memory which is DDR3, since i am using Arty A7 100T. Could you please let me know how can i do it? from the fifo, data are going to my microblaze processor to be displayed over ethernet. Is there any considerations should be taken? my processor clock is 81.24, and my rtl blocks are 100MHz. Thats why i am using fifo generator for cdc. What i did so far is configure the fifo generator to independent clock block RAM, and vivado always shows this error message: [Synth 8-5833] Design has more instantiated block-RAMs than device capacity. Consider targetting to a different part.
  17. Hello John. Have you had an opportunity to find a solution for the ODBC error message? My trial is for 26 days, and we have yet to perform a successful test on the evaluation copy of DASYLab 2022_1. Please advise. Regards, Matt
  18. I suspect a short (less than 6 feet), straight-through DB37 cable will work. However, MCC did not test such a scenario, so it will be up to you to verify the performance.
  19. Windows 11 requires InstaCal version 6.72 or newer and DASYLab 2022. The current version of InstaCal is 6.74, which can be found here. You can purchase a DASYLab update here.
  20. I forgot about the ACC-202 DIN rail mount. To mount it, line up the holes in the mount with the circular pattern of holes on the bottom of the device. Use the self-tapping screws that come with it. https://digilent.com/shop/mcc-cables-and-accessories/
  21. Hi, We bought this device for a shock and vibe test of an assembly. We need to make sure none of the 24 switches and contacts change state while they wiggle vigorously for 6 hours and the .csv file would be the official proof report if every columns passed the test. If i set the sampling rate to 1000, i can only log 16 minutes? Do you have a software other than DAQami that can do that or log a much longer scenario? Cant i configure something so it never logs unless any of the them inputs change state? Or another software that can do that? Many thanks, Micaël from Fuji Electric
  22. The USB-2416 inputs are multiplexed, switching them one by one to the A/D converter. This style of design requires a low-impedance signal, while open inputs are high-impedance. If you have a channel connected to a voltage source and another channel that is not connected, the second channel can respond to the first. Connect the second channel to the device ground to eliminate any cross-talk.
  23. I have purchased AnalogMAX DAQ3 and have started acquiring data through the demo code provided in Jupyter Notebook. The data which is being acquired is for 500ms. I want to acquire data for at least 1000ms. How do I do that? Is it capable enough to acquire data for such a longer period?
  24. Hi @Rohan16 You can use StaticIO to drive the DIO 0/1. If not Z this has higher priority over the DIO than Patterns and Protocol.
  25. Hello Arthur, After I remove code from the functions in Zmod/baremetal/intc.c,the functionality of initializing ZmodADC has been consistently unusable.I've been trying to solve the issue of initializing the functionality of ZmodADC these past few days.This problem has been bothering me for quite some time.This is quite a strange question, I can't figure it out by myself, I feel like I still need some advice from you.Here's my main.c code. //-------------------------------------------------- // blog.csdn.net/FPGADesigner // copyright by CUIT Qi Liu // Zynq Lwip TCP Communication Test Program //-------------------------------------------------- #include "timer_intr.h" #include "sys_intr.h" #include "user_tcp.h" #include "lwip/netif.h" #include "sleep.h" //#define TRANSFER_LEN 0xB #define TIMER_LOAD_VALUE XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ / 8 //0.25S static XScuGic Intc; //GIC static XScuTimer Timer;//timer //extern volatile unsigned tcp_client_connected; //extern int tcp_trans_cnt; void start_application(void); #include "./Zmod/zmod.h" #include "./ZmodADC1410/zmodadc1410.h" #define SEND_SIZE 1463 //extern struct netif server_netif; static char val_formatted[15]; #define TRANSFER_LEN 0x5B7 // ZMOD ADC parameters #define ZMOD_ADC_BASE_ADDR XPAR_AXI_ZMODADC1410_0_S00_AXI_BASEADDR #define DMA_ADC_BASE_ADDR XPAR_AXI_DMA_ADC_BASEADDR #define IIC_BASE_ADDR XPAR_PS7_I2C_1_BASEADDR #define FLASH_ADDR_ADC 0x30 #define ZMOD_ADC_IRQ XPAR_FABRIC_AXI_ZMODADC1410_0_LIRQOUT_INTR #define DMA_ADC_IRQ XPAR_FABRIC_AXI_DMA_ADC_S2MM_INTROUT_INTR //static char sendBuffer_main[TCP_SEND_BUFSIZE]; //-------------------------------------------------- // 中斷與定時器初始化 //-------------------------------------------------- void System_Init() { Timer_init(&Timer,TIMER_LOAD_VALUE,TIMER_DEVICE_ID); Init_Intr_System(&Intc); // initial DMA interrupt system Setup_Intr_Exception(&Intc); Timer_Setup_Intr_System(&Intc,&Timer,TIMER_IRPT_INTR); Timer_start(&Timer); TcpTmrFlag = 0; } //-------------------------------------------------- // 主程序 //-------------------------------------------------- int main(void) { xil_printf("Im here~~~\n"); uint8_t channel=0; uint8_t gain=0; size_t length=TRANSFER_LEN; ZMODADC1410 adcZmod(ZMOD_ADC_BASE_ADDR, DMA_ADC_BASE_ADDR, IIC_BASE_ADDR, FLASH_ADDR_ADC, ZMOD_ADC_IRQ, DMA_ADC_IRQ); uint32_t *acqBuffer; adcZmod.setGain(channel, gain); acqBuffer = adcZmod.allocChannelsBuffer(length); adcZmod.acquireImmediatePolling(acqBuffer, length); static char time_formatted[15]; uint32_t valBuf; int16_t valCh; float val; int coo; xil_printf("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); struct netif *netif, server_netif; //用於lwIP網絡接口的通用數據結構 struct ip4_addr ipaddr, netmask, gw; //unsigned int //開發板的MAC地址 unsigned char mac_ethernet_address[] = { 0x00, 0x0a, 0x35, 0x00, 0x01, 0x02 }; System_Init(); netif = &server_netif; //0x50C004 xil_printf("netif = %s\tnetif = 0x%p\t&server_netif = 0x%p\n", netif, netif, &server_netif); //將4byte結構的IP地址轉換爲unsigned int IP4_ADDR(&ipaddr, 192, 168, 1, 10); //IP地址(開發板) IP4_ADDR(&netmask, 255, 255, 255, 0); //網絡掩碼 IP4_ADDR(&gw, 192, 168, 1, 1); //網關 lwip_init(); //初始化lwIP //將網絡接口添加到netif_list中 if (!xemac_add(netif, &ipaddr, &netmask, &gw, mac_ethernet_address, XPAR_XEMACPS_0_BASEADDR)) { xil_printf("Error adding N/W interface\r\n"); return -1; } xil_printf("netif_final = %s\n", netif); //NULL netif_set_default(netif); //設置默認網絡接口 netif_set_up(netif); //啓動網絡接口 tcp_send_init(); //初始化TCP PCB xil_printf("New acquisition ------------------------\r\n"); xil_printf("Ch1\tRaw\tTime\t\r\n"); // while(1) { if(TcpTmrFlag) { tcp_tmr(); TcpTmrFlag = 0; } xemacif_input(netif); //將MAC隊列中的packets傳輸到lwIP棧中 if (tcp_client_connected) { //連接成功則發送數據 xil_printf("TCP Connected"); /* for (int i = 0; i < 30; i++)// { valBuf = acqBuffer[i]; valCh = adcZmod.signedChannelData(channel, valBuf); val = adcZmod.getVoltFromSignedRaw(valCh, gain); adcZmod.formatValue(val_formatted, 1000.0*val, "mV\r\n"); //xil_printf("%d\t%s\t\r\n",i,val_formatted); strcat(sendBuffer,val_formatted); } */ //send_data(); //xil_printf("tran_cnt:%d\r\n", tcp_trans_cnt); xil_printf("Ready to send"); //strcpy(sendBuffer,""); //adcZmod.freeChannelsBuffer(acqBuffer, length); } if (tcp_client_connected==-1) { xil_printf("errorrrrr exit\r\n"); return 0; } //sleep(2); } return 0; } And if I removed the initiate part of ZmodADC uint8_t channel=0; uint8_t gain=0; size_t length=TRANSFER_LEN; ZMODADC1410 adcZmod(ZMOD_ADC_BASE_ADDR, DMA_ADC_BASE_ADDR, IIC_BASE_ADDR, FLASH_ADDR_ADC, ZMOD_ADC_IRQ, DMA_ADC_IRQ); uint32_t *acqBuffer; adcZmod.setGain(channel, gain); acqBuffer = adcZmod.allocChannelsBuffer(length); adcZmod.acquireImmediatePolling(acqBuffer, length); static char time_formatted[15]; uint32_t valBuf; int16_t valCh; float val; int coo; the code of can run successfully. In my opinion, the Eclypse Z7 may have a certain procedure to confirm the normal execution of interrupt processes. When there is any abnormality in the interrupt process, other actions will not be executed. Of course, this is my observation based on experiments, which may not be accurate. If you need any other information, please let me know. Thank you very much.
  26. Hi , was wondering if I can use a DB37 male to female extension cable to interface between the 2416 and the AI-EXP32 ? If yes , what is the max length of the cable than can be used considering losses ?
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