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Our Data Acquisition Handbook is a great place to start. https://files.digilent.com/reference/data-acquisition-handbook.pdf

Please review page 18 in the user manual for case dimensions and the attached files for the ACC-205. The ACC-205 kit includes a set of 4-20 x 5/16" screws used to mount the bracket to the existing holes on the bottom of the E-1608 case. ACC_205_DIN_clip_50mm.pdf MCC_ACC-205-assm_50mm-l_din_clip_4-hole_asm.stp

I have been asked to change the 8 slide switches on a Nexys board, and I have around 10 boards to complete. Just removing one switch is challenging......would it be any alternative by using the Pmod header interface ? Having Pmod SWT: 4 User Slide Switches x 2 ? and adding Pmod LED ? or do you have any idea ?

Hello i want to learn the data acquisition on the mcc usb daq 205 and can you share if there is any sort of resources where i can refer to it and know more about DAQ, thanks

@wayyu, You can use the DDR3 Control IP core provided by Xilinx. The Ip is free to use. Using the GUI of the IP you can select AXI as the user_interface for the Ctrl Core. There is also the Ctrl IP core documentation, MUST read it. Also there is an example_design in there which you MUST try out before creating your custom design.

Hello! We need to integrate the MCC E-1608 DAQ into a prototype. For that we would like to use the ACC-205 DIN Rail Kit but we did not find any drawing, CAD or dimensions for this item. Please could anyone help us? The minimum information we need is the size of the included screws and the spacing between the holes of the rails. Thank you. Javier

@Michael Bradley I have not taken a look for a long time into the Zybo Z7 pin mapping file. But I can tell you from memory that the PMOD connections are generally connected to the FPGA GPIO pins, so that you can control them as as you like. So the answer to your question would be a yes!

Board: Zybo Z7-10 Software: Vivado Lab Edition 2020.2 Debugger: Xilinx Platform Cable USB II When my Zybo Z7-10 board is connected to the PC using the USB cable, the Software can detect both the PL and PS. All good here! It is my desire, not to use the USB2JTAG bridge to access the FPGA over JTAG. Instead, I want to use the J13 header (I have soldered the pins in there for connection) for JTAG connection to access the FPGA. The Xilinx Platform Cable USB II has the JTAG cables at one end and I want to plug these into the J13 to have JTAG access. At the end Software needs to identify the FPGA over this direct JTAG connection. Is it possible? How can I do it? Is there some jumper settings I must change to facilitate this? Note that I am still using the USB to power the board, so the USB2JTAG is always remaining activated by default. Should I need to change to a 5V DC adapter to power the board when I want to the JTAG over J13? I have also referred here - https://digilent.com/reference/programmable-logic/zybo-z7/reference-manual but did not find any guidance to activate the JTAG over J13 header. Please advise.

I have a flash ADC built and I am trying to use my FPGA as the priority encoder. I need to connect the 3.3 and 0 V signals coming off of the comparators to my FPGA. I don't see any general purpose IO pins like an Arduino has so I was curious as to how I should connect the wires. Can I just use the PMOD ports for this purpose and alter the constraints/xdc file to map to whatever name I give them in the verilog code?

The output rate is about 1 kHz, and the range is +/-5V typically (though we've also tried +/- 10V). I configured the PCIe-DAS1602 for differential and that didn't seem to help. I am using comedi in Ubuntu to read from the board, and have been working to specify the input range as well.

and I need the complete kit

yes please

After applying that fix, I'm also seeing the last five bytes of the last packet be corrupted and need to look into it some more. At least with RECV_BUFFER_SIZE 200000, words_per_packet, 50000, packets 4. Updated main.c is attached. main.c

Hi @NAOUZ Could you restate your question? Are you looking for a Nexys A7 board that can use a 7-15 V external supply instead of a 5 V supply? Thanks, Arthur

Hi @Alturan Welcome to the forum. Storing data in block RAM (or just LUTs) and counting through addresses is a standard way of doing this kind of thing. Each SPI transfer sent to the DAC would have a new value - like your data_i signal would be a new piece of data read out of a BRAM at the start of every transfer, incrementing the address every transfer. You would use a separate counter to control when each new SPI transaction starts to control the sample rate - assuming a 100 MHz clock, you could get a 1 MS/s DAC update rate if whenever a counter counts to 100, a new transfer is initiated, although it looks like your controller currently takes 120 clocks to send out a transfer. You can even control the frequency of the output signal by changing how much the address counter goes up each transfer - adding 10 to a counter that rolls over when it goes above 255 lets you count through a lookup table 10x faster than adding 1 each time. I'd also recommend simulating your HDL as you go, before testing in hardware - using "if clk_divided = '1' then" instead of "if clk_div_counter = CLOCK_DIVIDER - 1 then" for the shift register enable is concerning - it's probably active for 5 clocks in a row, then idle for the next 5, rather than active for one in every five clocks, like I assume is intended. Check out this guide: https://digilent.com/reference/programmable-logic/guides/simulation. Thanks, Arthur

Hi @ericnstein, I have sent you a PM. Thanks, JColvin

Hi @tato0316 Welcome to the forum. MIO pins are not accessible through PL I/Os and don't get constrained - each MIO maps to a specific physical I/O on the chip. The Zybo's SD interface also doesn't have alternate paths on the PCB to FPGA I/O pins. You would need to access the SD card by using the PS, or maybe by controlling PS peripherals from fabric through the PS's AXI slave ports (assuming they're even addressable from there...). Depending on the end goal, maybe you could load the text file data into a BRAM instead, or even a couple of versions of the data, and bake it into the bitstream? Thanks, Arthur

i want such card with exactly the nexte specifications : ( Carte de développement FPGA technologie Xilinx FPGA part XC7100T-1CSG324C Logic Slices 15,8500 Block RAM (Kbits) 4,860 DDR2 Memory (MiB) 128 ClockTiles (with PLL) 6 DSP Slices 240 Internalclock speeds exceeding 450MHz On-chip analog-to-digital converter (XADC) Programmable over JTAG and Flash System Features USB-JTAG programmingcircuitry Poweredfrom USB or any 7V-15V source microSDcardconnector System Connectivity 10/100 Mbps Ethernet USB-UART Bridge Interaction and SensoryDevices 3-axis accelerometer PDM microphone PWM audio output TemperatureSensor 2 four-digit sevensegment displays USB HID for mice , keyboards, and memory sticks 16 Switches 16 LEDs 2 tri-colorLEDs 12-bit VGA output Expansion Connectors 4 PmodconnectorsPmod for XADC signals Réf : Nexys A7-100T )

Hi @Viktor Nikolov 500000 should be fine for a packet length - it fits within the 26-bit max of the DMA. I imagine you're also increasing the RECV_BUFFER_SIZE, since it doesn't sound like it's reporting errors - adding a return to the check in main would help debug: With fresh eyes, there's a bug in the code where the cache is handled - the ranges should be RECV_BUFFER_SIZE * sizeof(u32) bytes, rather than RECV_BUFFER_SIZE words. This would be obscured unless large enough values for the packet length and count are tried... Thanks, Arthur

Hi @ankit24, My name is Britt, I am on the team that manages Multisim Live. I've reached out to you via email to help solve the issue. Please continue this conversation there. -Britt

On our older machine we have 2 DT9812. Each card has 1 AI, AO, and counter. The counter uses the CounterTimerSubsystem with the following configuration. ctSS = device.CounterTimerSubsystem(0); ctSS.CounterMode = CounterMode.Measure; ctSS.StopEdge = EdgeSelect.GateFalling; ctSS.StartEdge = EdgeSelect.GateRising; ctSS.DataFlow = DataFlow.Continuous; ctSS.Clock.Source = ClockSource.Internal; ctSS.Clock.Frequency = 5000; ctSS.MeasureDoneEvent += CtSS_MeasureDoneEvent; Our new machine will need 3 counters, and up to 5 AI. However, the analog input isn't a solid requirement. We can read those elsewhere if necessary. I am aware I'll need to rewrite my code to use the universal library. That won't be an issue, as long as the driver can raise an event when the counter increments. Is there a reason so many DT models say "Not recommended for new applications."? If we knew why, we might be more inclined to use them.

Thank you, JRys.

Hi @rpatel, For the SMT4, I have been informed that the worst case for Vdd is 115 mA and the typical usage is 90 mA with JTAG running at max speed and UART running at 1 MBaud. The Vref current at 30 MHz is 12.5 mA typical and 35 mA max (unless you short the outputs, then Vref would probably peak out around 170 mA). You didn't ask about minimums, but when the USB controller is held in reset, the current consumption is ~20 mA. When it comes out of reset and enumerates on the bus it's ~87.5 mA. Let me know if you have any questions. Thanks, JColvin

@bsee, You have an existing application with the DT9812-10V, which is still available. How is the DT9812 used in the existing application, i.e. number of channels, sampling rate, subsystems? This information is necessary to match to an equivalent MCC device. Note that moving over to a MCC device will require rewriting your application with the MCC Universal Library.

Hi @Kevin.C, 3.22.19 is an "official" beta build (https://forum.digilent.com/topic/8908-waveforms-beta-download/) as opposed to a formal release (though the difference between a beta build and a formal release mostly boils down to the amount of documentation involved along extra hunting for bugs). I do not anticipate a formal release version to be made for at least a couple of months; it depends when a new Digilent Test and Measurement device comes out, but I have not seen any announcements as of yet. I will make a note to ping you once a release version has been made. Let me know if you have any questions. Thanks, JColvin