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  2. Let me offer a suggestion to all newbies, regardless of how smart you are, before trying to do FPGA development. Read all of the user guides for the FPGA device resources that you are likely to be using. These will include the SelectIO, Clocking, CLB , and memory guides at a minimum. [edit] also read the AC switching part of the device data sheet. Like it or not what you are doing in FPGA development is digital design and you need to have a sense of how design decisions affect timing. Read the Vivado user guides for design entry, constraints, simulation, timing closure, and debugging. Understand that even though various Zynq devices are based on certain FPGA families the documentation tends to be unique for these devices. You will be overwhelmed with all of the 'basic' information. Spend a week or so running though all of the basic documentation, spending more time on specific topics each read-through. The object isn't to memorize or understand everything but to get a general feel for how Xilinx presents its information. You can also learn stuff that you will miss in specific IP documentation by using the simulation, but only if you are careful to read all of the simulator messages. This is complicated stuff and the tools, even when they behave as described in the reference material is even more complicated. The purpose of doing this is to get a general feel for how the devices work and specific use limitations and how the tools work. It will take a year or so before you start becoming competent at it if you are a normal human.
  3. @askhunter Tip if you want to notify someone that you are responding to a post type @and the first few letters of their username. A selection of usernames will appear in a popup window to choose from. If you just type @ and the whole name you won't get the desired result. I confess that I'm not an expert on using the features of this site but I did figure out this one. As to understanding all of the Xilinx documentation what yo are doing is correct. Speed-read though a document to get a general sense of what's being presented and don't worry about the things that you don't grasp. Just being familiar with what information is where will help with a specific question later. The DSP48E is a very complicated piece of hardware. You only understand how complicated by trying to instantiate it as a UNISIM component to implement a particular algorithm. I've done this and it take time. You understand by doing; one step at a time. In your case I'm assuming that you are starting with someone else's code and trying to modify it. This approach takes a difficult task and turns it into an extremely difficult task. [edit] Vivado uses the multipliers in a seamless way when you specify a multiply in your HDL code. It takes care of a lot of little details, such as that the multipliers are signed 18-bit. There are a LOT of options with the DSP48E blocks. Once you start making decisions for Vivado, by say, using the use_dsp attribute in your code you are taking on responsibility for more of those details... so you had better understand how the DSP48E blocks work. Trust me, even after you have figured out all of the necessary behaviors of the DSP48E blocks it doesn't get easier as you will have to contend with routing issues that might dramatically reduce your data rates. This is a general rule for using FPGA device resources. You can use the IP wizards to help construct a component that's useful for your needs or do it yourself in HDL code and assume the responsibility for getting all of the details and constraints right.
  4. thank you for interesting. Actually, I read this documentation but this has so many detail and i'am very newbie in fpga. so i didn't understand mostly. even so I'll read it again.
  5. Today
  6. @askhunter I suggest that you read UG479 to see what the DSP48E blocks do. Then read UG901 to see what the use_dsp attributes do. Reading the recipe doesn't always help improve the cooking but it never hurts. A long time ago having signed multipliers in hardware was a big deal for FPGA developers. For the past decade or so these have become integrated into more complicated and useful 'DSP' blocks. The DSP nomenclature is a holdover from the days, long before IEEE floating point hardware was available, when having a fast multiplier in hardware meant that you could do some fun stuff in a micro-controller that you couldn't do with software routines. These days the lines are blurry. Most FPGA devices have some really fast hardware features, block ram and DSP blocks ( depending on how they are used ) being the most useful for grinding out mathematical algorithms. By the way, the DSP blocks can be useful for more than multiply-add operations.
  7. Hello friends, i have been build HelloWorld Linux application using Xilinx SDK cross compliler=C:\Xilinx\SDK\2017.4\gnu\aarch32\nt\gcc-arm-linux-gnueabi\bin\arm-linux-gnueabihf- after creating hello.elf .. I copy this file into sd card and then switch on my zybo board containing sd card (hello.elf) then after running Linux over zybo zynq soc, I tried to run hello.elf, but I am getting following error... zynq> hello.elf - /bin/ash: hello.elf: not found why it is saying not found ...what is meant by that... please reply if you have any solution regarding this issue. thanks regards Arjun
  8. first : without dsp attribute - attribute use_dsp of sum : signal is "no"; second image : with dsp attribute - attribute use_dsp of sum : signal is "yes";
  9. Hi, I try to simple multiplication, but when i use dsp attribute then i got different result in simulation .what is the reason of this? without dsp attribute - attribute use_dsp of sum : signal is "no"; with dsp attribute - attribute use_dsp of sum : signal is "yes"; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.types.all; entity convolution2d is port ( clk, rst : in std_logic; start : in std_logic; window : in frame9; done : out std_logic; pixel : out pixel8 ); end convolution2d; architecture rtl of convolution2d is constant mask : mask_9 := (-1, -1, -1, -1, 8, -1, -1, -1, -1); signal sum : integer:=0; attribute use_dsp : string; attribute use_dsp of sum : signal is "yes"; begin -- iterative way process(clk) is --variable tick : std_logic:='0'; begin done<='0'; if rising_edge(clk) then if start = '1' then sum <= 0; for n in 0 to 2 loop for k in 0 to 2 loop sum <= sum + (to_integer(unsigned(window(n*3 + k))) * mask(n*3 + k)); end loop; end loop; done<='1'; pixel <= std_logic_vector(to_unsigned(sum, 8)); end if; end if; end process; end rtl; "
  10. I am using Xlinux ZYBO-7000 board with Debian Jessie Linux, the FPGA programming is done by my professor. as part of my project I have to display my PyQt5 application via HDMI, in order to display pyqt45 application via HDMI, I have to point PyQt5 application to framebuffer /dev/fb0. but it gives me "cannot connect to X server" error. I had used qt designer to create my GUI application in ubuntu16.4 and then I copy my project into ZYBO (Debian-Jessie). but then I find out that I have to compile pyqt5 with linuxfb then it will display GUI into framebuffer. but I do not know how to do it? I search on the internet but I could not found a solution. can anyone please suggest me so tutorial or something regarding how to run the pyqt5 application in zybo 7000?
  11. is it possible to run Application by writing it in SDK on video passthorugh/HDMI demo given
  12. This was solved by switching to Vivado 2017.4
  13. Mukul

    Data compression

    I'm working on Data compression so studying different code techniques such as follows to implement on zybo board Golomb coding special case Rice code compression Huffman code Arithmetic code And finally Dynamic Markov compression I selected DMC because it is dynamic in nature and work well with sensor (as input).Here is the problem that i don't know exactly markov compression is good for this or not. Also when i study the DMC it's algorithm is similar to sequence detector (so are they same?). Secondly in video processing/image processing or in general which tech. Is used in Data compression.
  14. @SGY What you will get is a pretty nice, somewhat elderly but very useful FPGA development hardware. You also get the Zedboard community and all of its postings. There are numerous tutorials written expressly for a version of this board. I highlighted 'a version' because you need to know that there were a few important hardware changes in the life of the board. Because it's older most of the tutorials were written for long gone versions of ISE or Vivado and might be difficult to follow as the Vivado user experience changes with every new version. As to RTL code you can find some but since this is a ZYNQ product the emphasis is on the ARM development. I've had the C version of the board for quite a while and still make use of it when I need a Zynq solution. The Zedboard contributions are at this time mostly old at this time so you will have to learn the whole Zynq development ecosystem. Once you've done a few PL designs it will get easier. Zygot's hint for the day is to let Vivado create a Zynq HDL toplevel source file in a project that you, not Vivado, manage. You can instantiate that into your own toplevel design with all of the PL magic that you can conjure up. You'll have to trust me that this is the far easier way to go if you want to do FPGA development with ARM support. Your opinion is more important (to you) than mine however...
  15. @Reggs Thanks for posting your question. My first suggestion is that you figure out how to use the testbench in Vivado. You can create a special Vivado project using just the UART_DEBUGGER,vhd and YASUTX.vhd source files. It doesn't matter what device you use. Just make sure to add the T_* testbench files as simulation sources after the project has been created. Both Vivado and ISE mark source files as implementation or simulation or both and it's important that VIvado knows which are which. All of this was easier in ISE. ( in a lot of ways Vivado is a really badly conceived software application ) In Vivado Simulation Settings you can select which of the testbenches you want to simulate. I strongly suggest that you get to know how to do simulation in Vivado or ISE ( simulation is actually easier in ISE ). None of the code uses a particular feature of any particular FPGA device so you could use the free version of ModelSim that comes with Quartus to run the simulations as well. If you really can't get the simulation running let's work on that first. Once you have the simulator working it will, by default, show you the toplevel (in this case the testbench) signals. You can then add any or all of the lower level code in the hierarchy to the simulation waveform viewer. Just understand that the more signal you show and the finer the time resolution the longer the simulation takes. For this code what takes time is the slow uart output. You did read the commentary at the top of the source files, right? You should be able to use a 50 MHz clk and get out a message at a 115200 baud rate. I've used this component often and with a few baud rates ( I haven't tested it exhaustively at lots of different baud rates ). The idea is to send a string of hex numbers in ascii form so that you can read the value of a register in your code at a particular event or time. This particular tool isn't meant to send text, only hex numbers in ascii format. The number of hex digits displayed in the terminal should match your DATA_CHARS assignment. Are you sure that the clock that drives the UART_DEBUGGER matches the generic CLK_RATE? From what you depict as your output it looks as though your problem is not with baud rates ( clearly there are recognizable characters being printed ) but in using the data_write_stb and busy signals. data_write_stb should not be asserted until after busy is de-asserted (low). The busy signal indicates that the YASUTX transmitter is in the process of sending a set of characters and not ready for another set. Make sure to strobe data_write_stb for only 1 'clk' clock period. In your code you will decide what conditions or event starts a message. It should be obvious that any baud rate is going to be pretty slow relative to whatever is going on in your design at 50 MHz so you need to make logic to select the instant where your data is captured and sent. By the way you can capture multiple data states in successive clocks by putting a fifo between your data and the UART_DEBUGGER; that way you can feed say, 1000, snapshots of your data to the fifo and let the UART_DEBUGGER read them at its own slow uart time frame. I have an example of this lying around somewhere around here... Oh, if you look at S3_PGMR_D.vhd in the source in the S3 Starter Board Programmer project that I've posted here in the Project Vault you can see an example of using a FIFO with UART_DEBUGGER. You may wonder why you'd want to print out data faster than you can read it but if your use Putty as your terminal it can be set up to fork all incoming and outgoing text to a file so that you can read it later... how cool is that? Once you get the code simulated you will quickly figure out what's going on. Hopefully, you will be encouraged to start on creating your own debugging IP. You can, with a bit of skill and practice make better and more useful debugging tools than Vivado provides. [edit] Xilinx has a number of helpful guides to using the Vivado simulator in tutorial, reference manual or user guide formats. There's a lot of information about the devices and tools to digest but you don't have to understand everything in order to learn enough to do a specific thing. Being able to use the Documentation Navigator and material is key to success with FPGA development.
  16. Yesterday
  17. want to buy ZEDBOARD ZYNQ-7000 ARM/FPGA SOC. Will RTL code provided with the board? what do i expect to get? Thanks,
  18. Dear Sir/Madam, I am trying to create a single pulse using the wavegen in labview but couldn't find the subVIs in the DigilentWF library. I was able to use the Waveform software to create a single pulse. Attached are the pictures. Is there anyone that can help to shed some lights on how to achieve that? Much appreciated.
  19. I was working on my project the other day and in between launches, the Vivado SDK stopped generating the drivers folder. I didn't change anything in my block diagram and only changed a little bit of VHDL in the top file (creating 2 wires unrealated to the IP cores). My block diagram has a Microblaze connected to 3 PMOD SD blocks and a BRAM controller. I've grabbed the most recent version of the vivado-master library from Digilent's Git. I'll attach the SDK output log. Let me know what else you need from me, and thanks a million in advance everyone! SDK.log
  20. I'm trying to boot petalinux on the Z7-20 board and after following the instructions in the github page, I am running into an error. After putting the SD card into the board and starting the boot process, it says there is a command not found. Do I need to try redownloading the packages in case an error occurred doing this? I'm running this off of Ubuntu 2017.4 and I know there were issues with the locale checks where I had to edit those files in order to bypass. Thank you for the help
  21. kwilber Thanks! That's what I need to know for now. I'm solidifying my choice of board and trying to locate anything which can't work with the board that I choose. I've been leaning towards Arty A7, and this was the last potential gotcha I have to check. I'll move forward now and assume Arty A7 is it. I'm still trying to get my company to install Vivado on my PC, or I would have been able to look myself directly. Allan
  22. The Digilent proprietary USB UART/JTAG circuity allows for simultaneous jtag and uart use.The board appears as two serial ports. Vivado and the SDK automatically find the jtag port and you can use a communication app like TeraTerm using the other port. The "hello world" example you can create in the SDK demonstrate that. Serial communication with the pc is fairly common.
  23. Hi @jamesW, I think that the bit depth of both images would need to be the same in order for it to work correctly (which I believe you said did work correctly at the end of your original post), though I am not certain of this. From what I can tell in the MTDS Library Programmer's Reference Manual (available as part of the documentation included in library download), it says in the BitMap Objects section that "Depending on the coordinates specified and the graphical element being drawn, the clipping can result in all, some, or none of the pixels making up the graphical element to be rendered actually being drawn on the bitmap itself. This is not an error, it is simply a natural consequence of the view that a bitmap is a viewport onto a larger virtual coordinate space." Truthfully, though I'm not certain when these circumstances would occur, though it seems to support the idea that both images would need to be the same bit depth. I also know there are a number of raster operations you can apply in the BitBlt() function as it's own parameter which specifices how the source and destination pixels are combined, but I'm not very familiar with how those all work visually, but the operations are defined on page 12. Thanks, JColvin
  24. Hi All, The first thing that I suspected is a bad cable, so I did try it with several different brand micro USB cables. I tested it with different USB ports, a powered USB hub, then I tested it with another PC. Same behavior in all cases. Second I suspected that maybe since the board was more recent than the other boards I had been using, I updated the Digilent drivers from the Digilent web site. I even installed the Digilent Adapt 2 app which permits you to program the part without Vivado. But the same flaky behavior was observed. I took a look at the board under a magnifying glass to see if anything is amiss -- it is tiny with 0201 parts, but it looks fine. I rebuilt the design (with different pinouts) for the Arty board, following the same programming sequence, and that worked fine on the first try. I regularly work with different FPGA boards, including the Zedboard, the original Zybo, the Zybo Z7-20 and the Arty with no such issues on the same setup so I think the likelihood that something with my installation of Vivado, drivers, or knowledge of FPGAs being the issue is low. I will test the current draw, but I cannot imagine that exceeding 500 mA would be considered normal for an idle board, especially if it is not driving anything external. The Arty works fine just powered off the USB bus (it has the same Xilinx XC7A35T-1C part). I'll look into how others resolved this problem, but it seems to look like an issue with the FTDI chip. Unfortunately the Cmod does not have an alternate JTAG pins to bypass the FTDI. Thanks!
  25. Hi @D@n Thank you for your perfect analyzing and solution to my issue . I just toggled the MSB in each written Byte and I got the sinewave finally. However, I wondered , since in the data sheets (AD5541A , AD7303) is mentioned I have to use operation amplifier in order to get a bipolar signal ! Thanks again.
  26. Thanks for your replies. Sure, if I can use the single USB cable for debug plus device configuration, I'll be glad to do it! I just didn't understand how Vivado would know about the USB-to-FTDI chip link for the Arty A7. Isn't this why we require Adept for configuration instead of doing it directly by Vivado? Also, I'm I'm using a UART bridge for communicating with the Arty A7, wouldn't debug wreck that connection? I'll look at the videos, but I doubt this sort of thing is covered, PC communication with the Arty boards is not something that most people do. Allan
  27. its not detected by waveforms or windows device manager.
  28. I am trying to figure out the pin functions on both the Zedboard and KC705 boards, and was wondering if there was a document that explains the functions of the pins based on their names.
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