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  1. Today
  2. Hello all I tried to implement zybo-z7-hdmi-demo using instructions in the: and I got 5 critical warnings after Implementation of the this project for Zibo Z7-10 within Vivado 2016.4: ImplementationDesign Initialization[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-HDMI/src/bd/system/ip/system_v_vid_in_axi4s_0_0/system_v_vid_in_axi4s_0_0_clocks.xdc":11] [Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-HDMI/src/bd/system/ip/system_v_tc_0_0/system_v_tc_0_0_clocks.xdc":5] [Vivado 12-259] No clocks specified, please specify clocks using -clock, -fall_clock, -rise_clock options ["e:/VICT/Vivado2016_4/Zybo-Z7-10-HDMI/src/bd/system/ip/system_v_tc_0_0/system_v_tc_0_0_clocks.xdc":6] [Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [all_registers -clock [get_clocks -of [get_ports -scoped_to_current_instance clk]]]'. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-HDMI/src/bd/system/ip/system_v_tc_0_0/system_v_tc_0_0_clocks.xdc":6] Route Design[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. impl_1launch_sdk -workspace E:/VICT/Vivado2016_4/Zybo-Z7-10-HDMI/proj/HDMI.sdk -hwspec E:/VICT/Vivado2016_4/Zybo-Z7-10-HDMI/proj/HDMI.sdk/system_wrapper.hdf [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. As I think the reference design must have all necessary parts to do implementation without the critical warnings. Please help me to resolve this problem. Thank you, Best regards, Viktor.
  3. jasonkh12

    Clocking Wizard

    Thank you @zygot, Yes, I am using ISE. The Clocking Wizard is greyed out in IP Core and cannot be selected. I will try to instantiate it as macros. Thank you.
  4. HI, Zygot, OK. I got you. Good advice. I will do that. Thank you !!! Antonio
  5. solved: the problem was made when syncing with a clock and nSamples bigger than clock cycles. solution: adding exit condition in acquire loop, using FDwfDigitalOutStatus to check if output is done
  6. Hi JC, et al. Any progress on a USB HID PMOD board? Surely I'm not the only one who would like to use a USB keyboard, but talk to it in PS/2 protocol on boards that don't have the PIC fitted. You've already developed the firmware and circuitry using the PIC chip, so it shouldn't be too difficult? Cheers, Leslie
  7. Hi Andrew Many thanks for this, I've been looking forward to this for a long time! However I'm still not smart enough to get it to work I've downloaded the executable and tried to run it by first opening a windows7 command window by typing "cmd". When that brings up a command window, I change directory to where the executable and my OpenLogger .log files are stored and type: dlog-utils-v2.2.0.exe inputfile.log outputfile.csv and the response I get is "dlog-utils-v2.2.0.exe is not recognized as an internal or external command, operable program or batch file" The readme on the repository says: Run an example (Windows): ./examples/build/main.exe log.dlog log
  8. RajD


  9. Glenn

    USB Power

    Upon further reflection, I bet my switched cables do not have all the USB lines coming through. RPi only needs power via it's microUSB input.
  10. Yesterday
  11. Hi! Here is a small anouncement New version of LINX will be released in May 2020 and beta is available now through Software Technology Preview website.
  12. Do a little hunting around the Digilent forums...
  13. Glenn

    USB Power

    Hello. Is there anything special about the USB power cable that comes with the AD2? I've tried to use a couple cables with inline switches to allow easier on/off, but neither seem to work. Both work with my RPi. Glenn
  14. When adding HDL sources to a project you can add files from a particular directory or add copies into a new project. For IP generated by Vivado or ISE things get messy because the tools don't always specify source files relative to the current project. This can be irksome when you change the IP in a source project to fit the needs of a current project. Sometimes short-cuts have negative consequences. My advise is to re-create IP for new projects. It takes a little longer but you don't have to contend with surprises.
  15. zygot

    Clocking Wizard

    Where'd you get that idea? Spartan 3 devices have DCM blocks so it is certainly possible to create a 100 MHz clock from a 50 MHz input. You are of course using ISE since Vivado doesn't support older devices. If you don't find what you are looking for in the IP you can always instantiate a DCM as a macro in Verilog ro VHDL. Sometimes, like the Genesys Vritex5 it's not obvious from the selection of clocking IP how to get what you want. The solution is to learn about the device and instantiating resources as macros from the literature.
  16. Hi, Guys, Suppose I am using a certain IP that is located at directory named AA c:\VivadoProjects\AA\ I have exported the project to another directory (BB) and I have given the project another name c:\VivadoProjects\BB But the fact is that the new project is still grabbing files from the first directory AA (Specifically one of the IIPs) and If I delete the first directory, the IP gets unresolved. How can I make sure that all the necessary files and IPs are exported to the new directory and no longer need the original directory files ? Thanks Antonio
  17. First of all the Project Vault is a place to post working projects, not ask questions; so this post belongs somewhere else. Doing things and knowing how they work are often two different challenges. Understanding how to create a tone and how to implement LTE are worlds apart. Wanting to understand the concepts for both are worthwhile goals. I'd advise starting with a good textbook. Janak Sodha's book Fundamentals of Communications Systems is a good introductory text with lots of accessible examples. Analog Devices has a number of good application notes texts available as well. Beware that there is a lot of math involved. Fortunately, one doesn't have to do brute force math to implement basic signal creation. To start, consider a vector. It has length and an angular orientation relative to some X-Y coordinate system. If you pin the tail to a fixed point and spin the head of the vector around at a constant rate you've created the basis for a tone. The basic building block of a tone generator is the phase accumulator. The phase accumulator is nothing more than an adder where you don't care about overflow. The time it takes between overflows represents the tonal frequency. Of course tones are sinusoidal so the actual tone requires using the accumulated phase as a pointer into a sine or cosine lookup table. And that's the 10 second introductory lecture on communications. Now if you suppose that creating a tone and creating the exact tone with the qualities that you want might be a bit more complicated then you assume correctly; but dealing with the details isn't a 10 second presentation. Now, you can do all sorts of interesting things with your rotating vector like modulate ( vary ) its magnitude for AM. Or, instead of changing the phase input to your phase accumulator at a constant rate you can modulate the input to do FM or PM. If you create a number of different tones and add them you can encode information that can be extracted by finding which tones make up the signal. There's quite a leap from there to modern communications in terms of what you need to understand but that's the fun. All of these can be implemented in FPGA logic with a lot of knowledge and a bit of insight. Communications is little more than creating and manipulating tones with some sophisticated conditioning involved. Conditioning is important because poorly designed or constrained communications interfere with other even well designed communication systems. That's why the experimenter needs to be careful building hardware that transmits signals. Drowning out an FM station that you are listening to while playing around with your hardware might be fun for you but will not be so much fun for your neighbours; particularly if they are dependent on a communications system like police and firemem or pilots. The pioneers of modern communications were mathematicians like Fourier, Laplace and Euler who understood the basic concepts long before other very smart people got around to playing with tonal generation for transmitting and receiving information. And all of it is possible because someone had some insight that made the very difficult practical to implement.
  18. jasonkh12

    Clocking Wizard

    I am new to FPGA. I know that nexys2 board (Spartan3E) has 50MHz oscillator. Is there a way to generate 100MHz clock, since Clocking Wizard in IP Core does not support this board? Thanks
  19. Dear All I want to generate an arbitrary waveform or tone having bandwith as large as 20 MHz . I am using ADRV9361-z7035 hardware from analog devices . I gone through online material , but I found material related to LTE waveform , DSSS etc .So I dont want to generate a tone or spectrum of particular standard . I am very curios that how this be done ? as the SDR I am using has 56 MHz (real time instantaneous BW ). Best Regards
  20. Are there any recommended hard/soft UART IPs for the CMOD S7 (VHDL)? Is there any standard one with a data bus, ready trigger, software interrupt?
  21. Last week
  22. @attila Hey Thank you helping with my project a month ago.. Below is the code that you helped me with. Basically when the scope is triggered I average the number of readings that are given. It seems that when the data is averaged from the scope I am getting weird data within the array. for example I may get a quanity of 9 numbers and most of them are around 44.3, 44.9 or 45.23... Those numbers would be ok. But within the same averaged array I am getting numbers that are 80 and 60 and I am not sure how. Thank you for the help. var rgusw = [] var cw = 0 var sumusw = 0 var SensorA_CC_Tested = 0 //Sets Sensor Test Value to zero before test var SensorStep = 1 //Sets the clockwise test into action -- Sets to zero before test // This keeps the script running all the time. (while Statement) while(SensorStep <= 3 && Scope1.State.running() && Logic1.State.running()){ for(var i = 0; i < 8 && Scope.wait(); i++){ var usw = Scope.Channel1.measure("NegWidth")*1e6 // us rgusw.push(usw) // array sumusw += usw cw++ } //print(rgusw) //Uncomment to print all averaged data var uswavg = sumusw/cw if(SensorStep ==1){ SensorA_CC_Tested = "1"; print("Counter Clockwise Average:",+uswavg+" uS")
  23. just an observation: Most people would probably implement this around a shift register, instead of muxing a single bit. Functionally it would be the same (of course, assuming timing is met).
  24. Hi @sgrobler, I've build a 64-bit executable for Windows, which you can download from here. Save that into a location you're likely to remember. Refer to the repository README for instructions on how to use the executable. Regards, AndrewHolzer
  25. Hi @Asha Devi, Thank you for sharing the source and the screenshot. The errors you are seeing say that there are multiple definitions of the ComposeHTMLGetALS function. That is happening because you are including HTMLGetals.cpp in deWebIOServerSrc.cpp. You can fix this by removing #include "./HTMLGetals.cpp" and writing a ComposeHTMLGetALS function declaration in deWebIOServerSrc.cpp or (better yet) a HTMLGetals.h header file that gets included into deWebIOServerSrc.cpp. AndrewHolzer
  26. Welcome to the forums! Some comments: You really should simulate this. Even a simple testbench could help you to start identifying potential issues. How are you driving the chip select and serial clock? If the chip select is held low, it may cause the DAC to misinterpret data as 32-bit words, which could cause the DAC to discard the command bits, at least. Because of the counter=0 check, index=0 only lasts for a single clock cycle. Why hardcode the command bits? You have plenty of space left in your slave register. Thanks, Arthur
  27. JColvin

    JTAG-HS2 program issue

    Hi @Chase, Have you tried closing out ISE iMPACT and then re-opening it and/or restarting the computer? Occasionally drivers can get confused about what is connected; I've run into this same issue before and successfully resolved it in that way. As an additional question, have you successfully gotten the downstream Spartan-6 device to be detected before? Do you have Digilent's Adept software open at the same time as iMPACT? If that doesn't work, we can troubleshoot further. Thanks, JColvin
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