All Activity

This stream auto-updates     

  1. Past hour
  2. Hi @KevL Reading of --3.212V indicates that you have only the 1- (scope channel 1 negative input) connected to the +3.2V The 1+ is floating or it is connected to ground.
  3. Hi @Jope See the following example: The captured data looks good from first to the last byte. >python DWF Version: b'3.11.4' Opening first device Generating gray counter Configuring DigitalIn DigitanIn base freq: 800000000.0 Sample rate: 100000000.0 Buffer size: 268435456 Waiting for acquisition... done Writing to file... done
  4. Today
  5. Hi, thanks for a reply. Let share the project and problem. We can learn from them.
  6. I am also interested in this kind of task. But I will be using AXI Stream and MIPI interfaces with a lot errors that I need to solve..
  7. Sduru

    AXI4 and Vivado ILA

    Thanks for your reply @zygot . As you said about the problem, I've checked the constraints names. I am using Zybo Z7 board and its constraints file in the link . I realised that some of the port names of MIPI D-PHY IP are different from those in the constraints file. I've corrected all of them and toggled non-used pins like in the following: However, I am still getting the same errors. I will be very appreciated if we solve this problem... Many thanks...
  8. Hi Mr. @zygot, I added enable signal (i_en) , which is controlled by a counter. As shown in my code below: -- Library's library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity LFSR3 is Port ( i_clk : in std_logic; o_lsfr : out std_logic_vector (2 downto 0) -- i_en : in std_logic ); end LFSR3; architecture Behavioral of LFSR3 is signal i_en : std_logic := '1'; signal r_lfsr : std_logic_vector(2 downto 0) := "100"; constant maxcount : integer := 625; signal counter : integer := 0 ; begin o_lsfr <= r_lfsr; LFSR_proc: process(i_clk) begin counter <= 0; i_en <= not i_en; if (i_en = '1') then if(rising_edge(i_clk)) then r_lfsr(2) <= r_lfsr(0) xor r_lfsr(1); r_lfsr(1) <= r_lfsr(2); r_lfsr(0) <= r_lfsr(1); end if; else -- line 75 (the error) freq_8kHz: while (counter <= maxcount) loop counter <= counter + 1; end loop freq_8kHz; end if; end process LFSR_proc; end Behavioral; And , when I run synthesized an error appeared : "[Synth 8-3380] loop condition does not converge after 2000 iterations ["d:/Users/dell/Vivado_projects/LFSR2/LFSR2.srcs/sources_1/bd/LFSR/ipshared/4f95/src/LFSR3.vhd:75]" I have pointed to the error location in my code (line 75) . So plz , could you tell me why my loop seems to be infinite (does not converge) !? Thanks.
  9. @AndrewHolzer 1. Tried to change the localhost to with the On Line version of WaveForm Live. No luck. 2. Could not carry out the check with the WIN8.1 machine on network as that engineer is on leave. 3. Installed a new copy of the Digilent Agent ( 1.2.4) and checked. The screen shot is attached. 4. Antivirus .... I run the native Windows Defender and have enabled pass through Firewall. See attachment. But I see two copies of Digilent Agent ? I am sure I uninstalled the old version before installing the latest. If you see the Chrome screen shot , you will see it is saying " Insecure" in the address bar. Is this the reason it cannot connect with Agent ?
  10. It appears to me that it is normal behavior with implementation design. In RTL simulation, there is no gate delay. All logic gate operate without any delay from its input to output ports. However, the delay is attached on simulation with delay on inplemetation design. That is why you can see that each bit of a bus signal will have different propagating time. It called "skew" sometimes in layout design. If there is no timing volation on your design, then there would be no problem with this.
  11. Hi all, I am new to FPGA and it is my hobbies. Most of my job is to design RTL IP and ASIC related work. Currently, I am investigating bus interface in general from UART, I2C, PS-2 to AXI, SPI and so on. My target is to build an IP set to adapt the peripheral using those Interface. Hope to see someone in the same interest.
  12. fpga_babe

    HID protocol on Basys3

    Hi, I am using Basys3 board and I want to write a RTL module in FPGA to get the character from USB Keyboard. From the Digilent reference of basys3, if the FPGA side only receive the data from Keyboard, then the PS_CLK and PS_DAT ports can be as input direction. My question is that, to receive the keycode from a keyboard, do we need to send configuration to Keyboard before hand ?
  13. Have you set up the Arty and Olimex ARM-USB-TINY-H as detailed in chapter 2 of this document? It looks like the TINY-H connects to the Arty via pmod JD.
  14. I'm a new user about arty a7 borad ,referring to the demo_gpio program(,am trying to run this on Artix-7 35T Arty board but getting errors in uploading program. Licensed under GNU GPL v2 For bug reports, read adapter speed: 1000 kHz Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'. Info : clock speed 1000 kHz Error: JTAG scan chain interrogation failed: all ones Error: Check JTAG interface, timings, target power, etc. Error: Trying to use configured scan chain anyway... Error: riscv.cpu: IR capture error; saw 0x1f not 0x01 Warn : Bypassing JTAG setup events due to errors Error: Unsupported DTM version: 15 Info : Listening on port 3333 for gdb connections Error: Target not examined yet
  15. G'Day Andrew, Uh, so there's no way to view the recorded data? Oops. (<flashback to the Seinfeld "most important part" scene> :-) Obviously it'd be great to load / replay the recorded data back into WFL, the interface is pretty neat and I'm a fan of the browser-as-an-app-platform. In the meantime, yes, can you please provide the header? (btw, when's all this going up on github?) Ta, Ben
  16. Yesterday
  17. Are you doing this on Linux or bare metal?
  18. Hi @benl, At the moment you can't use WFL to view the logged data. There are some challenges that surround this and we are working on finding a solution that best solves these problems. The dlog utility has yet to be updated to parse the OpenLogger .log files, as they have a different binary format from the OpenScope. If you are eager and have the capabilities to do so, we can provide you the .log header struct so that you can make your own parser. Otherwise, we'll be working on updating the dlog utility, and will let you know as soon as that has been done. Regards, AndrewHolzer
  19. Might be a little late, but did you manage to get this passthrough working and if so, how?
  20. Hi @jpeyron, Yes sure sir. I have attached a screenshot of block design with the code of my custom IP. And base address of my BRAM is 0x40000000. Similarly I've attached SDK code for transferring data from PS to first four locaiton of BRAM. Regards, Sami IP Core.txt SDK Code.txt
  21. Hi Attila, Thank you very much for your reply. Will try then your suggestion. Best,
  22. Just to be clear on the setup in case I did post this in the wrong place, I'm using: -Analog Discovery 2 -Waveforms Beta Version 3.11.2 64-bit Qt5.9.7 Windows 7 SP 1 -I'm using the Waveforms Spectrum Analyzer tool a lot, along with the API calls for the ADC. I do also look at the Waveforms scope for troubleshooting.
  23. @Raghunathan, Let's try a few more things here. First, can you remove the OpenLogger you have added there, and try adding it again while still on the network? What I'd like you to do differently is replace localhost with when you are at the step where WFL requests the URL for the Agent. Are you running any anti-virus software on your machine? I don't expect it to be causing you any issue (and see no reason why turning on Airplane mode would affect it) but it's still a possibility. If you are running anti-virus, turn it off for a moment and try adding the device again. Another thing to try is to connect the OpenLogger to your WIN8.1 machine and run the Agent there, but use WFL on your WIN10 machine. When you go to add the Agent, replace localhost with the IP address of your WIN8.1 machine. Even if this works its still not an ideal setup. I'm asking you to try this so that I can get a better feel as to what the real issue is here. If you try all that and it still doesn't work, then I'd like you to try a new build of the Agent. You can download that here. Let me know what your results are. I will continue to research this issue and get to the bottom of it all. I personally appreciate your patience as we work through this issue, AndrewHolzer
  24. Hi, I'm stuck in SDK. I want to control visuals by manipulating an hdmi out design, but can't seem to get my software to run properly. I cant even xil_printf nor light some LEDs on my Zybo z20. Any suggestions? head.h helloworld.c
  25. @kwilber Good point.. of course the more you read the more you become familiar with Xilinx terminology. I've posted this this before but it can't hurt to repeat it with reference to this thread. Before trying to use Vivado or build a design you should download all of the relevant device and tools user's guides and reference material from Xilinx and speed read through them.. just to get a sense of what's involved, how Xilinx presents it material, and where useful information. Very few people will read though all of this once and be an expert or remember or even understand most of it. It's an iterative process. Read some stuff.. do some stuff. After a while things will make sense and you will develop a sense of what you need to learn before trying to implement more complex designs.
  26. One of the things those new to Xilinx struggle with is the terminology. I think this thread is a good example of that. The OP was thinking in terms like schematic and symbol whereas the Xilinx concepts are block design, IP, packaging and rtl module. While @zygot is correct that DocNav is the ultimate reference, I found my DocNav searches became more effective as I became more familiar with Xilinx terminology.
  27. zygot

    AXI4 and Vivado ILA

    In my experience this message generally does refer to the tools not being able to relate constraint names to source signal names. I don't use the board design flow quite the same way as you do. I get Vivado to create an HDL for the board design schematic. It's very important to make sure that your manage this file rather than use the default setting of Vivado managing the file. I then create a toplevel file that instantiates this HDL and also all of my one code. This is also where I would put my ILA. You need to understand that when you use Xilinx IP Vivado usually creates constraints files for that IP but you won't see it listed in the GUI. You have to go though the IP directory and look for it (them). Sometimes you can wade through all of the messages and find the source of the problem but not always. In my experience the more you let Vivado manage stuff the less informed you will be by what exactly Vivado is doing... so I've learned to restrict Vivado to the extent possible. It's a little more effort for me up front but much easier to resolve problems. Just before I was about to submit this I looked over your block diagram again. Are you sure that all of it wasn't optimized out since you are no longer connecting the MIPI interface to the PS? Try my approach and start over with the full working board design. Your toplevel source should be an HDL of your choice and you can tap off the input signals to connect to your ILA. An alternate approach would be to cut out the PS altogether and just do everything in your HDL. This might get messy as you'll have to make Vivado think that all of your output signals are being used.
  28. hello, I am new to designing with pmod wifi. I want to send audio files from pc to the zybo via pmod wifi and then process it then play it via output port. is it as easy as that example showed here? Bests, Meysam Sh.
  1. Load more activity