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  2. Am I correct in assuming that there is no testbench and that rgb2grey is your toplevel entity? That is you just let Vivado decide how to simulate rgb2grey? Did you have a timing constraint for the clk period when you implemented the design? Was the timing score 0? Now that I'm trying to read your code the organization needs work. Why is all of your logic in one process? Why is the process creating output when active_i is de-asserted? Also, I'm curious as to your reasoning for changing your internal registers to type integer from std_logic_vector. Lastly, I'm having a hard time correlating the simulation waveforms to your code. I don't see a rst or 24-bit output in your code.
  3. Today
  4. I see in the documentation that the ADG612 gain switch between high gain and low gain to the ADC. I see in Waveforms Spectrum analyzer that there are many gain options: 0.01x, 0.1x, 1x, 10x, 100x. Which hardware gain setting is used in Waveforms for those gain settings? Thanks!
  5. I was able to recreate the image you show above following your instructions so maybe all hope is not lost. I am still getting really strange readings though trying to do my project. I using the AD2 to power a micro-controller with positive V+ set to 3.3V and with the the grounds tied together. In order to get an idea for how much power the microcontroller is consuming I placed a 10 ohm resistor in series with the V+ output from the AD2 and i'm trying to use the scope to measure the voltage drop across that resistor to get an idea of the current being used. Below is the view I am getting from the scope which doesn't make any sense to me. Why would it be centered around -3.212 V? The voltage drop across the resistor should be only a few mV. The square wave does make sense because the program on the microcontroller is being used to flash an LED at that frequency. Any ideas?
  6. Yesterday
  7. Hi JColvin, I borrowed a Xilinx ZC702 board and brought it up. I built a Vivado project, generated bit file and SDK. I can run LED tests via GPIO with ZC702. We really want to use Zedboard since it is smaller. How much work involved to bring up Zedboard? what is included in the Zedboard package? How many useful I/O in Zedboard? Thanks, Shuguang
  8. these two photos maybe a little more revealing about my problem.
  9. @askhunter It's not clear from your pictures what it is that you are referring to since the times scales are different. The purpose of post place and route timing simulation is to show the relative signal path delays in your implemented design as well as possible inferred latches or registers hidden by IP. The RTL simulation merely indicates if your behavioural logic is performing as you intended ( assuming that the testbench is well designed ). It is merely a simplified (no delays, no setup, no hold times) idealistic representation of simple logic. If the timing simulation doesn't give the same results as the RTL simulation then it's unlikely that your hardware will behave as you intend either. In the typical professional setting a lot of people are working on parts of a large design effort simultaneously. No one can afford to schedule a design effort where everything is done sequentially. In such a case timing simulations become a very important indicator of risks of projects not making deadlines. It simply isn't possible to create a lot of hardware, software, test protocols etc sequentially or even in parallel and 2 weeks before shipment throw all that stuff together for the first time and then figure out why things don't work. So we have a lot of ways to do simulation that offer increasingly more accurate, and hence reliable, views of how our design ( after it's been optimized, re-worked and reduced to LUT equations ) might actually work in a system before having to run it in hardware. When there are 10 engineers doing parts of 1 large FPGA design and all of those parts are integrated it's not uncommon for some of them to start failing due to limited routing resources and clock line limitations.
  10. Hi, I am currently running the Pmod WiFi TCP demo on two zedboards and encounter an issue as below: For the server, it gave me a status 0x10003A00. For the client, it gave me a status 26845304. Unfortunately I cannot figure out the definition of the IPstatus in the demo. I checked my vivado project and zedboard setup, which seemed to be correct. I am using USE_WPA2_KEY with the same ipv4 address, ssid, and password btw. Is there any hint for debugging based on the current information? Thanks in advance.
  11. My my... I'm not sure what LFSR you are using but mine have a shift enable input so that I can use any clock that's available but update the LFSR output at almost any update rate needed. You can create a counter to control the shift enable so that it's synchronous with whatever logic is running at 8 KHz and needs data at that rate. It's typical in a design to have lots of parts of the logic changing states at lots of different frequencies. You don't want separate clock domains for all of those rates even if those clocks are derived and phase coherent. Sometimes, for high speed applications you do need a higher, phase coherent clock; like in video where there might be a reference clock and a higher but synchronous pixel clock. In general it's best to have the minimum number of clock domains in a design that you can get away with. FPGA devices don't have long analog or combinatorial delay lines on the order of microseconds or milliseconds. The Series 7 devices do allow adding very small delays to signals coming into FPGA pins via the IDELAY2 primitive. If your device has outputs on pins on an HP bank you can also add similar small delays to output signals using the ODELAY2 primitive. Synchronous delays lines using counters and enables as I mentioned before are the normal way to achieve teh equivalent of the analog delay line that used to be part of some digital logic long long ago.
  12. Hi , I need to use 8 kHz as a clock signal for my LFSR IP core in my block design. But this low rate can not be implemented in ARTY 7 , as shown in the attached picture ! What are the other choices I have in order to achieve the output of LFSR at the low rate that I want ? I read about delays in FPGA , but I found delays are not synthesized in FPGA ! Looking for your help, Thanks
  13. @jpeyron if I ignore the critical warnings and generate the project and start SDK I will have problems making the board support package. See the screenshots below. Interestingly the KYPD also has a wrong board setting as the SD IP (arty instead of nexys-a7-100t) but it will work in SDK. Thank you for your help.
  14. Thanks Jon and Zygot, I appreciate the explanation. Regards
  15. Hi, I design a module for rgbtogrey. When i start post implementation timing simulation,I get the following result.(gryodata) Everything was seamless until post implementation timing simulation, but here I came across something like this. I would be very happy if someone could help me with this subject. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.types.all; entity rgb2grey is Port ( clk : in std_logic; active_i : in std_logic; active_o : out std_logic; rgb_in : in std_logic_vector(23 downto 0); gry_o : out std_logic_vector(7 downto 0) ); end rgb2grey; architecture Behavioral of rgb2grey is signal active,active2,active3,active4: std_logic:='0'; --signal temp_gry,temp_gry2,temp_gry3,temp_gry4 : std_logic_vector(7 downto 0):=(others=>'0'); signal temp_gry,temp_gry2,temp_gry3,temp_gry4,tempy_reg,temp_son : integer:=0; --temp_gry<= std_logic_vector(to_unsigned((to_integer(unsigned(rgb_in(7 downto 0))) + to_integer(unsigned(rgb_in(15 downto 8))) + to_integer(unsigned(rgb_in(23 downto 16))))/3,8)); BEGIN process(clk) begin if rising_edge(clk) then if active_i='1' then temp_gry<= to_integer(unsigned(rgb_in(7 downto 0)))/3; temp_gry2<=to_integer(unsigned(rgb_in(15 downto 8)))/3; temp_gry3<=to_integer(unsigned(rgb_in(23 downto 16)))/3; active<='1'; else active<='0'; end if; temp_gry4<=temp_gry+temp_gry2; tempy_reg<=temp_gry3; temp_son<=temp_gry4+tempy_reg; gry_o<=std_logic_vector(to_unsigned(temp_son,8)); active2<=active; active3<=active2; active4<=active3; end if; end process; -- gry_o<=temp_gry3; active_o<=active4; end Behavioral;
  16. Thank you @jpeyron for your answer. I tried using the on board SD and the external, none of them were working. In the following set up I use a PmodOLEDrgb and a PmodSD (onboard config) IP block. The OLED IP works fine, when I add the SD IP, problems occur. I validate te design: Following warnings appear: When I press generate Bitstream following critical warnings appear: I use the hotfix-PmodOLED_RGB library: When I go check the files, for the working OLED and the not working SD I see that in the SD files the wrong board (arty instead of nexys-a7-100t) is set: So can I just change the lines in the files to make it work? Is it a problem in the hotfix library that Digilent needs to solve? Thank you for your help!
  17. Hello, I have a problem concerning the Digital Discovery using the Waveforms SDK. I thought it is possible to use the full 256MBytes on-board recording memory for 8-bit sampling, but I am only able to read 64M samples, no matter if I use 32 bit, 16 bit or 8 bit sampling (which I configure with the function FDwfDigitalInSampleFormatSet). The maximum size I can set via FDwfDigitalInBufferSizeSet() is 64M (i.e. 67108864), no matter what sample size I set via FDwfDigitalInSampleFormatSet(). That is, if I try to set a higher value for the buffer size, FDwfDigitalInBufferSizeGet() will still return 67108864, regardless which sample size is set (8, 16, 32). So I thought this buffer size value is the value for 32-bit sampling, and therefore 4 times as big when using 8 bit sampling. But unfortunately, when I try to read the data via FDwfDigitalInStatusData(), with a countOfDataBytes value that is higher than 67108864, all bytes after the 67108864 byte are zero. I am using single aquisition mode, and start an aquisition with FDwfDigitalInConfigure(handle, true, true) and then wait until the device state becomes DONE. I would be very thankful if someone could explain what I am doing wrong here. The Waveform GUI seems to be possible to do that (64M samples for 32 bit sampling, 256M samples for 8 bit sampling), so I thought it is possible with the SDK, too. Thanks.
  18. @PG_R Typically Ethernet PHY devices such as the Marvel 88E1111 are optimized to work with Cat5e cables. The interface between the PHY and the FPGA is immaterial; it doesn't make any difference whether it's RGMII, GMII, or SGMII. As long as the PHYs on both boards are setup properly to communicate at a particular speed, say Gigabit, and auto-negotiate you can just connect a cable between the boards and the PHYs will establish a connection without any assistance from the FPGA logic or ARM cores. Of course when the PHY is connected to FPGA logic then RGMII and SGMII is a bit more complicated, especially if you want to support 10/100/1000 rates. Most PHYs can be set to automatically switch input/output signals on the cable side so there isn't a driver conflict ( you needn't worry about using a cross-over cable ). The bad news is that programming many Ethernet PHYs is not always easy... the Marvel products require an NDA to see the register functionality. The good news is that for Xilinx and Digilent FPGA boards the PHYs are typically initialized on power-up or reset in the proper mode. For Intel based FPGA boards this is not the case as Intel wants you to be dependent on their IP to use the Ethernet PHY; this extends to their partners in crime. I've used the Ethernet PHYs to pass data between FPGA boards for many years. The next question then becomes; Do you want to use a MAC? For Zynq based boards the Ethernet PHY is connected to the ARM core through a MAC in the PS.. no getting around the MAC. For boards where the PHY is connected to logic you can do anything that you want. Once the PHYs on your boards have auto-negotiated a connection you will be responsible for the actual passing of packets and supporting particular protocols.
  19. Thanks for your help, I am sorry to say i am having problem with vivado identifying my ARTYS7 connected to my laptop
  20. Hi @KevL The Scope inputs are differential but not floating. A common ground connection between the analyzed circuit and device is needed. Without such the measurements can be wrong or the device and the circuit can be damaged. https://reference.digilentinc.com/reference/instrumentation/analog-discovery-2/reference-manual#scope Connecting a floating battery is fine, since this gents balanced through the 1M scope input impedance. To test if the scope/awg is working you should connect the Scope 1+ (orange) to AWG W1 and Scope 1- (orange/white) to GNG (black) wire, generate and capture some signal.
  21. Esti.A

    OpenCV and Pcam5-c

    Hi @bogdan.deac, I followed your instructions but I found a error message while booting from the sd card the reVision platform that says the following: U-Boot 2017.01 (Aug 05 2018 - 22:17:14 -0700) Model: Zynq Zybo Z7 Development Board Board: Xilinx Zynq I2C: ready DRAM: ECC disabled 1 GiB MMC: sdhci@e0100000: 0 (SD) Using default environment In: serial Out: serial Err: serial Net: ZYNQ GEM: e000b000, phyaddr 1, interface rgmii-id SF: Detected s25fl128s_64k with page size 256 Bytes, erase size 64 KiB, total 16 MiB Warning: ethernet@e000b000 using MAC address from ROM eth0: ethernet@e000b000 U-BOOT for Zybo Z7 ethernet@e000b000 Waiting for PHY auto negotiation to complete......... TIMEOUT ! Hit any key to stop autoboot: 0 Device: sdhci@e0100000 Manufacturer ID: 1d OEM: 4144 Name: SD Tran Speed: 50000000 Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 58.9 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes reading image.ub 3910868 bytes read in 340 ms (11 MiB/s) ## Loading kernel from FIT Image at 10000000 ... Using 'conf@2' configuration Verifying Hash Integrity ... OK Trying 'kernel@0' kernel subimage Description: Linux Kernel Type: Kernel Image Compression: uncompressed Data Start: 0x100000d4 Data Size: 3878632 Bytes = 3.7 MiB Architecture: ARM OS: Linux Load Address: 0x00008000 Entry Point: 0x00008000 Hash algo: sha1 Hash value: 4b23816e227252b7549419997f26b3edbd525a7e Verifying Hash Integrity ... sha1+ OK ## Loading fdt from FIT Image at 10000000 ... Using 'conf@2' configuration Trying 'fdt@0' fdt subimage Description: Flattened Device Tree blob Type: Flat Device Tree Compression: uncompressed Data Start: 0x103b30b0 Data Size: 30941 Bytes = 30.2 KiB Architecture: ARM Hash algo: sha1 Hash value: 6bda90ed3c9361add0bd7bb38aeb560c25288661 Verifying Hash Integrity ... sha1+ OK Booting using the fdt blob at 0x103b30b0 Loading Kernel Image ... OK Loading Device Tree to 07ff5000, end 07fff8dc ... OK Starting kernel ... Uncompressing Linux... done, booting the kernel. Booting Linux on physical CPU 0x0 Linux version 4.9.0-xilinx-v2017.4 (digilent@ubuntu) (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11)) #1 SMP PREEMPT Mon Jul 9 19:13:02 PDT 2018 CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache OF: fdt: Machine model: Zynq Zybo Z7 Development Board bootconsole [earlycon0] enabled OF: graph: no port node found in /amba_pl/xilinx_drm EXT4-fs (mmcblk0p2): couldn't mount as ext3 due to feature incompatibilities INIT: version 2.88 booting Starting udev udev: Not using udev cache because of changes detected in the following files: udev: /proc/version /proc/cmdline /proc/devices udev: lib/udev/rules.d/* etc/udev/rules.d/* udev: The udev cache will be regenerated. To identify the detected changes, udev: compare the cached sysconf at /etc/udev/cache.data udev: against the current sysconf at /dev/shm/udev.cache Populating dev cache ALSA: Restoring mixer settings... No state is present for card ZyboZ7SoundCard Found hardware: "Zybo-Z7-Sound-C" "" "" "" "" Hardware is initialized using a generic method /usr/share/alsa/init/default:26: value write error: Input/output error /usr/share/alsa/init/default:26: value write error: Input/output error /usr/share/alsa/init/default:263: value write error: Input/output error /usr/share/alsa/init/default:263: value write error: Input/output error /usr/share/alsa/init/default:265: value write error: Input/output error No state is present for card ZyboZ7SoundCard hwclock: can't open '/dev/misc/rtc': No such file or directory Tue Jul 10 02:14:48 UTC 2018 hwclock: can't open '/dev/misc/rtc': No such file or directory Starting internet superserver: inetd. INIT: Entering runlevel: 5 Configuring network interfaces... udhcpc (v1.24.1) started Sending discover... Sending discover... Sending discover... No lease, forking to background done. Starting system message bus: dbus. Starting Dropbear SSH server: dropbear. hwclock: can't open '/dev/misc/rtc': No such file or directory Starting syslogd/klogd: done Starting tcf-agent: OK as you can see it is not finding this device and I dont know if this causes not to display any image in the hdmi. I am using filter2d demo, as is suggested for PCAM-5c set-up.
  22. Hi @DurandA Please disable the data compression to prevent this issue, to make sure the last digital samples are recorded at such low rate.
  23. Hi I'm using pmod CAN module to communicate between zybo z7-10 and tms570LC4357 launch pad(Texas Instrument). The connection is like this : zybo z7-10( - Pmod CAN module) ----------------- CAN trasceiver(SN65HVD230) -- tms570LC4357 launch pad I took a test with zybo z7-10 - tms570LC4357 launch pad(bit rate = 250kbps), the oscilloscope graph is the graph with delta x = 82us, 1/delta x = 12.2KHz. And CAN doesn't work.. (the probe is picking CANH(red), CANL(yellow) in Pmod CAN module) I'd like to change bit rate, so I took a look the datasheet ( mcp25625). And change registers CNF1, CNF2, CNF3 CNF1 (0x41) -> (0x09) CNF2 (0xFB) -> (0xFF) CNF3 (0x86) -> (0x87) 250kbps -> 40kbps but...! the graph's period doesn't change at all.. Is there anything I shall do more things to change bit rate? Sorry for bad english.. please answer.. thx!!
  24. Hi @Luighi Vitón, Thanks for your reply and for your heads up, I'm glad you managed to get it working. --Ciprian
  25. Hi @DurandA The digital channels can't be accessed from the Logger tool, but you could perform a recording in the Scope with low rate like this: From Script you can access the StaticIO readings or captured data in Logic or Scope like this:
  26. Szia @Andras At the moment you have WAV RIFF WAVE export under Scope/View/Logging/Script/Example.
  27. Hi @Frenchpark43 It should work, it is working for me on Ubuntu 18.04 amd64 You could try install with: sudo dpkg -i --force-depends digilent.waveforms_3.9.1_amd64.deb
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