All Activity

This stream auto-updates     

  1. Past hour
  2. Thank you very much, @attila; I guess for the first experiment we can keep it simple and neglect temporal jitter/drift during time scales < 10 µs.
  3. Hi @JColvin @rprr It looks like all the USB 2/3 ports of RPi4B are working reliably with AD2. I have updated the post:
  4. Today
  5. Hi @attila F argument worked! Thank you for the all the quick replies and help!
  6. Hi @tdavismn The latest WF beta version adds dBm, dBm/Hz, dBm/MHz units for the Spectrum Analyzer and Scope FFT:
  7. Yesterday
  8. Hi @sgandhi, The attached echo.c shows how to take the typed text off of tera term on the PC and compare it to a pre-selected string and then send a pre-determined string back to tera term through the ethernet connection. I would suggest looking here: C:\Xilinx\SDK\2019.1\data\embeddedsw\ThirdParty\sw_services\lwip202_v1_2\examples for better examples for a web server using the LWiP. I would also suggest looking for more detailed xilinx information here. best regards, Jon
  9. Hi @jpeyron, So, do I just change echo.c using the file you provided? I am even suppose to change main.c when using the template of lwIP echo server in the SDK? Thanks for the reply, Shyama.
  10. Hi! Nowadays i have get Zedboard) and decided to try on it soft core MicroBlaze. I created project and add IP cores in analogy with my experiment with Arty A7-35. In Arty DDR3 has been added avtomation, in Zedboard i written adreses manual in XDC for each pins : It is in .XDC file: #MEMORY DDR # ddr3_dq_0 set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[0] }]; set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[1] }]; set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[2] }]; set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[3] }]; set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[4] }]; set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[5] }]; set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[6] }]; set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[7] }]; set_property -dict { PACKAGE_PIN AA22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[8] }]; set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[9] }]; set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[10] }]; set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[11] }]; set_property -dict { PACKAGE_PIN AB19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[12] }]; set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[13] }]; set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[14] }]; set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[15] }]; set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_p_0[0] }]; set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_p_0[1] }]; set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_n_0[0] }]; set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_n_0[1] }]; #ddr3_addr_0 set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[0] }]; set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[1] }]; set_property -dict { PACKAGE_PIN AB16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[2] }]; set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[3] }]; set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[4] }]; set_property -dict { PACKAGE_PIN AA17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[5] }]; set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[6] }]; set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[7] }]; set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[8] }]; set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[9] }]; set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[10] }]; set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[11] }]; set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[12] }]; set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[13] }]; set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[14] }]; #ddr3_ba_0 set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ba_0[0] }]; set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ba_0[1] }]; set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ba_0[2] }]; #ddr3_ras_n_0 set_property -dict { PACKAGE_PIN AA14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ras_n_0 }]; set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_cas_n_0 }]; #ddr3_we_n_0 set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_we_n_0 }]; #ddr3_reset_n_0 set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_reset_n_0 }]; set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ck_p_0[0] }]; set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ck_n_0[0] }]; set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_cke_0[0] }]; set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dm_0[0] }]; set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dm_0[1] }]; #ddr3_odt_0 set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_odt_0[0] }]; # DDR3 STOP After start generating Bitstream i get ERROR: [DRC MDRV-1] Multiple Driver Nets: Net system_i/mig_7series_0/u_system_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/write_buffer.wr_buf_out_data_reg[112]_0[0] has multiple drivers: system_i/mig_7series_0/u_system_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/mem_reg_0_15_0_5_i_4/O, and system_i/mig_7series_0/u_system_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/mem_reg_0_15_0_5_i_5/O. DRC report in Syntesys are next: and InOutTerm #1 IO Standard LVCMOS33 does not support IN_TERM, but I/O port ddr3_dq_0[0] has IN_TERM set to UNTUNED_SPLIT_50. What is mean @IO Standard LVCMOS33 does not support IN_TERM@ ??? How to fix it??? Best regards.
  11. 1. The documentation says, "The analog inputs has the following features, 500 kS/s aggregate input." By aggregate, does it mean that if I record all 8 analog channels, the data rate is (500 kS/s divided by eight channels = 6.25 kS/s per channel? 2. Suppose I record only one analog channel at the 500kS/s conversion rate. The documentation says the logger has a max logging rate of 400 kS/s. Thus the conversion rate is greater than the logging rate. Will OpenLogger be able to log data for say 1000 samples without losing data or is the conversion rate effectively throttled down to the logging rate? 3. Digilent is calling their analog outputs "DC Power Supplies". Isn't the so-called power supply outputs powered by nothing more than Digital to Analog Converter chips? Why use the foreign terminology and just call them the industry typical DA outputs? You don't have to answer this one, just a peeve of mine.
  12. Hi @mustafasei, Here is a LabVIEW MakerHub forum thread that discussed having a PI controlling an Arduino. best regards, Jon
  13. Hi @sgandhi, I have attached an altered echo.c that might help you better understand process. I would also suggest looking into the TCP or UDP client/server templates in SDK as well. best regards, Jon echo.txt
  14. Hi How the port will appear on .vi if I connect the arduino to the RPI USB port?? because I cannot see the COM port for the arduino on the .vi of RPI is there any recommendation for this connection ?? please advise
  15. Hi, We bought Analog Discovery Studio. It works fine with the waveform software. But the MATLAB R2016a cannot even identify this devise. I have "Data acquisition toolbox" and "Data Acquisition Toolbox Support Package for Digilent Analog Discovery Hardware" installed. Could you tell me what else should I install in order to have matlab identify Analog Discovery Studio? Thanks a lot
  16. Hi @Dareamol, Welcome to the Digilent forums! Here are the basic steps to getting the hello world project working. In Vivado: 1. Makes sure the board files are installed and you select the zybo-z7-10 when creating the project. 2. create a block design 3. add the zynq processor and run the default(board files) block automation. 4. connect the axi-m-gp0-aclk pin to the fclk_clk0 pin on the zynq processor. 5. right click on the design in the sources tab and create a wrapper letting vivado handle it. 6. generate a bitstream. 7. Export the hardware including the bitstream. 8. Launch SDK In sdk: 1. once sdk has fully loaded with the hw_platform them click on file and add a new application. 2. give it a name and leave everything else as default. select next. 3. Select the hello world template. 4. program the FPGA 5. Open a serial terminal emulator like tera term and connect the com port of the Zybo-Z7-10. Make sure to adjust the baud rate to 115200 and typically leave all of the other settings at default. 6. right click on the application and select run as->launch on hardware(system debugger) and you should see hello world on the serial terminal!!!! best regards, Jon
  17. Thanks @attila I am using Terminal program to check the data output. Im using a USB to Serial adapter to the pc. Looks like the problem was the polarity. Once I changed it to inverted the data started working correctly. Thank you for the help!! Matt
  18. Hi @Matt B I don't know how, what application are you using for UART reception... Is the same UART Rate specified on both sides? also verify the parity, polarity.. Do you have common ground connection between the devices?
  19. Hi @attila I adjusted my code to convert to text and I am not getting the desired text. Do you have any ideas?
  20. Hi @osti 1. The Sync mode on Digital Discovery uses re-sampling at 1.25ns (800MHz) resolution. This uses the device triggering mechanism, so when using Sync mode the trigger options are not available. 2. At the moment only 100MHz base frequency is supported. I'm planning to add option to be able to fine adjust this frequency, like: 50.00836820083682, 50.00985221674877, 50.01197604790419, ... 98.86567164179104, 98.87323943661971, 98.88, ... ,99.97714285714285, 100 MHz
  21. This solution seems to be suitable for AXI-based projects... whereas I'm using PLB 😢 That's sad...
  22. It would probably be more useful for you to know why you were having issues. As you found out, it is possible to create a Verilog module that can't be instantiated in VHDL. Specifically, try declaring your module port IO without wire or register assignments. I know, it involves more writing as you'll have to add wire and reg assignments anyway. There is no std_logic_vector equivalent in VHDL for the Verilog reg. I supposed that you get points for finding a work-around but then you also get deductions for claiming that you've solved your problem... Friendly advise. Instead of seeing issues as obstacles to be avoided see them as opportunities for experimentation and learning. You'll be much more productive and happier in the long run.
  23. I might answer partially my own question as I have found this tutorial : How To Store Your SDK Project in SPI Flash It is for Vivado but with a little luck, this might work for ISE 14.7 too. I'll post some time soon to tell you if I managed to have it work or if I need help !
  24. Can anyone suggest me how to program the UART/USB available in the ZYBO Z7 board and use it as a port to feed the data from the PC/SERVER ?
  25. @JColvin, Thanks for a quick reply. I will get the cable changed then. I just hope it won't be difficult for our purchase dept. Anyways, Cheers!
  26. @hamster, thanks for reply and problem solved, yet in another way The vhdl file is in a block design, so vivado cannot identify my verilog module directly. I'm doing package works now.
  27. Maybe remove the 'reg' from the Verilog port definition?
  1. Load more activity