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  2. Hi @mehdi, How did the EEPROM get erased? And you are using the JTAG HS2 with a Xilinx device of some kind? Are you not able to see the JTAG HS2 in Digilent's Adept program? Thanks, JColvin
  3. I require the download site for the zc2020 image processing factory image for programming an sdcard. I have searched Diligent sites but I have not been able to find it. Thank You Tom
  4. Hi @mustafasei, I reached out to another engineer about this, but unfortunately they did not have any additional advice for what could be attempted. Thanks, JColvin
  5. Inclusion of the ps7_init and HDF file in the application project src folder (and the ps7_cortexa9_0 folder in the _today project) looks very strange to me. It also seems to have caused a lot of errors when I opened the workspace and built it on my system, so I am not sure if something strange happened when sharing the workspace. If this reflects what you have on your system, you could try just creating a new Hello World application project to confirm that the exported hardware is valid, and that you can program and communicate with your board. <-- This is what I would expect the application project to look like. (Error is a result of using sources from another HDMI demo with differently-named IPs)
  6. Hi Attila, do you have another product or variant of this product that has this kind of playback capability?
  7. Hi @Serdar Unfortunately it is not supported. The custom pattern is limited to 32k/channel.
  8. link:
  9. Needed to double check. Have you connected a serial terminal (Tera Term or whatever)? If so, what is being printed by the demo? For what it's worth, I've seen similar projects halt on "printf" statements before, depending on Vivado version and the board used. xil_printf generally works fine, but does not accept floats. Here's a diff of a fix for that issue. Could you zip and share your SDK workspace?
  10. Have you programmed the hardware and run the demo application in Xilinx SDK? Both the hardware and software must be running on the board to get an image.
  11. Hello! Yes of course. I have used it. With best regards, Mikhail.
  12. Hi, tried it by moving the jumper JP6 to jtag mode. But no signal in the display.
  13. Looks like the board may be booting the out-of-box demo from QSPI flash. It is still possible to program it while this is happening, but you may still want to move the JP6 jumper to JTAG mode. -Arthur
  14. The Nexys Video is a -1 part with maximum LVDS rates <= 950 Mbps ( less than the ATLYS Spartan 6 board ). LVDS is a 2.5V or lower standard and TMDS for HDMI is 3.3V so you'd expect data rates to be higher for lower voltage signalling. For educational purposes and home projects this doesn't mean that you can't achieve data rates at toom temperature above this for any specific design. For commercial projects or professional projects it's wise to observe the AC switching specifications for your part. Data sheet specifications are guaranteed and **tested** performance numbers. You might be lucky and get a device that performs near the point where some of the specs might have made it to the next speed grade but don't count on it. Saying that a board works fine for out-of spec designs is one thing; hooking up your board running the applicaiotn to professional grade measurement tools and citing actual properly made measurements is another... not that I'm saying that hamster is wrong. **tested** is something that needs to be researched carefully and probably doesn't mean wht you think it means.
  15. Attila, thanks for the response. We want to import from a file in which every line (sample) has 6 bits of information. 32K samples is too small for us. Is there a way to handle much larger number of samples (eg. 10M samples)? This data is coming from an audio sample file so we can't create these samples with a script.
  16. Hi,Please help me,my programmer don't work because of e2prom erasing, thanks
  17. Thanks for posting your code Peggy, Iv'e managed to use it to view some data. Did you find out any more about what is in the header? Maybe that contains things like number of channels, sample rate etc?
  18. I've recently added two more boards to the list of DUTs that this tester works with. When Intel announced the Cyclone 10 family and I realized that instead of making the Cyclone family a better product it was an opportunity to further fracture Cyclone devices into more low end and less useful products and push customers into paid tool subscriptions (Cyclone 10 GX) I lost interest. I did recently get the Cyclone 10LP development board for a project ( there's not much out there to choose from so I must not have been the only one to lose interest ). The part is a really small device with minimal resources but the board has an 8 MB HyperRam, a 1G Ethernet interface and reasonable IO for $99. Hmmm.... this board would make a nice optical sensor video server using one of Terasics' add-on boards. I've had the MAX10 Development Kit for about 2 years now and spent quite some time trying to implement the Ethernet interface ( it has 2 1G ports! ). MAX used to be a PLD but these days looks more like a Cyclone without full IO support. I put the board on the shelf but decided to give it another whirl having ported an Ethernet PHY DUT so easily for the Cyclone 10LP board. This time things went smoothly though Quartus is doing some magic that isn't obvious to anyone trying to do the same thing from scratch for the device. The device on this board is quite large, there 2 1G Ethernet ports, an HSMC connector and DDR3 external memories. The price is about 2x the $100 I associate with cheap usable FPGA development platforms but it is quite capable. There are a number of options here for anyone wanting to do something with 2 100+ MHZ ADC/DAC channels on a tight budget. It would for sure be nice if I could find an equivalent Xilinx Series7 board for either of these.
  19. Hi @Mahmood ul Hassan, I just tried and it works. You have to fill in the form and the download will start. Regards, Bianca
  20. Well you are partially correct. There certainly are differential logic standards for 3.3V logic. Decades ago 3.3V IO was the cutting edge and differential logic has preceded FPGAs by decades. But not since the Spartan 3A have any Xilinx devices that I can think of supported a differential IOSTANDARD for IO Banks powered by 3.3V Vcco. It is possible, though arguably not practical, to add termination allowing differential reception, in a board design. The question is why would a company continue to put such connectors onto their boards, in the face of Xilinx documentation to the contrary, after having been called out by customers, without ever providing a PMOD designed to use it, basically wasting up to half of the IO pins provided on their development boards, when an suitable alternative is so trivial to implement. Why would an FPGA vendor put up with a partner subverting students and customers from learning how to use their devices in all of their glory? Why ponder questions that will never be answered? If you want to experiment with LVDS or differential IO on an FPGA find a board that is designed to let you do so. Finding such a board is a question for which there are answers.
  21. Thanks for respond: Do you have any source where exactly performed those process (cross-compile) for sdr adrv9361 board or any other fpga board?
  22. Hi @Serdar You could use a custom Bus and import data from file (up to 32k/channel) or use Script to generate custom pattern or parse the imported data.
  23. Hi @m72 After adding the Order option in Logic Analyzer (splitting the Input selection in two) I have forgotten to update the Protocol/Logic Analyzer to set the Order option automatically. Thank you for the observation, it is fixed for the next release.
  24. Hi @m72 This looks like a digital issue in the ADC. Have you used for this tests the WF v3.11.23 I sent you in private message?
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