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  2. Hmm, it looks like I configured my Audacity to use 32-bit float sampling by default, and it loads every WAV as it were 32bit-float. Strange, and a little misleading, I need to be more careful next time, because that lead me to believe that 32-floats are supported in Python. My bad, sorry. Anyway, I'm testing the script, I have a few questions: The vAmplitude is the amplitude of the wavegen and as I change it I can confirm the change in the WAV file. The scope also has the vAmplitude parameter, set to the same value as the wavegen. What does that exactly mean for the scope? If both the generator and the scope have the same vAmplitude, shouldn't the captured data (in the WAV file) always reach its peak value when the sine wave is at its peak? You made a change so that the data is saved into memory during the recording and the file is only written at the end of the acquisition. It could be alright, but when I set the nSamples to a value which covers the whole night, start the script and then stop it within let's say 3 seconds, I'll get a huge file with a tiny amount of usable data at the beginning. Is there a way to change this, and only write the captured data? Also the nSamples must be fit into a int, so capturing 8 hours can be done only at lower sample rates. Is there an efficient way to do the wave saving continuously, so that there is no time or sample rate limitation (except the free space on the drive, of course)?
  3. Today
  4. Here you have a dwfcmd build which continues the generation after quitting the application: dwfcmd.exe It requires WF v3.8.15 or newer! You can get the latest beta version from here: In very old software versions the device was stopped on close, later this was changed to continue and since v3.8.15 it has an option for this matter: in SDK: FDwfParamSet(DwfParamOnClose, 0 continue, 1 stop, 2 shutdown) and in the application under the device options.
  5. Szia @attila, Cool, I'll try it right away. The mistake I made is that I supposed that FDwfAnalogInStatusData returns 32-bit floats, not 64-bit doubles. Also, I didn't know about FDwfAnalogInStatusData16 which returns 16-bit integers. The other problems arose from this wrong presumption... Python's wave supports both the 16-bit integer and the 32-float format, but not the 64-float.
  6. Szia @Andras The Python should look like this: This records and saves raw uncalibrated scope ADC data of 16bit signed values. Imported looks like this: In your code with the 1.41V offset and 1.41V amplitude signal top value was 2.82V which with scope range of 5V, +/-2.5V peak entered in limitation. It was appending separate captures to wav file instead of continuously recorded data, the Python wave might not support 32float format.
  7. Szia @attila, alright, thank you for making it clear!
  8. Oh, thanks Attila, your command works!!!. But I wonder why the same built command worked in my previous setup using my laptop and is not Working in the new. To develop a little more the issue: in my tests I setup a StartWaveform(...) and StopWaveform() functions ; I usually run the Start and in the middle I run some additional stuff (time variying from test to test), finally whenever I fininsh I run the Stop. In the Start function I've never used the pause, evenmore I would say I could not use it in order to get the execution focus immediately to the 'script' and do additional stuff as the Waveform is running in backgorunf Do you have any hint why this behavior might have changed from one PC to other; (in concrete, the use of the pause)
  9. Hi @Alberto The device is stopped when the application quits. In order to have signal output running use for instance the pause argument, like this to run for 10 seconds: DWFCMD.exe connect analogout channel=0 enable=1 sine frequency=1k amplitude=1 start watch=0 pause=10
  10. Szia @Andras This is a completely different library than the one provided by the FTDI. In order to use this the Adept Runtime would need to be modified. On the other hand I don't see in this lib support for the FIFO data transfer mode nor the MPSSE used by AD, so it is unusable for this purpose.
  11. Hi @skaitmenukas I suppose you have different configuration for Trace than for the Ref traces. When data of multiple traces are exported in one table it takes as guideline the start/stop/samples parameters of the Trace. Make sure to have same start/stop/samples settings when Trace and all the Ref traces where made.
  12. Hi, I combined a few python scripts from the SDK (AnalogIn_Acquisition, AnalogOut_Play and AnalogOut_Sine) to write a script which is intended to run during the night and save the scope's data into a WAV file. All looks somewhat okay, but there are a few things that don't look perfect. For this test, I connected CH1 and W1 and started both the Scope and Signal generator in the script. I'm intending to generate a 80 Hz sine wave and record it with the scope running at 8 kHz. I attach the whole script, and here are the important parts: # set up signal generation channel = c_int(0) # use W1 dwf.FDwfAnalogOutNodeEnableSet(hdwf, channel, AnalogOutNodeCarrier, c_bool(True)) dwf.FDwfAnalogOutNodeFunctionSet(hdwf, channel, AnalogOutNodeCarrier, funcSine) # ! this looks like a square wave dwf.FDwfAnalogOutNodeFrequencySet(hdwf, channel, AnalogOutNodeCarrier, c_double(signalgenhz)) dwf.FDwfAnalogOutNodeAmplitudeSet(hdwf, channel, AnalogOutNodeCarrier, c_double(1.41)) # ! this doesn't really do anything dwf.FDwfAnalogOutNodeOffsetSet(hdwf, channel, AnalogOutNodeCarrier, c_double(1.41)) I played around with the parameters and after some investigation with Audacity it seems like the funcSine parameter generates a square wave and the amplitude is always 1.0 no matter what I set. The other problem I have is with the FDwfAnalogInStatusData function, it looks like it doesn't just get the raw data from the scope, is contains something else. So in order to get the scope's CH1 data, I need to have a 2-channel WAV file, and discard its first channel. The second is the data I'm looking for. waveWrite =, "wb"); waveWrite.setnchannels(2); # 2 channels for the testing (1 channel would be enough if FDwfAnalogInStatusData returned only 1 channel's data waveWrite.setsampwidth(4); # 32 bit / sample waveWrite.setframerate(samplerate); waveWrite.setcomptype("NONE","No compression"); dwf.FDwfAnalogInStatusData(hdwf, 0, rgdSamples, buffersize) # get channel 1 data CH1 - ! it looks like 2 channels get read here and only the second is the data of CH1 waveWrite.writeframes(rgdSamples); I would expect that if I only need the CH1 of the Scope, I could save it into a mono WAV file.
  13. @xc6lx45 thanks for the reply.. the issue is most of the things are for zybo z7-20 boards.. and i can understand both boards are somewhat similar but sometimes little changes require a lot of effort.. anyhow if you send me some link... i would be very thankful to you
  14. HI @osmaan_khan, To clarify on xillybus and XADC, we have never configured the design which they provide, therefore we don't know how to add the XADC IP to it and interface it with their linux kerne and rootfs. Regarding the VCC and the GND pins, the PMOD connector JA can be configured as XADC or can be used as a simple PMOD connector (following the PMOD standard you need VCC and GND), when using it in a XADC configuration the VCC and the GND can be ignored. All the information on how the XADC works, configurations and limitations can be found in ug480 form xilinx. For instance, you cannot measure a voltage grater 1V using the XADC, you will have to scale your voltage in order to measure it with the XADC (maybe use a voltage divider, it depends on you circuit). The XADC is a Xilinx IP which is configurable both from the IP configuration window in Vivado and trough some registers using the AXI-Lite interface, with a xilinx kernel you should have access to it if the XADC driver is active in the kernel and if the .dts is configured to include the IP. We cannot help you with this, unfortunately; you will have to ask the support team from xillybus about how to manage this. - Ciprian
  15. Sduru

    Vivado sysnthesis fail..Pcam

    Hello Dear @jpeyron I've already solved the problem. It was related to selecting wrong language C instead of C++ when creating new application project. PCAM project was written in C++, but I wrongly selected C! After I corrected that mistake, now there is no any linking error. Thanks...
  16. Hello, we are using the analog discovery in out test setup. I prepared several scripts to automate the validation. For the Analog Discovery control we are using the DWFCMD.exe utility application that comes with the WaveForms SDK. The point is that all the scripts that we had perfectly running in my PC has stop working in a new PC that we have prepared for the TESTs. Both PCs have the same sw versions. I've installed all the application in the same way as in my PC. It's curious that the GUI Waveforms works, the only that does not work is the DWFCMD.exe utility in the new PC. There is no error message. Here a sample of th e output: ./DWFCMD.exe connect analogout channel=0 enable=1 start Starting AnalogOut Channel 1 Starting AnalogOut Channel 2 Some extra data (may be relevant): Digilent WaveForms utility application. Version 0.1.1 OS Windows 10 Waveforms: 3.7.5 64-bit Qt5.6.3 Windows 10 Any hint about what might be failing in the command line ? Did this occur to any other in the past? Please let me know what else can I check or if you need some extra information to debug this issue
  17. OK I remember there were some recent posts on the topic I think Digilent has ported some of the code to FPGA using HLS (e.g. search for openCV, HLS).
  18. daeroro

    pmod can period

    Well, I figure out a bug in the example code. In the CAN_Configure function : // Set CAN control mode to configuration CAN_ModifyReg(InstancePtr, CAN_CANCTRL_REG_ADDR, CAN_CAN_CANCTRL_MODE_MASK, CAN_ModeConfiguration ); needs to be change like this: CAN_ModifyReg(InstancePtr, CAN_CANCTRL_REG_ADDR, CAN_CAN_CANCTRL_MODE_MASK, CAN_ModeConfiguration << CAN_CANCTRL_MODE_BIT); So it can enter the configuration mode... After changing the code, CAN communication between Zybo-z7 and MCU works really well. You need to change your git example code.
  19. revathi


    Hi @jpeyron, I would like to do differentiation function on xadc output. Will you give some basic idea or any references for doing the differentiation function over the ADC output Thanking you
  20. I am having this problem with my project under a shared folder on Dropbox. When under OneDrive (no share), no problem. Windows 10 Vivado 2018.2 [IP_Flow 19-3475] Tcl error in ::ipgui_wifi_demo1_mig_7series_0_1::updateAllModelParams procedure for BD Cell 'mig_7series_0'. error renaming "c:/Users/xxxx/Dropbox/yyyy/7.9.2/Ar_WF_WS.srcs/sources_1/bd/wifi_demo1/ip/wifi_demo1_mig_7series_0_1/_tmp/wifi_demo1_mig_7series_0_1" to "c:/Users/xxxx/Dropbox/yyyy/7.9.2/Ar_WF_WS.srcs/sources_1/bd/wifi_demo1/ip/wifi_demo1_mig_7series_0_1/wifi_demo1_mig_7series_0_1": permission denied I need it to work on Dropbox. Please, advise. Thanks
  21. hi @xc6lx45 thaks for the reply.. i have worked on openCv in Raspberry Pi and bananPi... i have done video processing in it... the reason i want to do it on FPGA is the speed... FPGA are faster then pi.. so i just bought zybo z7-10 board played with it.. try to make my self familiar with it.. tried all the demos. familiar myself with vivado and sdk. as well try to install and run petalinux.. all done.. now i dont find a way how to use open cv for the board.. any more help wil be much appreciated
  22. Yesterday
  23. Hi @jpeyron I have used your information - it has some helped me. Thanks!) 1) I have connected .XDC file (to constarints) 2) i have Created blocks like in youtube example ( and Generate succesful bitstream. Then opened SDK and get problem in downloading code to fpga (clicked PROGRAM FPGA in SDK) - i show image. SDK don't see FPGA ((( (I give rar of my project HLS + SDK What do you phink about connecting to FPGA? Best regards
  24. @tahoe250, A quick Google search should yield almost all of what you need: how to create the IP, integrate it into your design, adjust addresses, build with it, and use it in practice. Be aware, a lot of Xilinx's AXI IP (as of 2018.3) both has bugs in it and is (rather) slow. Check out this post discussing the bugs in their AXI-lite demo core, or this one showing how you can build (and verify) a core without the bugs. Dan
  25. In one of three attempts i was able to create the 100 MHz clock but then I got critical warnings during validation:
  26. I am using Vivado v2018.3 (64-bit) SW Build: 2405991 on Thu Dec 6 23:36:41 MST 2018 IP Build: 2404404 on Fri Dec 7 01:43:56 MST 2018 My procedure: Create new RTL project with "Zybo-Z7-Master.xdc" Add "vivado-library" as IP repository in project settings Create Block Design Add IP: ZYNQ7 Processing System Run Block Automation Connect Board Component: JB to PmodCAN_v1_0 Run Connection Automation But it is not possible to create the 100 MHz clock...

    fpga kit

    Sir i am using fpga kit of DIGILENT ATLYS SPARTAN -6, is this can be program by using ISE DESIGN SUIT? Is this fpga has analog to digital pin and digital to analog pin? is this can be used for controlling of power switches like MOSFET ,IGBT?
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