All Activity

Hi @JRys, Would this be able to automate the process as well for actuation of valves?

Hi @Shaq Welcome to the forum. Digilent doesn't support ModelSim. That said, if this is the top module in your simulation, you likely need a testbench and some kind of stimulus to apply to your module's input ports. Thanks, Arthur

If your budget is tight, consider the free Community version of National Instruments LabVIEW. Our LabVIEW support for the Counter Input has a timed mode. It can measure frequency in timed mode by counting pulses over a desired period. For instance, if the period is one second and it determines that 100 pulses have occurred, then the frequency is 100 Hz. Another approach is to create your own Python script to do what you want.

Perfect! That works fine - it just wasn't documented anywhere that I could see! Thanks for the "video", that would have been hard to explain without it!

Hi @Duh, You should be able drag each of the signal groups via the small rectangle on the left hand side next to each group. It's not particularly visible when compared to moving a browser tab but it should work: Logic_move_signals.mp4 I don't think you can readily change the order of things within a bus though (such as the chip select and clock within SPI), at least as far as I can tell. Maybe the WaveForms developer (not me) will consider that option for a future update. Let me know if you have any questions. Thanks, JColvin

Is there any way to re-order signals that have been previously defined in the list of signals? I have a list of previously defined signals and have added a new signal. It appears at the bottom of the list and is only visible by using the scroll bar. I can't compare it to signals higher up in the list, so I would like to move it upwards in the list. I would like to be able to drag the various signals around for comparison to each other for various tests that I am performing. Most logic analyzers allow you to drag and drop signals in the list to re-order them. Thanks!

Thank you @AKA . I was having a similar problem myself but the delay fixed it ! Edit by JColvin: deleted the mass slew of duplicate posts. Uncertain of the cause.

The ... button on each comment should have the option to delete:

It's odd that the heap is overflowing the local memory by the same number of bytes. Feels like it might indicate that it's still out of sync with the updated spec somehow, but I'm not sure - the instructions you found for switching out the XSA are the correct ones. I'd be curious whether a new application project with the same source files and the new XSA still presents the same bug. You could also potentially try reducing the heap size in the linker script. It doesn't solve the problem of the updated address map not getting applied, and could lead to overflows, but to just get something working initially... The screenshot below is from a Zynq project with DDR, so yours will look a little different, but this is where to find the heap size setting: If you end up uploading the Vitis project, please use the File -> Export menu instead of zipping the folder in Explorer, as there are a bunch of absolute paths in various files that the software needs to update when the workspace gets moved or copied.

Hi @Clyde, The Analog Discovery 3 has 9 MHz bandwidth unless you're using the BNC Adapter which bumps the bandwidth up to 30 MHz: https://digilent.com/reference/test-and-measurement/analog-discovery-3/specifications#analog_input_channels, though the ADP3250/ADP3450 both have the 55 MHz analog input bandwidth like you indicated (ADP2230 has 50 MHz bandwidth for its two analog input channels). Regarding a SPI bus transaction on the AD3 specifically, I would probably be using the Logic Analyzer instrument on the digital channels and have a result more like the splash screenshot I took for AD3 reference manual: https://digilent.com/reference/test-and-measurement/analog-discovery-3/reference-manual#logic_analyzer. If you're instead looking for a more traditional MSO setup, you could use the Digital view inside the Scope instrument to view both the digital and analog input channels in a time correlated fashion (rather than having the logic analyzer and oscilloscope run simultaneously in two separate windows) along with the option to interpret one of the analog input signals as part of the digital bus directly, much like I've done here with the Scope Channel 1 being subbed in for the SPI peripheral out controller in line (MISO): The catch with style is that the analog to digital interpretation is done in WaveForms, so you won't have the option to do any digital protocol triggering on a bus utilizing an analog input. If they are separated out, like how MISO is, you can still trigger off of the digital protocol values, like how I did above to trigger on the h40 value for MOSI. If you're looking to analyze digital protocols directly within WaveForms though, I personally think you'll have an easier time with either the ADP3250/3450 or the ADP2230 since they both have on-board DDR memory. That'll let you get much longer captures relative to the Analog Discovery 3 which are more helpful for digital protocols where there can be a comparatively long amount of downtime between the fast bursts of communication. The point is moot of course if you're only ever looking at a few frames at a time. Let me know if you have any questions. Thanks, JColvin P.S. The Analog Discovery Pro 5250 (a rebranded version of the NI VirtualBench 8012, now sold by Digilent) also has 100 MHz bandwidth for it's two analog input channels, but it lacks DDR memory and has a different price point than something like the Analog Discovery 3.

Thanks!

Hi, I have previously received a USB-2416-4AO from Digilent. Now I am trying to use this to run and collect data from my test rig. The goals are: 1. Energize a solenoid valve to open position through the DI/O port 2. Receive a pressure upper value to de-energize the solenoid valve to closed position holding that pressure 3. Wait for a certain period before energizing the solenoid valve again, and then waiting for a period before repeating the same process again for a certain number of cycles So essentially, I need to automate the process based on a pressure signal, number of time steps and number of cycles to be performed. I also need to automate the counter input to be able to give me event number for the given time step because I am assuming the counter ports of this DAQ would not be able to read a frequency wave directly? Based on this, what software do you recommend? Please keep in mind that this is to be used for a research project at Simon Fraser University, BC, Canada and therefore cost of the product should reflect that. Many thanks, Talha

Hi Arthur, I'm glad I asked — that approach was much easier than rebuilding the block diagram! Thanks. I used those steps to increase both the DLMB and the ILMB values in the block design, reverting them from 8K back up to 32K. (In my diagram, unlike the screenshot in the link, they weren't in the same part of the tree: one was in Network 0 and the other in Network 1. I've no idea if that's important or not, so I presumed it wasn't.) I rebuilt the bitstream and exported the XSA file, and then found and used this guide to update the hardware specification back in Vitis: https://digilent.com/reference/programmable-logic/guides/vitis-update-hardware-specification In Vitis, I could then see in the Explorer that the file at ‘<my_project>_wrapper/hw/<my_project>_wrapper.mmi’ had been updated, and that the ‘AddressSpace’ element there now had an ‘End’ attribute set to 32767, as expected. However, the build still doesn’t work. I’ve tried running a ‘Clean’ on each of the platform, system, and application projects in the Assistant area just in case, but I still get this: 17:00:20 **** Incremental Build of configuration Debug for project microblaze_flash_wrapper_app **** make all Building target: microblaze_flash_wrapper_app.elf Invoking: MicroBlaze gcc linker mb-gcc -Wl,-T -Wl,../src/lscript.ld -L/home/pdw/Documents/Vitis-workspace/microblaze_flash_wrapper/export/microblaze_flash_wrapper/sw/microblaze_flash_wrapper/standalone_microblaze_0/bsplib/lib -mlittle-endian -mcpu=v11.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "microblaze_flash_wrapper_app.elf" ./src/main.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group /home/pdw/Xilinx/Vitis/2022.1/gnu/microblaze/lin/x86_64-oesdk-linux/usr/bin/microblaze-xilinx-elf/microblaze-xilinx-elf-ld.real: microblaze_flash_wrapper_app.elf section `.heap' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' /home/pdw/Xilinx/Vitis/2022.1/gnu/microblaze/lin/x86_64-oesdk-linux/usr/bin/microblaze-xilinx-elf/microblaze-xilinx-elf-ld.real: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 1856 bytes collect2.real: error: ld returned 1 exit status make: *** [makefile:38: microblaze_flash_wrapper_app.elf] Error 1 17:00:20 Build Finished (took 207ms) which as far as I can see, is exactly the same error message as before. Any suggestions of what I might be missing? I'm still at the "read instruction, click button" stage with Vitis, so I'm expecting it's a beginner's mistake somewhere. Also, in case it’s relevant (but definitely not presuming anything here!), I’m happy to upload the Vitis project somewhere if that’ll help: there’s nothing sensitive in this project yet, and it compresses pretty well. Thanks in advance for any clues you might have, Cheers, Paul. P.S. No idea why my previous post was double-posted; is there some way to delete one of them?

A lot of questions, and I just get 2 pictures?? I would have thought that playback would be part of the Digital Pattern Generator tool. The manual states "The Digital Pattern Generator (Patterns) lets you define the output on the digital lines, using standard types or user-defined types. The manual states for the Logic Analyzer tool "The Logic Analyzer allows acquisition and visualization of digital inputs." In any case, my objective is to play back my own custom file I created. So if it is done via the Logic Analyzer, no matter... In the demo tool, I imported my file (junk.txt) into the Logic Analyzer via the screen shown in picture "import". It consists of 2 columns of data - time and value. Based on the screenshot, it appears to recognize these properly. After importing it, I open up the data window to look at the data. Refer to "import3". Isn't the data window supposed to show what was imported? It does not look like what I imported. Why is there a red box with the word "busy"? I am running this in demo mode. Perhaps it is getting confused. Maybe this would work better if I had an actual device? If I click play, I would then expect that the data I imported would play back on DIO24, correct? Can you point me to a tutorial or video of playing back an imported file? junk.zip

I have two pretty good bench supplies, so, I do have that covered. What I am really after is a new scope to sort of replace my old Tek scope. It has 100 MHz bandwidth and four channels. I am spoiled at work with the newer digital scopes and would like those features. From examining the specs, my take on the product offering highest analog bandwidth is 55 MHz. This is probably more than adequate for what I do. Attached are couple of scope shots. (This model scope was Tek's last glass CRT model they produced.) One shows a SPI bus transaction and as you can see, this is a stretch for this instrument. I would be curious to know how the Discovery 3 would do on these wavefomrs.

Hi @attila I manage to fix it by adding time delay between PWS power-on and DIO. Not sure the problem is, but it has to do with power/IO timing. Much appreciation for your help.

Hi, SHA512 is fine! Thank you for the support here -- is there a general timeline for this this being done? When do you guys expect the next beta release for Waveforms to be? Thank you guys, and let me know if i can answer any more questions. @malexander @attila

Hi @Evan Cleary, My understand is that it is possible to do, but you need to change out a couple of DLLs to make it work as per this specific post (and the one chronologically after it): Let me know how it goes. Thanks, JColvin

Hi @Clyde, I don't know what your specific needs are, but other devices, such as the Analog Discovery 3 or the Analog Discovery Pro 2230, have eFuses to limit the total power output (which you can set the value of) on their adjustable -0.5 V to -5 V and +0.5 V to +5 V supplies. Thanks, JColvin

Ok, now I understand. The description leads one to believe there is a more substantial connection, and perhaps an equal to a very light duty bench supply, or at least that is how I have interpreted it. I am just trying to figure out if this is the instrument for me.

Hi @Clyde VIO = Digital Power Supply 2 pins on the DIO connector

Please send me an email, I am an Engineer working with Johnson and Johnson. I would like to continue working with your company, but I really need a form of documentation.

Hello @Ross MacKenzie. No records are available for external requests.

I should mention that I have USB keyboard, USB mouse, and even USB headphone. None of those are recognized by the Horizon Client, but all working when I use my virtual machine Debian.

Thanks attila. I'm using VMWare Horizon Client on which I have a Debian OS. On my VMWare, I have only "USB Unavailable".