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  2. Hi @Phil_D You can use the RangeSet function to select the gain and the RangeGet function to get the calibrated value, full swing. All the Set/Get function in the API behave like this. Normally it is not recommended to go with full swing input signal since clipping can occur. Like when the scale top is 5.561V and the input signal reaches 5.562V dwf.FDwfAnalogInChannelEnableSet(hdwf, c_int(-1), c_bool(True)) dwf.FDwfAnalogInChannelRangeSet(hdwf, c_int(-1), c_double(5.0)) dwf.FDwfAnalogInConfigure(hdwf, c_int(1), c_int(1)) range1 = c_double() range2 = c_double() offset1 = c_double() offset2 = c_double() dwf.FDwfAnalogInChannelRangeGet(hdwf, c_int(0), byref(range1)) dwf.FDwfAnalogInChannelRangeGet(hdwf, c_int(1), byref(range2)) dwf.FDwfAnalogInChannelOffsetGet(hdwf, c_int(0), byref(offset1)) dwf.FDwfAnalogInChannelOffsetGet(hdwf, c_int(1), byref(offset2)) print("Scope 1 Range: "+str(range1.value)+"V Offset: "+str(offset1.value)+"V") print("Scope 2 Range: "+str(range2.value)+"V Offset: "+str(offset2.value)+"V") # on my AD2 the actual ranges are the following: # Scope 1 Range: 5.560701917732086V Offset: -2.4933249474501373e-06V # Scope 2 Range: 5.558373268176409V Offset: 0.00021560932083742462V
  3. Today
  4. I think you'll find the AD2 manual answers your questions very thoroughly. Scroll down into the details of the scope input gain staging, etc. https://reference.digilentinc.com/reference/instrumentation/analog-discovery-2/reference-manual?s[]=schematic&s[]=analog&s[]=discovery&s[]=2
  5. Hello everyone, I am working on zynq FPGA systems and curruntly i start working on Cora z7-07s board but when i add board file in vivado 2015.4 of Cora z7-10 and Cora z7-07s then cora z7-10 is successfully recognize and i can see in boards tab but Cora z7-07s is not appear also i can not find the part
  6. xinx_92

    Arty S7 with Simulink

    Thanks for your Reply! I figured out how to Import my Matlab models in Vivado. My question is now, is there a tutorial somewhere how to find out how to use vivado. To set and configure the Input and Output layout of the Pins for example?
  7. xc6lx45

    I bricked my CMOD-A7

    You might try to take an old USB cable and put an amperemeter into the 5V wire. I suspect you'll observe that current consumption starts around 80 mA (the FTDI chip waking up) then dropping much lower when the FTDI chip shuts down. I've seen this pattern on other designs when there are issues with USB / power supply. Most likely it has nothing to do with Flash. Hypothetically, I could flash a design that draws more current than USB can provide, and would cause the FTDI chip to run out of juice and shut down. Maybe the PROG_DONE LED goes on for such a short time that the eye does not notice. In this case, the paper clip trick should be sufficient to bypass Flash boot once. And as mentioned above, you can access the boot mode pins, e.g. solder a wire to the FPGA end of the resistor.
  8. xc6lx45

    Offline Installer

    I might chime in with an opinion here: This problem will generally become more severe in the future now that Windows 7 is EOL and obviously unsafe: There is a big number of (pre)-Windows 7 based embedded machines etc out there that came with a 6- or 7 digit price tag and must be isolated from the web nowadays. I am personally aware of one large vendor who is totally oblivious to this problem (e.g. trying to stream a welcome video with their driver installation and failing, relying on 256-bit encryption which is not included in Vanilla Windows 7 as found on a recovery partition) and it has cost them dearly. In a trade fair or marketing presentation, everything is new and shiny but dinosaurs walk the factory floors... which is BTW the reason why GPIB needs so heavy cables 🙂
  9. Graham, thanks for the guidance! Hadn't realized the constraint sequence was germane. Ran the wizard yesterday; its suggestions and questions led me not to a new constraint file but (better) to reading more Xilinx documents. 🙂 Will check out the video too. It's been pretty magical to see the RTL schematics recapitulate the drawings in my lab notebook upon which the VHDL was originally based. It's been correspondingly striking to see the synthesized circuits depart from expectations, sometimes in very surprising ways. Those departures have been VERY educational (and eg led to the original post). Much to learn! AA
  10. mattk

    Offline Installer

    i might have to, it is hard to download anything with the internet computers since network security is a max priority. Would you know about the general size of the files?
  11. zygot

    I bricked my CMOD-A7

    Before you start cutting you might consider trying to force JTAG configuration mode. It looks like the mode pins have 1K pulldowns for access.
  12. Hello, I'm using the Analog Discovery 2, and am using the API to basically use it as a high speed digitizer. What signal level would it take to drive the scope channels to full-scale on the ADC? I see that there are different gain options as well, but I also don't know how to control that with the API, if I even can? We'd like to set our max swing at full scale so we can get the best SNR. Thanks, Phil
  13. Hi Allan, I see you've got the right idea about the clock paths, and you've been re-formatting your hdl syntax too, it now looks much more like that recommend by Xilinx. If you are not doing so already, I'd recommend you take a look at the constraints, and note that there is a sequence that they should be in, its like this... Constraints Sequence ## Timing Assertions Section # Primary clocks # Virtual clocks # Generated clocks # Clock Groups # Bus Skew constraints # Input and output delay constraints ## Timing Exceptions Section # False Paths # Max Delay / Min Delay # Multicycle Paths # Case Analysis # Disable Timing ## Physical Constraints Section # located anywhere in the file, preferably before or after the timing constraints # or stored in a separate constraint file I think the Xilinx video on the constraints wizard is worth watching, and the wizard topic help is good. https://www.xilinx.com/video/hardware/using-vivado-timing-constraint-wizard.html Just to add, when possible, I like to keep a circuit in mind when I'm writing HDL, then keep an eye on the RTL schematic to check it's building what is expected. This usually works well, but it can be a little buggy (much better than it was). If the RTL schematic looks strange, check the technology schematic before you try to fix it. This technology schematic is normally a true representation of what you'll get. As an example of this I'll upload a couple of pictures from your design (see the slow clock). Primitives. I'd also recommend getting familiar with the primitives in the device you are using. One advantage is you can use your hdl to infer rather than instantiate what you want, another is you can improve performance. Hope thats helpful, Kind Regards Graham
  14. Greetings! I'm working on a project using the Analog Discovery 2. I observed that the Pattern Generator can be used as a Transmitter and the Logic Analyzer can be used as a Receiver, if used properly. Here's the VB Script that I've been working on: AD2_Time_Testing.rar The VB Script does the following: 1). ASCII data is entered. 2). The algorithm in the code will convert it into binary to be transmitted by the Pattern Generator. 3). The Logic Analyzer will receive the bits in Record Mode. 4). The UART decoder algorithm will convert the bits received back into ASCII character. The result that I'm expecting is this: "U" ---> (Converted into Binary) ---> (Transmitted by the Pattern Generator) --> (Bits received in Record Mode) --->(BIts will be converted back in ASCII) ---> "U" The actual result that I'm getting is this: (DIO#0 (Tx) and DIO#2 (Rx) was used) Data that is to be transmitted: I connected DIO #0 to DIO #2 and a UART controller. Data was sucessfully transmitted and it was received by the UART controller: I also observed the bits returned by the FDwfDigitalInStatusData became like this: I think because of this change the UART Decoder algorithm cannot process it properly. That's why I'm getting this result: The output of DIO0Mesg should be "U" as well. Any advice regarding this? Best regards, Lesiastas AD2_Time_Testing.rar
  15. hamster

    I bricked my CMOD-A7

    The devices identifies correctly so it looks as if the FTDI is OK. The serial port stays up and active, but the JTAG port only hangs around for a few seconds. It looks to me as though the lack of the FPGA to configure correctly is crashing/blocking the USB JTAG interface. Looking at the schematics the JTAG is only connected to the FPGA, and doesn't connect to the QSPI Flash at all, so I can't see why it won't work, unless the JTAG is blocked while the FPGA is configuring, and this is causing the driver to barf and fail. I wonder if I can remove and reprobe the USB device? I've checked at least the 3V3 rail, and it seems OK. I am half thinking of breaking out the microscope and jumpering the FPGA into JTAG boot mode rather than SPI.... Maybe if all else fails I lift the Flash from the board, program it with a good image and then put it back??? Looks very similar to https://forums.xilinx.com/t5/Other-FPGA-Architecture/device-disconnected-when-programming-FPGA/td-p/768702 and https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/Digilent-Adept-USB-device-disconnects-immediately/m-p/310301#M12179
  16. Yesterday
  17. I'm wondering if there's a way to modify the Arty Echo Server example project to utilize BRAM on the FPGA vice the DDR chip on the board? Thanks in advance.
  18. zygot

    Offline Installer

    @mattk My development PCs are sequestered from the internet as well; and have all of the available Digilent tools installed using the executables provided by Digilent's Resource Center. I just downloaded them to an internet connected PC. We're not talking about large files here. The Vivado tools are way too large for physical media and have to be downloaded. Perhaps you need to submit a request to your IT person to vet the tools and have them installed. It doesn't make a lot of sense that users in a closed environment would be allowed to install software on their own in such a setting.
  19. Hi @Jentson, I did a sort of back of the envelope calculation to figure this out. At 3 MS/s, the 32640 buffer will be filled in about 10.77 ms. The OpenScope has a 12-bit resolution per channel, which means we are looking at 391680 bits. To keep the buffer from overflowing you'll need to send all those bits over serial within 10.77 ms. The baud rate necessary to do so comes out to about 2.21 MBaud. The OpenScope runs at 1.25 MBaud with no way to change the baud rate, so you will run into issues. You will be unable to run the data over WiFi as well. There are few factors that play into the limited speed, but we measured a sustained speed of 200 kB/s over WiFi. I am sorry to say but the OpenScope won't cut it for the intended application you have in mind for it. AndrewHolzer
  20. mattk

    Offline Installer

    The computer i need to install Adept 2 on can never touch the internet as it is a lab computer and is never allowed on the network. So i must find a offline installer to install the entire program on the computer via CD/DVD.
  21. malexander

    DMC60c CAN Bus

    @opethmc I think reducing the baud rate should be fairly simple but this will result in an image that's not compatible with First Robotics Competition and it wouldn't be compatible with our configuration utility, which runs on a RoboRio in the FRC environment. Assuming that I can find time to make such an image what baud rate did you have in mind and how many devices were you planning on having on the bus? Thanks, Michael
  22. Hi @ker2x Thank you for posting. That looks like Digital Discovery. https://www.youtube.com/watch?v=vfUhF3BJoBc&t=8m7s
  23. It's kind of cool, there is a crazy project of genius restoring the original apollo guidance computer (AGC), which is 50years old. And i this video i just noticed that they used the analog discovery to test and debug the alarm module. (the famous "houston, we have a problem" (undervoltage on main bus). https://www.youtube.com/watch?v=vfUhF3BJoBc&list=PL-_93BVApb59FWrLZfdlisi_x7-Ut_-w7&index=3
  24. Hello, last week I got in a CoolRunner-II to start messing around with Verilog on a CPLD. Sometime this morning, my 4-digit BCD counter stopped working. The only LED lit up right now is the "USB 3V3" (LD4). Have tried different USB cables and different host USB ports. Even tried a hub to see if the hub recognized a USB device at the far end. All that makes it into the circuit board is power from the USB port. If nothing else, the four 7-segment LED displays should be counting but they are not lit up either. What would a good next step be? Please, no "magic smoke" answers. It's infantile and there is no evidence of anything overheating (or even getting warm). Thanks in advance.
  25. Thanks, @JColvin, I have a few additional questions. The schematic shows IC1 as part N25Q512A836SF40G . I was unable to find this exact part on DigiKey, though there are similar part numbers. Also, the reference manual lists an older and smaller flash part, the N25Q256A. Can you clarify? The part is now populated with the larger and newer part due to sourcing supply and demand? Also, the part number or serial on the IC is: 7JD1 7ZAI5 RW243 with logo ISA . Can you clarify if this is a generic N25Q256 or N25Q512 ? Tim
  26. Hello, I am new using FPGAs, so I assume this question may be easy, but I have been trying several demos and forums and I cannot find the anwer to my problem. I am using an Arty S7 My objetive was to use the XADC wizard to process and analog signal and pass it through the uart to the terminal. I would like to do this using the microblaze. The error I obtain is the following: [DRC UCIO-1] Unconstrained Logical Port: 5 out of 23 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: channel_out_0[4:0]. Which makes sense because, as it can be seen in the image, the output of the XADC wizard is not connected to anything. How could I connect this properly? Thank you very much:)
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