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  1. Past hour
  2. Hello, we are using the analog discovery in out test setup. I prepared several scripts to automate the validation. For the Analog Discovery control we are using the DWFCMD.exe utility application that comes with the WaveForms SDK. The point is that all the scripts that we had perfectly running in my PC has stop working in a new PC that we have prepared for the TESTs. Both PCs have the same sw versions. I've installed all the application in the same way as in my PC. It's curious that the GUI Waveforms works, the only that does not work is the DWFCMD.exe utility in the new PC. There is no error message. Here a sample of th e output: ./DWFCMD.exe connect analogout channel=0 enable=1 start Starting AnalogOut Channel 1 Starting AnalogOut Channel 2 Some extra data (may be relevant): Digilent WaveForms utility application. Version 0.1.1 OS Windows 10 Waveforms: 3.7.5 64-bit Qt5.6.3 Windows 10 Any hint about what might be failing in the command line ? Did this occur to any other in the past? Please let me know what else can I check or if you need some extra information to debug this issue
  3. OK I remember there were some recent posts on the topic I think Digilent has ported some of the code to FPGA using HLS (e.g. search for openCV, HLS).
  4. Today
  5. daeroro

    pmod can period

    Well, I figure out a bug in the example code. In the CAN_Configure function : // Set CAN control mode to configuration CAN_ModifyReg(InstancePtr, CAN_CANCTRL_REG_ADDR, CAN_CAN_CANCTRL_MODE_MASK, CAN_ModeConfiguration ); needs to be change like this: CAN_ModifyReg(InstancePtr, CAN_CANCTRL_REG_ADDR, CAN_CAN_CANCTRL_MODE_MASK, CAN_ModeConfiguration << CAN_CANCTRL_MODE_BIT); So it can enter the configuration mode... After changing the code, CAN communication between Zybo-z7 and MCU works really well. You need to change your git example code.
  6. revathi

    xadc_zynq

    Hi @jpeyron, I would like to do differentiation function on xadc output. Will you give some basic idea or any references for doing the differentiation function over the ADC output Thanking you
  7. I am having this problem with my project under a shared folder on Dropbox. When under OneDrive (no share), no problem. Windows 10 Vivado 2018.2 [IP_Flow 19-3475] Tcl error in ::ipgui_wifi_demo1_mig_7series_0_1::updateAllModelParams procedure for BD Cell 'mig_7series_0'. error renaming "c:/Users/xxxx/Dropbox/yyyy/7.9.2/Ar_WF_WS.srcs/sources_1/bd/wifi_demo1/ip/wifi_demo1_mig_7series_0_1/_tmp/wifi_demo1_mig_7series_0_1" to "c:/Users/xxxx/Dropbox/yyyy/7.9.2/Ar_WF_WS.srcs/sources_1/bd/wifi_demo1/ip/wifi_demo1_mig_7series_0_1/wifi_demo1_mig_7series_0_1": permission denied I need it to work on Dropbox. Please, advise. Thanks
  8. hi @xc6lx45 thaks for the reply.. i have worked on openCv in Raspberry Pi and bananPi... i have done video processing in it... the reason i want to do it on FPGA is the speed... FPGA are faster then pi.. so i just bought zybo z7-10 board played with it.. try to make my self familiar with it.. tried all the demos. familiar myself with vivado and sdk. as well try to install and run petalinux.. all done.. now i dont find a way how to use open cv for the board.. any more help wil be much appreciated
  9. Yesterday
  10. Hi @jpeyron I have used your information - it has some helped me. Thanks!) 1) I have connected .XDC file (to constarints) https://github.com/OrionInnov/uhd-fpga/blob/master/usrp3/top/e300/e310.xdc?_ga=2.195350511.234626281.1558874700-227237821.1553275560 2) i have Created blocks like in youtube example ( and Generate succesful bitstream. Then opened SDK and get problem in downloading code to fpga (clicked PROGRAM FPGA in SDK) - i show image. SDK don't see FPGA ((( (I give rar of my project HLS + SDK https://m.mega.dp.ua/kMWSx) What do you phink about connecting to FPGA? Best regards
  11. @tahoe250, A quick Google search should yield almost all of what you need: how to create the IP, integrate it into your design, adjust addresses, build with it, and use it in practice. Be aware, a lot of Xilinx's AXI IP (as of 2018.3) both has bugs in it and is (rather) slow. Check out this post discussing the bugs in their AXI-lite demo core, or this one showing how you can build (and verify) a core without the bugs. Dan
  12. In one of three attempts i was able to create the 100 MHz clock but then I got critical warnings during validation:
  13. I am using Vivado v2018.3 (64-bit) SW Build: 2405991 on Thu Dec 6 23:36:41 MST 2018 IP Build: 2404404 on Fri Dec 7 01:43:56 MST 2018 My procedure: Create new RTL project with "Zybo-Z7-Master.xdc" Add "vivado-library" as IP repository in project settings Create Block Design Add IP: ZYNQ7 Processing System Run Block Automation Connect Board Component: JB to PmodCAN_v1_0 Run Connection Automation But it is not possible to create the 100 MHz clock...
  14. NITISH KUMAR

    fpga kit

    Sir i am using fpga kit of DIGILENT ATLYS SPARTAN -6, is this can be program by using ISE DESIGN SUIT? Is this fpga has analog to digital pin and digital to analog pin? is this can be used for controlling of power switches like MOSFET ,IGBT?
  15. Thanks @rprr for posting a bug report on Raspberry's GitHub. I also have a Raspberry Pi 3 Model B and it would be great to have WaveForms running on it. There is a suggestion on the FTDI Community forum to try a 3rd-party library called libFTDI, they think it might work. Has anyone tried to compile it and use it with WaveForms? I tried the following, but my Linux knowledge ends here sudo apt-get install cmake libusb-1.0 git clone git://developer.intra2net.com/libftdi cd libftdi cmake . And I got this error: Could NOT find Confuse (missing: CONFUSE_LIBRARY CONFUSE_INCLUDE_DIR) @attila, do you see any chance this could work?
  16. I am looking for tutorial that guides through the entire flow. Meaning, create a vivado project then create a linux image based on that hardware design. I am trying to figure how to write an application that would access my custom HDL module through Linux. I have already verified that my custom HDL module works through the AXI lite bus interface. I created a bare metal application to test my custom HDL module and everything works as I expect it. So, the next step would be doing the same through a Linux application. Hope that makes sense. Also, I am currently working with vivado within Windows 10 would it make more sense to install vivado on a Linux Box? I have gone through this tutorial: https://github.com/Digilent/Petalinux-Zybo-Z7-20/blob/master/README.md?_ga=2.65706535.861548781.1558477480-254828324.1551742247 Basically, installed Petalinux on VM linux box. Another thing, I had a really hard time installing Petalinux on Ubuntu 18.04.2. I gave up and went to 16.04.4 then seems to work just fine. Not sure if I understand that one. Any guidance would be tremendously appreciated. P.S I am currently using Zybo-Z7 20 board
  17. Xilinx had a thread a few years ago that discussed this. They describe how you can get by without a level shifter. There is also an old Digilent forum thread that discusses a similar project using a Basys3.
  18. Last week
  19. According to the HCSR04 datasheet, it requires 5v for Vcc. The zybo reference manual shows, in section 16, pmods only have 3.3 v on pins 6 and 12. You would need a level shifter and a 5v supply powering the HCSR04.
  20. I have broken one of the audio jack sockets (AJ1) on my myProto board. Can anyone point me in the direction of a supplier where I could purchase a replacement jack socket? Thanks Phil
  21. Hi everyone! I encountered problem when connecting ultrasonic sensor HCSR04 with pmod pin JA. Is there any reference for using that sensor with zybo? thank you
  22. Hi all - I've searched through old threads and see some posts about this issue, but nothing in them has worked for me. I have a BASYS3 board, and I can't get Vivado to see it. I've tried on both Ubuntu and Windows 10. I'm trying to follow the simple LED tutorial on the Digilent web site. Here's what I've tried so far: - Made sure board is jumpered for JTAG and powered up - Made sure drivers were installed (manually went in and ran the batch files in cable_drivers/nt64 and ensured that both the pcusb and Digilent drivers successfully installed) and rebooted - Made sure the Basys3 board was copied over into board_files, shows up in the UI, and is the selected hardware for the project When I bring up hardware manager with the board plugged in and run auto connect, all I see is the local host server node with no devices under it. Running refresh_hw_server tells me no hardware targets are connected to the machine. Anyone have other ideas? Thanks! EDIT: Solved. Helps to use a USB cable that isn't power-only.
  23. you might have a look at the HLS (high level synthesis) toolkit. Pay attention to tool license issues / cost.
  24. I have used openCl only on GPUs but the first search turned up a link with this: >> Specifically, we use Intel FPGA SDK for OpenCL that allows modern Intel FPGAs to be programmed as an accelerator, similar to GPUs I suspect this architecture may not mix too well with network data processing: The architectural paradigm on GPUs is "one control path, many data paths" but I think you will need many parallel, independent control paths. GPUs win by massive parallelism / memory bandwidth via bitwidth. The clock speed is fairly low (=> higher end-to-end latency). Just like on FPGAs. You may be able to find a simple example on the web looking for the following functions: clCreateProgramWithSource clBuildProgram clCreateKernel clSetKernelArg. In principle, a complete example can fit into one screen length but some "simple" things like take the maximum of a vector (reduction operations) turn out to be not simple at all... If anybody has experience with openCl specifically on FPGAs, please feel free to correct me...
  25. Hi Everyone, I am a pretty seasoned C++ programmer dealing with low level things but I am brand new to FPGA topic. I have read some articles, watched a dozen or two videos and looked into some boards and I would like to start my first project but dont know where to start. I have a few questions: 1. Do i need to learn Verilog/VHDL if i plan on using openCL? 2. Do all boards "support" openCL? 3. Do i need to actually buy a board to start working on my project or i can just use a Software Emulator for one? If i can use an Emulator, where do i get it? 4. Could you suggest any openCL starting guides and tutorials that are easy to understand for someone who doesn't know Verilog/VHDL or FPGA in general? My project goal is to have a "smart" network interface that would pre-process data arriving on Ethernet and store it on host machine RAM directly, so that my C++ program running on CPU can use that data. Thank you!
  26. >> new to fpga and zybo >> i want to use open cv but i dont know where to start from Just thinking aloud: Independently of making hardware work, it might be a good idea to forget everything about hardware and video. Spend some time with openCv and offline bitmap examples on a standard Linux machine, say a virtual Linux box or a Raspberry Pi. Can speak only for myself, but I rather fight my dragons one at a time, not all at once
  27. Thank you for your timely response . Now, I want to measure DC voltage.what if I feed in a voltage greater Than 1 volts? Another question: what is the purpose of VCC and GND in XADC pmod(the last 4 pins)? Do their power up the ADC? Thanks.
  28. So once I've logged a file to an SD card, how do I get hold of the data? I can download the file to my computer but I can't read it as its in some unknown binary format and I can't export it to something like and ascii text or .csv file. Am I missing something here? or have I got a logger that can capture data but the data can't be displayed, viewed or otherwise accessed?
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