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  2. Hi @JeffKlaas See page 114 of the SDK manual and the AnalogIO_DigitalDiscovery.py example. # set digital voltage between 1.2 and 3.3V dwf.FDwfAnalogIOChannelNodeSet(hdwf, c_int(0), c_int(0), c_double(1.8))
  3. Hi @Mgilbert, I sent you a PM about this issue. best regards, Jon
  4. Hi @Zhanneta, I have moved your thread to a sub-section where more experienced embedded linux engineers look. best regards, Jon
  5. Hello, I am trying to boot up linux on Cora Z707. I am using the base projects for Vivado (https://github.com/Digilent/Cora-Z7-07S-base-linux/) and petalinux (https://github.com/Digilent/Petalinux-Cora-Z7-07S/archive/v2017.4-1.zip) provided by Digilent. I followed the following steps: 0. Generate project and CD into the new project directory (petalinux-create -t project -s <path to .bsp file>) 1. Format microSD card to FAT filesystem partition (1 GB FAT32, 31 GB EXT4) 2. Copy _pre-built/linux/images/BOOT.BIN_ and _pre-built/linux/images/image.ub_ to the first partition of your SD card 3. Create a new file on the microSD card called uEnv.txt. Add the following line to the file, replacing the MAC address as found on the board's sticker, then save and close it: ethaddr=XX:XX:XX:XX:XX:XX 4. Eject the SD card from your computer and insert it into the Cora Z7 5. Short the MODE jumper (JP2) 6. Attach a power source and select it with JP3 (note that using USB for power may not provide sufficient current) 7. If not already done to provide power, attach a microUSB cable between the computer and the Cora Z7 8. Open a terminal program (Tera Term) and connect to the Cora Z7 with 115200/8/N/1 settings (and no Hardware flow control) 9. Press the SRST button to restart the Cora Z7. You should see the boot process at the terminal and eventually a root prompt. I got to step 9 and I am able to see Cora Z7 as one of my serial ports, but I don't see the boot process. Later I was able to get an SDK application running on Cora Z7 and I was able to see that over terminal with 921600 baudrate. What do you think is the issue with the terminal and boot process? Why am I not able to see it and log in into the system? Do you have any suggestions for tackling this issue? Thank you in advance for your help! Kindest regards, Zhanneta
  6. I'm having the same problem as skakon . i accidentally erased EEPROM attached to the FT2232 device.
  7. Thank you @JColvin, I'm glad you reached the same conclusions that I did. I can indeed confirm that the memory seems to work correctly at 1.35V, but the datasheet for the DDR chip is certainly ambiguous. Charlie
  8. jpeyron

    Pmod wifi

    Hi @harika, Unfortunately, we do not have the bandwidth to make a YouTube video for the Zedboard and the Pmod WIFI. On your other thread here I have posted a verified working Zedboard/Pmod WIFI project for Vivado 2017.4. that should only need you to alter the HTTPServerConfig.h with your router login and password. best regards, Jon
  9. Using the Waveforms GUI, we can set the SPI logic driver levels using the Supplies tab. How do we do the same thing in a Python script? All of the examples generate 3.3V SPI logic levels. I need to get to 1.8V logic levels.
  10. jpeyron

    pmod wifi

    Hi @harika, Here is a complete and verified Zedboard WIFI project done in Vivado 2017.4. I would suggest to download Vivado 2017.4. You will need to alter the login and password in the HTTPServerConfig.h for it to work with your router. best regards, Jon
  11. Hi @catphish, I took a look at the possible build list for the Arty S7 and it seems that the Piecemaker board is a build option for the two versions of the Arty S7, which I was surprised to learn. The datasheet that I am looking at the for the Piecemaker DDR chip (link to datasheet) seems to say in some places that it will work with either voltage (such as in the description on page 4 and page 11) but the list of the parts list on page 5 seems to say only one particular part works on 1.35V. However, we have one of these Arty S7 boards with that same PMF511816EBR-KADN chip and we verified that it works correctly and measured the capacitors that it runs at 1.35V. I have reached out to our design engineer for this board to confirm this though. Thank you, JColvin
  12. Thanks @OvidiuD, I'll take one step after another and the forums are quite a good source of knowledge. So far, I plan to start with very basic schemes in order to understand how Vivado works. Then I will work on communicating with the Axoloti through SPI. Best regards
  13. Thanks @JColvin! I put some of the original numbers into a spreadsheet here, re-ordering the pins from alphabetical to numerical. Some questions: * Each pair has up to +/- 1.2mm delta, I assume this is within spec (which spec, heh) or accounted for by extra trace length in the FGPA? * Looking at these totals, I assume that each differential pair is only length matched as a pair and not for all pairs in the high speed PMOD port? e.g. if I have two differential data lines clocked to my differential clock, I’ll have to add some serpentine routing to the shortest pairs. Thanks for your awesome support(ing) an older board!
  14. jpeyron

    pmod wifi

    Hi @harika, The board connects to the router through the Pmod WIFI. That is why you need the login and password for the router added in the HTTPServerConfig.h. The mode jumper would be set to SD if you were booting your project from the SD card reader. In this case the project is just using the SD card reader and not booting from the SD card reader. You should have the Mode Jumper set to JTAG. best regards, Jon
  15. Hi @RedMercury, I learned that those distances do not include the leg distances, so they just go to the through hole. Based on the datasheet for the female Pmod header you should be able to find out those details if you want to though. Thanks, JColvin
  16. true but it's a five-line job e.g. in Verilog reg[15:0] counter = 0; reg [15:0] impulse = 0; always @(posedge clk) begin counter <= counter + 1; impulse <= (counter == 0) ? 16'h7FFF : 0; end plus the protocol interface (e.g. trigger a new valid sample if counter[7:0] == 0)
  17. Hey, I just got my AD2 and it's not outputting any voltage.  It says it's connected just isn't outputting any voltage (I checked with a multimeter). Any idea why it isn't working?

    Thanks,

    Anna

  18. Hi @TomF, Are you using the Digilent boards files? When doing block automation in vivado I would suggest using 32KB for local and 16 KB for cache. Please attach a screen shot of your block design. What frequency are you giving the ext_spi_clk on the QSPI Flash IP Core? best regards, Jon
  19. Hi @Abdul Qayyum, I would suggest using an enable signal in your UART FSM if you haven't already. For initial implementation i would suggest tying the enable to a button or switch. Also please attach your top/wrapper file as well. best regards, Jon
  20. hello, I'm trying to port a baremetal design, in which I have a simple HLS IP that performs vector additions, that triggers an interrupt when it finishes its computation. After the bitstream generation I exported the hdf and I generated the Petalinux project based on it, in which I specified "generic-uio" in the compatible field as follows: amba_pl: amba_pl { #address-cells = ; #size-cells = ; compatible = "simple-bus"; ranges ; &irq_gen_0: irq_gen@43c00000 { clock-names = "ap_clk"; clocks = ; compatible = "generic-uio"; interrupt-names = "interrupt"; interrupt-parent = ; interrupts = ; reg = ; xlnx,s-axi-axilites-addr-width = ; xlnx,s-axi-axilites-data-width = ; }; }; Then I created an appropriate bootargs configuration and placed inside the uEnv.txt file: bootargs=console=ttyPS0,115200 earlyprintk uio_pdrv_genirq.of_id=generic-uio and I enabled the following modules: CONFIG_UIO=y CONFIG_UIO_PDRV_GENIRQ=M CONFIG_UIO_DMEM_GENIRQ=M then I create a simple application that runs the initialization drivers of the IP and wait for interrupts: int main() { int a ; int b ; for(int i = 0; i < N; i) { a = i; b = i; } XIrq_gen HLSdevice; XIrq_gen_Initialize(&HLSdevice, "irq_gen"); XIrq_gen_Write_a_Words(&HLSdevice, 0, a, N); XIrq_gen_Write_b_Words(&HLSdevice, 0, b, N); int uioFd = open(UIO_DEVICE, O_RDWR); if( uioFd < 0) { fprintf(stderr, "Cannot open %s: %s ", UIO_DEVICE, strerror(errno)); return -1; } volatile uint32_t* counters = mmap(NULL, MMAP_SIZE, PROT_READ, MAP_SHARED, uioFd, 0); if(counters == MAP_FAILED) { fprintf(stderr, "Cannot mmap: %s ", strerror(errno)); close(uioFd); return -1; } uint32_t intInfo; ssize_t readSize; for(int i = 0; i < 10; i) { XIrq_gen_Start(&HLSdevice); printf("XIrq_gen_Start() "); intInfo = 1; if(write(uioFd, &intInfo, sizeof(intInfo)) < 0) { fprintf(stderr, "Cannot acknowledge uio device interrupt: %s ", strerror(errno)); break; } printf("write() "); // Wait for interrupt readSize = read(uioFd, &intInfo, sizeof(intInfo)); if(readSize < 0) { fprintf(stderr, "Cannot wait for uio device interrupt: %s ", strerror(errno)); break; } // Display counter value printf("We got %lu interrupts, counter value: 0xx ", intInfo, counters ); } XIrq_gen_Release(&HLSdevice); return 0; } The program blocks on the read call and does not receive any interrupts. Under /proc/interrupts I can see my HLS IP, but the interrupt counter is still zero: root@InterruptLinux:~# cat /proc/interrupts CPU0 CPU1 16: 1 0 GIC-0 27 Edge gt 17: 0 0 GIC-0 43 Level ttc_clockevent 18: 2998 **** GIC-0 29 Edge twd 19: 0 0 GIC-0 37 Level arm-pmu 20: 0 0 GIC-0 38 Level arm-pmu 21: 43 0 GIC-0 39 Level f8007100.adc 24: 0 0 GIC-0 35 Level f800c000.ocmc 25: 726 0 GIC-0 82 Level xuartps 26: 11 0 GIC-0 51 Level e000d000.spi 27: 534 0 GIC-0 54 Level eth0 28: 248 0 GIC-0 56 Level mmc0 29: 0 0 GIC-0 45 Level f8003000.dmac 30: 0 0 GIC-0 46 Level f8003000.dmac 31: 0 0 GIC-0 47 Level f8003000.dmac 32: 0 0 GIC-0 48 Level f8003000.dmac 33: 0 0 GIC-0 49 Level f8003000.dmac 34: 0 0 GIC-0 72 Level f8003000.dmac 35: 0 0 GIC-0 73 Level f8003000.dmac 36: 0 0 GIC-0 74 Level f8003000.dmac 37: 0 0 GIC-0 75 Level f8003000.dmac 38: 0 0 GIC-0 40 Level f8007000.devcfg 45: 0 0 GIC-0 41 Edge f8005000.watchdog 46: 0 0 GIC-0 61 Level irq_gen IPI1: 0 0 Timer broadcast interrupts IPI2: 844 1294 Rescheduling interrupts IPI3: 1 2 Function call interrupts IPI4: 0 0 CPU stop interrupts IPI5: 0 0 IRQ work interrupts IPI6: 0 0 completion interrupts Err: 0 could you please give me some hints? thanks
  21. Hi @Remirod26, We do not have a suggestion for a company that would repair the Arty A7. I sent you a PM about the potential next step. best regards, Jon
  22. Hi @hkhantang, I sent you a PM about this issue. best regards, Jon
  23. @Ahmed Alfadhel, I blogged about how to do this for some of my own filters when using Verilator. You can read that post here if it helps, Dan
  24. Hi Attila. Your example works perfectly. I have done some modifications to get channel 1,2 in within the loop. It works fine but I have one question. In the line in your code dwf.FDwfAnalogInChannelRangeSet(hdwf, c_int(0), c_double(10)) Shouldn't I set it for the channel 2, If I wish to read both channels ?? like this dwf.FDwfAnalogInChannelRangeSet(hdwf, c_int(1), c_double(10)). It seems to work anyway. He's your modified code. """ DWF Python Example Author: Digilent, Inc. Revision: 2018-07-19 Requires: Python 2.7, 3 Description: Generates AM modulated signal on AWG1 channel Scope performs scan shift acquisition and logs DC and AC/DC-RMS values """ from ctypes import * import math import time import matplotlib.pyplot as plt import sys if sys.platform.startswith("win"): dwf = cdll.dwf elif sys.platform.startswith("darwin"): dwf = cdll.LoadLibrary("/Library/Frameworks/dwf.framework/dwf") else: dwf = cdll.LoadLibrary("libdwf.so") hdwf = c_int() sts = c_byte() secLog = 0.5 # logging rate in seconds nSamples = 8000 rgdSamples = (c_double*nSamples)() cValid = c_int(0) version = create_string_buffer(16) dwf.FDwfGetVersion(version) print("DWF Version: "+str(version.value)) print("Opening first device") dwf.FDwfDeviceOpen(c_int(-1), byref(hdwf)) if hdwf.value == 0: szerr = create_string_buffer(512) dwf.FDwfGetLastErrorMsg(szerr) print(str(szerr.value)) print("failed to open device") quit() #set up acquisition for channel 1 dwf.FDwfAnalogInChannelEnableSet(hdwf, c_int(0), c_bool(True)) dwf.FDwfAnalogInChannelRangeSet(hdwf, c_int(0), c_double(10)) dwf.FDwfAnalogInAcquisitionModeSet(hdwf, c_int(1)) #acqmodeScanShift dwf.FDwfAnalogInFrequencySet(hdwf, c_double(nSamples/secLog)) dwf.FDwfAnalogInBufferSizeSet(hdwf, c_int(nSamples)) #wait at least 2 seconds for the offset to stabilize time.sleep(2) #begin acquisition dwf.FDwfAnalogInConfigure(hdwf, c_int(0), c_int(1)) # used for skipping the first sample first = True print("Press Ctrl+C to stop") try: while True: dwf.FDwfAnalogInStatus(hdwf, c_int(1), byref(sts)) dwf.FDwfAnalogInStatusSamplesValid(hdwf, byref(cValid)) # loop through both channels 0,1 for channel in range(2): # channel in loop dwf.FDwfAnalogInStatusData(hdwf, c_int(channel), byref(rgdSamples), cValid) # get channel 1 or 2 data dc = 0 for i in range(nSamples): dc += rgdSamples[i] dc /= nSamples dcrms = 0 acrms = 0 for i in range(nSamples): dcrms += rgdSamples[i] ** 2 acrms += (rgdSamples[i]-dc) ** 2 dcrms /= nSamples dcrms = math.sqrt(dcrms) acrms /= nSamples acrms = math.sqrt(acrms) if not first: print(f"Channel {channel+1} = DC:{dc:.3f}V DCRMS:{dcrms:.3f}V ACRMS:{acrms:.3f}V") time.sleep(secLog) first = False except KeyboardInterrupt: pass dwf.FDwfAnalogOutConfigure(hdwf, c_int(0), c_bool(False)) dwf.FDwfDeviceCloseAll() Thanks for the code example..
  25. Hi , I am using a signal of a frequency of 16 kHz sinewave, and the sampling frequency (Fs) is 48 kHz in my design, and I want to test it with FIR filter compiler 7.2. I built simple design (first attached picture), consists form a DDS compiler and FIR compiler. Then I imported the FIR coeffiecents from Tfilter tool. However, the FIR filter was passing even the frequncies in the stopband, as illustrated in this discussion thread. I looked through UG073, and I found figure 5.1 (second attached picture) shows the sampling frequcies lower than 0.5 MHz is processed by Sequnctial FIR filter architechure. While the FIR compiler options are only providing Parallel FIR filter architecure (Systolic Multiply Accumulate) as shown in the third attached picture. Is there any way to change the filter architecture in FIR compiler 7.2 ? If only this architechture (Systolic) is available, what I can do to stop the frequencies in the stopband from passing the FIR filter? Thanks.
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