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  3. Hi @Tim S., I apologize for the delay. I believe these clock registers can be found in the implemented design. I don't know what your application specifically is, but if you are looking to adjust AXI timings on the IO pins on the Arty, you probably do not need to worry too much as current limiting series resistors are implemented on most of the IO lines, limiting the effective bandwidth through those pins. Thanks, JColvin
  4. Hi @chaitusvk, Was this successfully resolved in your other thread here? Thanks, JColvin
  5. I added some colormap animations. The buttons cycle between them. No mushrooms were harmed in the making of this movie.
  6. Hi attila, Thanks for your help. I got below error msg by executing the cmd above. Please help take a look. ========================================================================================================== % python /Applications/WaveForms.app/Contents/Resources/SDK/samples/py/Device_Info.py dyld: warning, LC_RPATH @executable_path/../Frameworks in /Applications/WaveForms.app/Contents/Frameworks/dwf.framework/dwf being ignored in restricted program because of @executable_path (Codesign main executable with Library Validation to allow @ paths) firmware path not found jtscInit 0x3F5 Reinstall Digilent Adept Runtime DWF Version: 3.12.2 Number of Devices: 0 ==========================================================================================================
  7. Hi @Michal Hucik, Later versions of Vivado will not readily work as the MII to RMII IP core is no longer included with Vivado and as per this Xilinx forum thread, there is no recommended replacement available, so we don't currently have any recommendations for this material later versions of Vivado with non-Zynq chips. I was able to confirm that both Vivado and SDK work with this material on the 2017.4 versions though. Let me know if you have any questions about this. Thanks, JColvin
  8. zygot

    DSRC transceiver for FPGA

    There are two general approaches to dealing with resolving complicated problems. One is to work out the easy, trivial, straight-forward stuff first and worry about the rest later. I've found that facing the hardest, scariest stuff first is always a better approach. Better to find out the bad news as early as possible... for a number of reasons. I wouldn't want to fund a start-up that did things the first way. Find something that provide the DSRC functionality and potentially workable as a system component and perhaps we'll have something specific, and more productive, to discuss.
  9. vinivj

    DSRC transceiver for FPGA

    Sure... Hoping to find one soon...
  10. zygot

    DSRC transceiver for FPGA

    The you understand how devilish the details can get. Decoding stereo FM from an SDR with readily available software tools is one thing. Decoding something involving complex FEC, equalization, and other proprietary functions is quite another. Stick with finding a working DSRC platform that you might have a shot at using within a reasonable time frame.
  11. vinivj

    DSRC transceiver for FPGA

    @zygot Thank you for your explanation. I understand the complexity behind SDR working. This is true. Will work on it as per your suggestion.
  12. @attila How can i achieve bode as the AD cannot take the negative voltage. although i did use offset and level shifted the disturbances through waveform generator. but i cannot do next.
  13. zygot

    DSRC transceiver for FPGA

    There certainly are SDR modems available that operate in that range. But, operating range is not everything. There's the data bandwidth consideration. There's the SDR interface ( the Zybo does have a USB 2.0 OTG port but are you prepared to write your own driver?). There are particular DSRC protocol and modulation/demodulation specifics... etc, etc. Usually, you have to pay a lot of money to join an association to get the specifications and standards to develop you own application for such things. I don't think that you appreciate the complexities of how typical SDRs work. I appreciate the thought that you've put into this but it's all moot if you can't find a DSRC modem with a downstream USB interface or Ethernet interface. It's very unlikely that you would be able to use a free PMOD ( 8 single ended < 10 Mhz 3.3V IOs ) to make a custom interface to anything that I've seen related to what's available. Admittedly, I haven't tried too hard. Again, committing to a platform architecture that's half thought out, and missing a key element, is a dangerous way to live. But this is just my personal perspective. Who knows perhaps amazing+luck is around the corner.
  14. vinivj

    DSRC transceiver for FPGA

    Will there be RF modems operating at 5.8 to 5.9 GHz frequency? Even that would suit my objective, if available (for FPGA). Available PMODs actually made me to choose Zybo board as my objective includes interfacing GPS and a display (in addition to DSRC module). I am not sure about designing a PMOD on my own...having time constraints. As I mentioned above, I have to interface other modules (which are available as PMODs) and hence I am going with Zybo. If I get suggestion on another low cost FPGA that would suit DSRC module interface, I would be glad to choose that one too. I have put up this question here in this forum to get an answer exactly to this question. I am not sure about that really. I could afford if I get a better option to proceed. Except for the DSRC modem interface, I find Zybo a better option to accomplish my objective. Just wondering if RF transceiver could serve the purpose?
  15. Markus, Another outstanding tutorial with plenty of goodies for those who want to learn stuff. Tip of the bowler.... There just aren't that many commercial quality fractal generators available . Actually, this was a delight on so many levels. Almost brought tears to my eyes ( not of joy ) remembering past tousles with Forth... Your projects are like watching a magician's act. While the direct effect might not be totally mesmerizing watching the manipulations behind the scene certainly are. It's rare to find a published project where the source code is a star and so enjoyable; same with getting a glimpse of the technical obsessions of smart people like those represented in this release. Now, if only there was a testbench.v to match the provided simulation and verilator code and make it complete... 😆
  16. Hi @Ramunas, You have a private message. Regards, Bianca
  17. Hello, The maximum sample rate for the chip on ZmodADC1410 (AD9648) is 105 MSPS and the IP is designed for 100MSPS. This is the only available reference design. What sample rates do you need?
  18. This is 6,144 RGB LEDs being controlled by an FPGA. This gives the display 12-bit color. I started with a single 32 x 32 RGB LED panel, to check on how it works. The LED panels used for this project have built-in drivers from the LED video wall manufacturers. To control color, the entire panel must be updated at high speed.
  19. Although volunteering can receive no compensation, he/she can be eligible for reasonable benefits or a nominal fee to perform.
  20. Hello there I am working on an image processing project that uses a camera with cameralink interface and FMC CameraLink board (AD01249) to interface it with FPGA (ZedBoard). I had a difficulties when trying to connect the FMC board to the FPGA to stream the video recorded by the camera on the FPGA to do image processing on it. I have all the components listed above but I don't know how to program the FPGA to read the data stream coming from the camera through the FMC board. Can you help me with sources that explain how to do it in details or some documentation on the FMC connectors and how to read its content on a FPGA? I need that sort of information to start my work. I am new to the FPGA design and I search the internet but I couldn't find anything useful. Thank you in advance.
  21. Hi Atilla We checked all most all power outputs as per each section in schematics but when we enable the VP+, VP- , VREF on Diligent Waveform Software, values are random. The DMM Values dont show anything 0V on all these points on BB. We could not co-relate VP to which Legend on the schematics and so on?? Hope my query is clear why we requested layout. Is it possible u can link with Diligent Design team to get the pdf as components are almost invisible to trouble shoot on the PCB??
  22. I have a task, as a part of my master thesis, to generate a sine wave using Pmod DA4. I found the solution, however, to generate a sine wave using look-up table. The online LUT generators are for fixed amplitude i.e., sine wave is generated with a dc offset of 1.25V and an amplitude of 1.25Vp-p (considering DA4 with a reference of 1.25V and an internal gain of 2). However, I want to generate a sine wave with different amplitude and frequency (changing frequency is possible with the help of timers, so that is not a problem). Therefore, I want to know if it is really possible to generate a different amplitude sine wave? Is there any algorithm for doing that? My requirements are, 1. Sine wave with the frequency of around 10Hz (which is possible). 2. With 500mV of dc offset and around 50mVp-p of amplitude. I am using zeboard for the development.
  23. Hi @S.Kagawa The erc 2 indicates timeout on waiting for the device to reply. const ERC ercTransferCancelled = 2; // The transfer was cancelled or timeout occurred
  24. Hi @krishnaprasad The BB### are the breadboards. You can identify them by function. The square throughhole is pin 1. I don't have layout. You have the full schematic and labels for all the components on the board (except BB). This is what we used when we validated, troubleshooted the prototypes of this board.
  25. Hi @Leon I'm not familiar with this 3rd party dwf.py package... Try running the examples from the WF SDK: $ python /Applications/WaveForms.app/Contents/Resources/SDK/samples/py/Device_Info.py
  26. Hi @JColvin, As per your instructions in my other post I was able to run the Embedded Vision demo successfully. Can you please suggest me how can I add another filter to this demo project? Thanks
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