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  1. Today
  2. Hi,guys! I'm currently working on how to send character"hello" to FPGA and then transmit "hello" back to my PC. But it seems I only can send some characters to my board and cannot receive the chracters back to PC. I wonder how to build my code in python to get the characters back to my PC. The attachment is my code(PYTHON) and result of runing. import serial ser = serial.Serial("com9",9600,timeout=0.25) print(ser.name) print(ser.port) #ser.open() c=input("hello") b=ser.isOpen() s=ser.read(10) ser.write(c.encode()) print(s) print(b) ser.close() Thanks, Dehao
  3. Good day, I am currently working on a system which requires ethernet control on an FPGA. To this extent I have successfully managed to implement the echo server as per Xilinx`s tutorial. However, I now require to transmit data from my laptop to the FPGA. I am unsure of how to amend this project in its current state to receive data from an external program (such as matlab) and from where to verify the data I have received is correct. Could anyone kindly provide some insight? Regards
  4. Can i get a UCF fle fore this kit and is there a specia ucf file for pmod or ?? no there is only one file in general
  5. alrekaby68

    Audio streaming

    I am grateful to you Vicentiu, I am currently trying to implement the projects you have proposed.
  6. I can understand that digilent has compiled adept and waveform for what i believe others mentioned raspberry pi 4 OS. Is this correct? Is it possible to get the repositories for tinkerboard to also have working copy of adept and waveforms? If so what would i need to do to hasten this type of event? I am guessing the code is propitiatory and it is in the best interest of digilent inc to have it software available on as many platforms as possible so long as it excludes the loss of intellectual property of digilent inc.. If i contact sales force of digilent or digilent's legal team to sign a waver would this help or.. is it not worth the trouble?
  7. Thank you very much for the assistance! I was able to make the necessary corrections and my project is running smoothly now. I also found some other errors in the logic of my code, which I have corrected as well.
  8. Hello, I am having a similar problem. Can either @Staff or @rvmoreira share how to solve this issue? I am currently running WIndows10 macbook pro. Thanks, Beqo06
  9. Hello, I have an Analog Discovery Studio and when I fire up Waveforms I cannot detect it (no device found). This is my setup: MacBook Pro 2017 MacOS 10.14.16 Waveforms 3.12.1 I followed the waveforms installation found at: https://reference.digilentinc.com/reference/instrumentation/analog-discovery-studio/[[getting-started-guide]] The device appears listed in the USB section info as a Digilent USB Device so it is recognized by the OS. Tried restarting, plugging, unplugging, re-installing waveforms.. In the past I had the EE Board up and running with the same setup. Any debugging bone you can throw at me? Regards, Dario.
  10. Yesterday
  11. Hello, While trying to compile (a modified version of) the 18.2 Zybo PCAM 5 demo inside the SDK I got the following error: no matches converting function 'MyCallback' to type 'XIicPs_IntrHandler {aka void (*)(void*, long unsigned int)}' The error pointed to the following line of code in a file named PS_IIC.h : XIicPs_SetStatusHandler (&drv_inst_, &stat_handler_, &MyCallback<void(int)>); Please explain this error. Notes: 1. The Vivado project compiled correctly and the hardware was exported successfully to the SDK. 2. The PS_IIC.h file and a snapshot of the error message are attached. PS_IIC.h
  12. I am not sure you understand my question. I am not talking about the connector that plugs into the PMOD, but the outputs analog connector on the Pmod DA4, that outputs the 8 analog signals to the outside world since I am designing a board to plug into this connector. The schematics shows a 1 x 12 connectors yet the picture of the board shows a 2 x 6. This is all about the mechanical layout of the board and how the connectors was pinned out when the board was layed out. I attached with the two different pinouts. You can see that only pins 1 and 12 are in the same physical location on these two connector pin out schemes. If I used the pin out for the one on the right and it was layed out to the one on the left, I would only connect 2 pins correctly. I have seen both used in industry, but never both being used in the same system, people usually choose one or the other.
  13. Seen the problem. You need to define both o1[0] and o1[1] in your constraints, as o1 is a vector of two signals. At the moment you are trying to attach both signals to the same pin, hence the error. Ditto for o2, o3 and o4.
  14. hamster

    Dividing in Verilog.

    If you are dividing by a constant to can multiply by the inverse. If you only have a small number of different divisors you could consider a lookup table of inverses. Otherwise you need to implement a binary division algorithm yourself, to meet your throughput and latency needs. Division by arbitrary numbers is quite expensive - best avoided if at all possible.
  15. skylape

    Dividing in Verilog.

    Hello guys, I have a question regarding dividing operation in FPGA(Verilog). Given that I cant use "/" operator, what are the method to divide when the two operands are 16 bit register and when one is 16 bit register and one is a constant? Also is there like a quotient and remainder register like those in AVR? Thank you.
  16. New Digital Discovery user. I did not purchase this device for its excellent documentation or thorough applications examples (which are not so great), but because it can capture SPI at 800MHz with the special adapter. I understand that the Digital Discovery will stream the captured data to memory and I can save it to disk. I'm debugging a difficult SPI issue, and need to see as much detail as possible (hence the 800MHz). Out test code captures some 30,000 rows of 14 consecutive 14-bit reads at an SPI clock speed of 27.5 MHz. This is a whole lot of data. We need to see the protocol capture results and compare it with what our embedded system is reporting. We read a very slow, clean R/C ramp (falling), gather all the data, and create a statistical plot which tells us how many "hits" we get on a certain bin value. Here's a snip: In this example, and despite the fact that our input ramp is changing in a very linear fashion (and therefore we should see equal distribution), decimal 4083 (ending in 100011) has far fewer hits than those adjacent. Each column (in the green) is a single SPI read of our ADC. We do 14 through DMA (very fast), and then repeat without much delay. I thought Digital Discovery would (a) trigger on the falling chip select, and (b) keep recording the data stream (ignoring subsequent chip select cycles). It doesn't. Instead, it captures the first 14 samples and no more data after that. Hopefully it's possible to trigger on CS (going low) and just keep sampling until I press stop. (Ideally if there's a timeout value allowing us to stop once CS stays high for a certain duration, that would be ideal). Finally, I have no idea how to save my data to a file and in a certain format. My setup: Please help this new user. I suspect it's simple, but the online docs are not very revealing, and experimentation isn't getting me far. Thanks!
  17. Never mind - I tried a third USB cable and everything suddenly works fine. I think I read somewhere that the Cmod A7 modules are a bit sensitive on the USB interface, and I guess the S7 is cut from a similar cloth. Glad it's working now 😄
  18. I have just received my new Cmod S7 module. Plugging it in to a USB3.0 port on my PC (Windows 7), it powers up and runs the out-of-box demo (lighting up the various LEDs in sequence). However, I notice that Windows doesn't detect any USB device being connected. If I remember correctly, these FTDI chips are usually auto-detected in Windows. However, I don't get any notification, nothing appears in Device Manager, and a terminal emulator (Tera Term) can't see a serial port. In Vivado (2019.2), the hardware manager can't find any device to connect to. I've tried a couple of USB cables (20cm - 30cm), which I believe are both fine, and also tried different USB ports on my PC. What should I do?
  19. vicentiu

    Audio streaming

    We have a demo project you can get started with. https://github.com/Digilent/Nexys-A7-100T-DMA-Audio https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-dma-audio-demo/start
  20. The rest of my .xdc file is comments from the other constraints I am not using. For my main design, I have three design sources with one being the top level. 1st (Top Level): module brain(input wire clk, output wire [1:0]o1, output wire [1:0]o2, output wire [1:0]o3, output wire [1:0]o4); wire new_clk; main main_unit(.clk(clk), .out(new_clk)); logic logic_unit(.clk(new_clk), .o1(o1), .o2(o2), .o3(o3), .o4(o4)); endmodule 2nd: `timescale 1ns / 1ps module main(input wire clk,output wire out); reg [18:0] r_reg; wire [18:0] r_next; always @ (posedge clk) r_reg <= r_next; assign r_next = (r_reg == 500) ? 0 : r_reg +1; assign out = ( r_reg == 500) ?1'b1 : 1'b0; endmodule 3rd: module logic( input wire clk, output reg[1:0] o1, output reg[1:0] o2, output reg[1:0] o3, output reg[1:0] o4 ); reg[18:0] count = 1; reg x1 = 1; reg x2 = 1; reg x3 = 1; reg x4 = 1; always@(posedge clk) begin if (count == 1) begin x2 <= 0; x3 <= 0; x4 <= 0; end if (count == 2) begin x3 <= 0; x4 <= 0; end if (count == 3) begin x4 <= 0; end o1 <= x1; o2 <= x2; o3 <= x3; o4 <= x4; count = count + 1; end endmodule
  21. alrekaby68

    Audio streaming

    Thank u vicentiu for your replay. I want to acquire speech samples using mic. and replay the sound through line out or HP jack.
  22. vicentiu

    Audio streaming

    What problems are you having?
  23. alrekaby68

    Audio streaming

    Hi, please can any one help me with a small Vivado project for streaming audio signals using genesys 2 or Nexys 4. Thanks in advance.
  24. adiganta

    arty gpio demo

    Dear All, I have attached a file Arty General I/O demo. If u go through the file , there is a GUI to display UART message in the computer. I am looking for the same GUI exe file. Let me know the source. Thanks. A DAS Arty General I_O Demo [Reference.Digilentinc].pdf
  25. Are you showing us all of the file? What does the top level of your design look like? Do you have any other XDC files in your project?
  26. Digilent Atlys Spartan-6 FPGA Trainer Board On Ebay https://www.ebay.com/itm/Digilent-Atlys-Spartan-6-FPGA-Trainer-Board/183940723184?
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