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  1. Today
  2. asd123

    Nexys A7 not working

    The Nexys A7 suddenly shut down when operating normally connecting to my laptop, and cannot be turned back on.
  3. TerryS

    Vivado free for Artix-7?

    Thanks for all the help. I was able to finish the Vivado install and get through the 'blinky' tutorial. Very nice documentation. It didn't exactly match the 2018.3 version of Vivado that I installed, but close enough to have me blinking an LED in no time at all. Terry
  4. Hi, I have a brand new Digilent A7-35T board I tried to program via the USB built in JTAG using Vivado 2018.2. The part intermittently shows up in Hardware Manager, but a seconds later disconnects. Sometimes it disconnects just being connected (opened) in Hardware Manager and sometimes during programming. It is even worse if I try to erase and program the QSPI flash. I also downloaded and installed the latest Digilent Adept 2 with updated drivers and observed the same behavior. I tried different USB cables, different USB ports directly on my PC, via a powered hub, but the behavior is always the same -- it intermittently disconnects and fails. The amber LED does however stay lit. In Device Manager I am able to see the FTDI UART. I did also see it enumerate as a Microsoft BallPoint Mouse -- whatever that is. With this exact same setup, PC, Vivado, USB cables, etc, I have been programming the Zybo Z7-20 and the Arty boards with several designs without any such issues. Please let me know if I missed anything and what are the next steps in getting the board replaced or fixed. Thanks.
  5. Yesterday
  6. TerryS

    Vivado free for Artix-7?

    Yep, my bad. I finally realized the download tool was reporting the rate in MBps (not mbps). So what I thought was only 1Mbps was really at least 8 times faster than that, which is about the limit of my rural internet service. The download is a whopping 18GB, which is going to take a while. Unfortunately, it kept stopping occasionally and reporting a file didn't download, and waiting for me to confirm and try again. So I couldn't just start the download and walk away. Anyway, I'm getting close. Thanks for the heads up on what to expect. It has been almost 20 years since I last did any FPGA work. Terry
  7. The Arty board has all the JTAG circuitry plus a USB UART on board. You don't need a special cable - just use a good quality USB to micro USB cable. In the Vivado IPI, when you instantiate a Microblaze core, the MDM is automatically added and connected by block automation. The Xilinx SDK debugger will automatically use the MDM for debugging. You don't have to do anything other than start your program in debug mode. It sounds to me like going through one of the numerous online tutorials would help you get your bearings. Digilent has several including this one.Prolific blogger Adam Taylor also starts a series of posts on the Arty here. And if you like watching videos, Jeff Johnson at FPGADeveloper.com has this one.
  8. I'm looking through Xilinx file pg115-mdm.pdf about the Microblaze debug module. If I use a Microblaze core, I'm sure I'll need some debug capability. But I'm not sure how the MDM can be used on an Arty board. MDM seems to be a JTAG-based debugger. I think it uses the FPGA's JTAG pins. I know the Adept2 utility uses the USB connection to access JTAG through the FTDI chip. But "JTAG debugging" isn't on the list of what Adept2 does. In the Adept SDK, I see information about an API to access JTAG. That would probably work, but I'd rather not be debugging debug system software while I'm trying to debug my Microblaze software. Another issue is if I use the existing USB cable for JTAG debugging, will I have trouble running the UART bridge interface? If I get a Digilent JTAG-HS2 and use that for JTAG, will that solve the problems? The Vivado software would know how to use the JTAG on this adapter for its debugger right? And the UART bridge would still work as usual. Do I have it right? Or am I missing something stupid. I just want to make sure there's no problem with Microblaze debugging that makes it too hard to use in my application. Thanks. Allan
  9. I'm glad to hear that you've made some progress, Raghunathan, and I greatly appreciate your patience. Nothing about your system tells me it would be interfering with the agent, so I need you to do some more digging for me. I'd like to see what the console output is when you try to add your OpenLogger. Before doing anything, visit the Settings page, and click Advanced. Click the Change Console Log button, and choose Console. Once you've done so, press Ctrl+Shift+i to open the Chrome Developer Tools, and make sure the Console tab is active. Run through adding the device until it fails again. You should see a bit more detailed information as to why it is failing in the Chrome Developer console. If you can share that with me as a screenshot or some other way, I would appreciate it. About the profile: You shouldn't have to select the last saved profile when launching WaveForms Live. Ideally WaveForms Live recognizes what profile your device has assigned to it and will load it up, but that doesn't seem to be working. If you could also give me the console output after entering the logger page (when WFL checks the device profile) and share that, we should get to the bottom of this issue as well. Thank you for your cooperation and patience, AndrewHolzer
  10. JColvin

    Vivado free for Artix-7?

    Hi @TerryS, Unfortunately, the download speeds you are reporting are due to your end (either your internet connection or your computer hardware), not Xilinx's end. Note also as a fair warning (since I believe this is your first time using Vivado) that even simple projects, such as LED blinking project that xc6lx45, will probably take more time than you expect as the Vivado software needs to program and set every transistor inside the FPGA. There is a nice comment summarizing what all the tools need to during synthesis, implementation, and bitstream generation here. But as @xc6lx45, a lot of the material looks more complicated than it actually is, mostly because it's a different language. Thanks, JColvin
  11. In the meantime I've found some errors in my timing module code. I will update as soon as I've rectified them.
  12. Hi there, I designed a small module that's supposed to feed timing signals into the rgb2dvi block provided by digilent. The code I wrote which produces this can be found here. The connections required in the block design can be seen below in the picture. The I/O planning is shown as well. I'm not getting any HDMI out of it. I checked the testbench and it produced the correct sequence of outputs. (When the VDE signal is high the screen uses the color rgb_in) Can anyone test this on his board or notice any flaws? If you run this on a zybo z7-20: To create the required clock signal use clock wizard (input 125 MHz clock on pin k17 and produce 148.5 MHz to the pixel module) Thanks a lot in advance.
  13. Hi @dcc, I'm not certain how you are verifying that the HDL is writing to and then reading back from the SD card in a normal formatting style, but in general FAT32 is a widely used format for SD cards that has existing material for it. I am uncertain why you are using a special tool to write to the SD card though; from what I can tell the tool is Windows compatible, so why not just use the Notepad program which comes with Windows and save a .txt file with the data you are interested in reading to the SD card or just using Windows Explorer (the file manager) to move the file of interest onto the SD card? If you do have a header in your file, you will need to take account for that, though I do not know what you mean by "random file" in this case. Thanks, JColvin
  14. Hi @jpeyron, Sorry for the late response, I'm busy these days. The problem is that I've never used ILA modules before and it would take time for me to understand it. Can you maybe check it really quick? The project files are available on the following link: https://www.dropbox.com/s/tjd21flsmxn650i/ZYNN_project.rar?dl=0 I appreciate your help, best regards. Toni
  15. Hi @sgrobler, Our design engineer who designed the OpenLogger did an end-to-end analysis to determine the end number of bits of the OpenLogger. This is what they ended up doing in a summarized fashion: <start> They sampled 3 AAA battery inputs to the SD card at 250 kS/s and set the OpenLogger sample rate to 125 kS/s and then took 4096 samples; they then took the raw data stored on the SD card and converted it to a CSV file and exported the data for processing. Their Agilent scope read the battery pack at 4.61538 V and as they later found from FFT results the OpenLogger read 4.616605445 V, leading to a 0.001226445 V or ~1.2mV difference, which is presuming the Agilent is perfect (which it is not), but it was nice to see that the values worked out so closely. They calculated the RMS value of the full 4096 samples in both the time domain and using Parseval's theorem in the frequency domain as well, both of which came up with the same RMS value of 4616.606689 mV, which is very close to the DC battery voltage of 4616 mV. Because RMS is the same as DC voltage, this gives the previously mentioned DC value of 4.616605445 V. They can then remove the DC component from the total RMS value to find the remaining energy (the total noise, including analog, sampling, and quantization noise) of the OpenLogger from end-to-end. With the input range of +/- 10V input, this produces an RMS noise of 1.5mV. At the ADC input, there is a 3V reference and the analog input front end attenuates the input by a factor of 0.1392, so the 1.5mV noise on the OpenLogger is 0.2088mV at the ADC. With the 16 bits (65536 LSBs) over 3V, 0.0002088V translates to ~4.56 LSBs of noise. The ENOB is a power of 2, so log(4.56)/log(2) results in 2.189 bits, giving us a final ENOB of 16 - 2.189 = ~13.8 bits. Note though that this ENOB of 13.8 bits is based on system noise and not dynamic range, so for non-DC inputs (which will likely be measured at some point) the end number of bits is not easily determined. The datasheet for the ADC used in the OpenLogger (link) shows that the ADC itself gives an ENOB of about 14.5 bits at DC voltage (so the 13.8 bits is within that range), but at high frequencies, this of course rolls off to lower ENOB at higher frequency inputs. Thus, they cannot fully predict what the compound ENOB would be over the dynamic range, but they suspect it all mixes together and is 1 or 1.5 bits lower than the ADC ENOB response. </end> Let me know if you have questions or would like to see the non-abbreviated version of his analysis. Thanks, JColvin
  16. Hi @M.Mahdi.T, Welcome to the Digilent Forums! We typically do not test the max throughput metric when validating our products. Looking at the AD5933 datasheet here the Pmod IA would be limited to 1 MSPS due to the on board ADC. The main bottleneck for throughput to a host board will be the I2C communication which runs at 400 KHz. Here is a good forum thread for using the Pmod IA with the Raspberry PI with code and hints for use , setup and calibration. Here is the resource center for the Pmod IA which has the Raspberry PI code as well. best regards, Jon
  17. Hi @PG_R, I have connected many different fpga's to my PC through Ethernet using a standard Ethernet cable. I believe a regular ethernet cable will do just fine. The difficult process will be facilitating the ethernet communication. That is why I suggested using the petalinux project linked above. best regards, Jon
  18. @Ahmed Alfadhel To understand what's going on, check out table 8 of the datasheet on page 15. Basically, the DAC provides outputs between 0 and max, where 0 is mapped to zero and all ones is mapped to the max. In other words, you should be plotting your data as unsigned. To convert from your current twos complement representation to an unsigned representation where zero or idle is in the middle of the range, rather than on the far end, just toggle the MSB. Dan
  19. Hi @Allan Flippin, Here is the VHDL code for the UART TX from our GPIO demo for the Arty-A7-100T which sets the tx baud rate to 9600. I have not used auto baud detection since typically we dictate the baud rate in our projects. best regards, Jon
  20. Hi @tjaplayer, When you say WaveForms would not recognize it, do you mean WaveForms does not detect the Analog Discovery 2 at all, or does it just come up as an unknown device? Additionally, are you able to see the Analog Discovery 2 on the Windows Device Manager (presuming) you are Windows? It will appear as "USB Serial Converter" under Universal Serial Bus controllers. Thank you, JColvin
  21. Jon, Thanks. I'm looking at the information from ftdichip.com. The only thing I'm unclear about is how the baud rate is set? I'm trying to find out if my HDL UART block will need auto-baud detect. Allan
  22. Hi @Allan Flippin, If you use the Arty-A7 35T or 100T or the Arty-S7 50T or 25T you can use a HDL(Verilog/VHDL) UART controller to communicate through the USB UART bridge. ZYNQ FPGA's have some of the components on the board tied directly to the Arm processor(PS). The DDR3 and USB UART bridge would be included in these components. With ZYNQ FPGA's you can not use the PL to directly use the USB UART bridge. I have attach an image that is a good reference on the ZYNQ processor. To use the USB UART bridge with the Arty-Z7 20 or Arty-Z7 10 you would need to use the Zynq processor. Here is the getting started with ZYNQ tutorial for the Zybo that can easily be used with the Arty-Z7 . The GSWZ tutorial shows how to use the PS to communicate through the USB UART bridge. Here is the Arty-Z7 , Arty-A7 and Arty-S7 resource centers. best regards, Jon
  23. Hi @hmd, I'm glad to hear that the command which vivado helped you find the path needed to complete the installation. Thank you for sharing what you did. best regards, Jon
  24. I bought an Analog Discovery 2 on 8/23/17. I used it my first year for labs. I stopped using it from December ,2018 till April 2019. When I went to go use it a week or two ago, it would not work. Waveform would not recognize it. The led would not light up when plugged in. I tried using different cables and on different computers to test out if it was just a connection issue. Any feedback on what can be done to help fix this issue is greatly appreciated.
  25. Dear friends! I solved the problem. To me everything was competently explained by the great expert Mikhail Korobkov. He is an employee of СTС "INLAYN GRUP". Problem reason: the name of the computer cannot be written with the Russian letters. The subject is closed.
  26. It's hard to tell why the files aren't being added without seeing your exact setup (recipes, config files, etc). One of the causes for "not a dynamic executable" is some missing libraries, but there could be other causes. I saw you also posted on Xilinx's forum. The fact that it works in 2015 but not in 2017 indicates some changes were made in how Petalinux deals with adding components. Have you checked the differences in the user guides between 2015.4 and 2017.4? Check the sections about adding components and Appendix G: Obsolete Features. Other than that, Xinlinx devs can comment better on why it wouldn't work in 2017.
  27. bogdan.deac

    OpenCV and Pcam5-c

    Hi @Esti.A, If you clone the repo you obtain the "source code" for the platform and you have to generate the platform by yourself. This is a time consuming and complicated task and is not recommended if you do not understand SDSoC very well. I advise you to download the last SDSoC platform release from here. You will obtain a zip file that contains the SDSoC platform already build. After that, you can follow these steps to create your first project.
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