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Hello, I bought a Basys 3 two months ago, the problem is the basys is not turning on, yesterday it was ok, I tried everything, I changed the USB Port with I was working, I connected it directly to the light and nothing

It will not be a problem to access ther FPGA over a USB Hub. Take a look into the Device Driver of your PC, all serial connections to the USB will be separately listed.

This helped a lot to me too. Just for additional info for those who cannot manage to force push it to the connector, I found what I needed was to physically bend (or straighten) the pins. I used a pin socket, push it towards the desktop. I needed to be cafeful to not let it be pushed too much and have it stuck. I still needed big pliers to remove it.

Hi @VictorV Please use Vertical Scale: Decibel instead of expressions: Using expressions to convert from a ratio to decibels is unnecessary, and as seen, produces incorrect results. We were told that this is due to the fact that the underlying representation of Vout and Vin is a complex number rather than just the magnitude. The same odd result of trying to calculate a ratio by dividing complex numbers like this also occurs in other SPICE-based simulators. You could calculate the magnitude with an expression of "Mag=sqrt((real(Vout))^2+(imag(Vout))^2)" and produce the expected high-pass plot (as seen below), however, there's not much reason to when the dB scale exists. Thanks, Arthur

I am a novice FPGA and Vivado user and I am facing some problems. I need to apply a Cordic phase to get an output signal. To do this, I added Cordic in Vivado 2019.1 and selected its "Sin and Cos" mode of operation. I've been studying testbench for a long time, but I still haven't figured out what I need to change in order to supply a phase input and get a sine wave output. And I also don't understand why the input is a sine and cosine, and the output is a signal of an incomprehensible shape. Inputs: s_axis_cartesian_tdata[31:0], s_axis_phase_tdata[15:0]. Output: m_axis_dout_tdata[31:0]. I hope someone can help.

I want to get a USB hub because my laptop doesn't have enough USB ports. I'll connect a keyboard, mouse, a USB cable for UART communication, and another cable for programming the FPGA. So let's say I connect 4 USB cables. What concerns me is that ultimately these 4 USB inputs are connected to the same USB port at the final. In this case, would it be possible to both program the FPGA and communicate via UART through the same USB port? and at the same i will be using keyobard, mouse I hope I've explained it clearly. As far as I've researched on the internet, a USB hub should be of high quality, meaning it should be able to provide high power (some USB hubs can be powered by an adapter). However, the question I'm asking is a bit more specific. Because UART is a serial communication protocol. I don't know the internal structure of USB, but I don't think we can perform parallel processing. Please correct me if I'm wrong. @asmi @zygot

Hi @rain, I have split your post off into a new topic. You could just use some sort of external module, be it a Pmod SWT or something else, as a replacement option for the collection of on-board switches, but there are a few catches with this method. One is that you will inevitably lose out on total available pins that are available to the user. This might not always be an issue if a design doesn't use all of the general purpose input/output pins, but it feels like kicking the problem further down the road. The second is .xdc file (file that tells the Xilinx software which ports in a design are connected to what physical pin on the FPGA) that Digilent provides will no longer be correct. While you can certainly edit the .xdc file to instead say that all (or just a select few) of the switches are instead attached to some other FPGA pin that goes to a Pmod port (and sets up a good habit of checking and becoming familiar with the .xdc file), this can become a hassle to have to correct every time, especially if the external switches move to different Pmod ports and it is a different collection of switches on the Nexys that are being exchanged out. It's been a few years since I've had to do any soldering and I wasn't an expert by any stretch of the imagination, so take this next bit with a grain of salt: I do not know which Nexys board you are using (Nexys A7, Nexys Video, etc.) nor do I know your set up or if you are just replacing the slide switches for different ones or with entirely different I/O devices or whatever, but I would probably look to get some sort of clamp stand (maybe even one designed to hold up an iPad rather than just alligator clips) to hold the board up on its side so that I could heat the underside of the through hole contacts with a soldering iron and pull out the switches with some sort of needle nose pliers. Let me know if you have any questions. Thanks, JColvin

Hi, Around month or two I trying add SD card for my project on KC-705, but all this time I can't find any information for this. All I found is Pmod ip core, which KC-705 not supported and logisdhc ip core, which I don't know how connecting to my board. I will be glad see any help with this stuff.

Hello Arthur, I am following up to my previous question. I understood that running a python script with a neural network on the ADP3450 is possible. I would like to ask the following follow-up question: Is the below doable? 1. Training a neural network to run in python script. The training can be done on a host PC. 2. Saving the trained neural network. When the neural network is trained, it has parameters that will use to predict the output when it receives a new input. 3. Running the trained neural network in a python script on the ADP3450 while running in Linux mode.

Our Data Acquisition Handbook is a great place to start. https://files.digilent.com/reference/data-acquisition-handbook.pdf

Please review page 18 in the user manual for case dimensions and the attached files for the ACC-205. The ACC-205 kit includes a set of 4-20 x 5/16" screws used to mount the bracket to the existing holes on the bottom of the E-1608 case. ACC_205_DIN_clip_50mm.pdf MCC_ACC-205-assm_50mm-l_din_clip_4-hole_asm.stp

I have been asked to change the 8 slide switches on a Nexys board, and I have around 10 boards to complete. Just removing one switch is challenging......would it be any alternative by using the Pmod header interface ? Having Pmod SWT: 4 User Slide Switches x 2 ? and adding Pmod LED ? or do you have any idea ?

Hello i want to learn the data acquisition on the mcc usb daq 205 and can you share if there is any sort of resources where i can refer to it and know more about DAQ, thanks

@wayyu, You can use the DDR3 Control IP core provided by Xilinx. The Ip is free to use. Using the GUI of the IP you can select AXI as the user_interface for the Ctrl Core. There is also the Ctrl IP core documentation, MUST read it. Also there is an example_design in there which you MUST try out before creating your custom design.

Hello! We need to integrate the MCC E-1608 DAQ into a prototype. For that we would like to use the ACC-205 DIN Rail Kit but we did not find any drawing, CAD or dimensions for this item. Please could anyone help us? The minimum information we need is the size of the included screws and the spacing between the holes of the rails. Thank you. Javier

@Michael Bradley I have not taken a look for a long time into the Zybo Z7 pin mapping file. But I can tell you from memory that the PMOD connections are generally connected to the FPGA GPIO pins, so that you can control them as as you like. So the answer to your question would be a yes!

Board: Zybo Z7-10 Software: Vivado Lab Edition 2020.2 Debugger: Xilinx Platform Cable USB II When my Zybo Z7-10 board is connected to the PC using the USB cable, the Software can detect both the PL and PS. All good here! It is my desire, not to use the USB2JTAG bridge to access the FPGA over JTAG. Instead, I want to use the J13 header (I have soldered the pins in there for connection) for JTAG connection to access the FPGA. The Xilinx Platform Cable USB II has the JTAG cables at one end and I want to plug these into the J13 to have JTAG access. At the end Software needs to identify the FPGA over this direct JTAG connection. Is it possible? How can I do it? Is there some jumper settings I must change to facilitate this? Note that I am still using the USB to power the board, so the USB2JTAG is always remaining activated by default. Should I need to change to a 5V DC adapter to power the board when I want to the JTAG over J13? I have also referred here - https://digilent.com/reference/programmable-logic/zybo-z7/reference-manual but did not find any guidance to activate the JTAG over J13 header. Please advise.

I have a flash ADC built and I am trying to use my FPGA as the priority encoder. I need to connect the 3.3 and 0 V signals coming off of the comparators to my FPGA. I don't see any general purpose IO pins like an Arduino has so I was curious as to how I should connect the wires. Can I just use the PMOD ports for this purpose and alter the constraints/xdc file to map to whatever name I give them in the verilog code?

The output rate is about 1 kHz, and the range is +/-5V typically (though we've also tried +/- 10V). I configured the PCIe-DAS1602 for differential and that didn't seem to help. I am using comedi in Ubuntu to read from the board, and have been working to specify the input range as well.

and I need the complete kit

yes please

After applying that fix, I'm also seeing the last five bytes of the last packet be corrupted and need to look into it some more. At least with RECV_BUFFER_SIZE 200000, words_per_packet, 50000, packets 4. Updated main.c is attached. main.c

Hi @NAOUZ Could you restate your question? Are you looking for a Nexys A7 board that can use a 7-15 V external supply instead of a 5 V supply? Thanks, Arthur

Hi @Alturan Welcome to the forum. Storing data in block RAM (or just LUTs) and counting through addresses is a standard way of doing this kind of thing. Each SPI transfer sent to the DAC would have a new value - like your data_i signal would be a new piece of data read out of a BRAM at the start of every transfer, incrementing the address every transfer. You would use a separate counter to control when each new SPI transaction starts to control the sample rate - assuming a 100 MHz clock, you could get a 1 MS/s DAC update rate if whenever a counter counts to 100, a new transfer is initiated, although it looks like your controller currently takes 120 clocks to send out a transfer. You can even control the frequency of the output signal by changing how much the address counter goes up each transfer - adding 10 to a counter that rolls over when it goes above 255 lets you count through a lookup table 10x faster than adding 1 each time. I'd also recommend simulating your HDL as you go, before testing in hardware - using "if clk_divided = '1' then" instead of "if clk_div_counter = CLOCK_DIVIDER - 1 then" for the shift register enable is concerning - it's probably active for 5 clocks in a row, then idle for the next 5, rather than active for one in every five clocks, like I assume is intended. Check out this guide: https://digilent.com/reference/programmable-logic/guides/simulation. Thanks, Arthur

Hi @ericnstein, I have sent you a PM. Thanks, JColvin