All Activity

This stream auto-updates     

  1. Past hour
  2. Hi @akeener The .customz is used as a mask. Bits of ones make the output high impedance Z, where it is zero the bit of .custom is used to drive low/high, 0/1 Here for instance the last .customz sample is 2 which makes bus[1] Z and the last .custom is 1 makes bus[0] 1, and the other bus[3-2] will be 0.
  3. Today
  4. This seems relevant: The same goes for GTX transceivers on the G2. Either use the wizard for your IP and do the lane mapping there, or instantiate it as GTX primitives and write a LOC constraint for the channel primitive. Since the channel primitive is fixed to its pins and there is no IOSTANDARD to specify, you do not need to constrain the pins at all. This is what I see in the JESD wizard.
  5. Hi @jamesbraza Yes, you are right. The application, the IA measures the DUT relative to a reference resistor, using the Scope Channel 1 vs 2 inputs. From this it can calculate the voltage/current. Taking in consideration the scope probe impedance and open/short compensation can calculate further values: impedance Z/Rs/Xs (Rp/Xp rarely used); admittance Y/Gp/Bp (Gs/Bs rarely used); series or parallel equivalent inductance or capacitance... See the following documents: https://cdn.testequity.com/documents/pdf/series-parallel-impedance-parameters-an.pdf 1.6 Equivalent circuit models of components, page 13 : https://literature.cdn.keysight.com/litweb/pdf/5950-3000.pdf
  6. Alex_V

    PROBLEM WITH NEXYS A7 EVB

    Hi Jon, Have you tried using different usb cables? - YES Is the mode jumper set to JTAG? - see attached picture What does the Nexys A7 show up as in the device manager under pots and universal serial bus controllers? The board not only recognized by the PC it also connected to Vivado Hardware Manager - see attached picture Thank you, Alex
  7. Xilinx Tools FPGA and ARM Coding? How does one program the newer boards with HDL and C coding on one platform? Do the tools support both processor and VHDL or Verilog? I don't see the big picture here. I am working the Spartan 3 and 6 designs. I would like to move into the Artix 7 at some point. I need a working platform for USB 3.0 and Ethenet 1 G. Phil
  8. Hi Andrew I just tuned out for some weeks to see if there are any updates posted in the interim. And whether that will help my now Openlogger that is not Win10 friendly. But still the same status. I see that there is a new firmware 0.1807 but of course that never updates as it fails in the end. And I try to do a raw update without bootloader but for that the Web page is still only the 0.1719 version. You cannot win either way !! I have checked Task Manager and only one version of the Agent is running ( Version 1.4) and I am able to see a page " Debug Controller page …" And that's it …. no logging to SD card .... no WiFi. The board is idling happily. Actually I feel bad in posting only problems here.. as I am sure such a product would have passed rigorous testing. Maybe I am stuck with a dud piece.
  9. I am using a nexys A7: fpga trainer board and the piezo is a dt series with lead attachment. (Sorry I didn't respond earlier, I'm new to the forum.) Thank you.
  10. Jon, Thanks for the pointer on the ILA. Whereas I wasn't able to get the module running in my block design I was able to find my problem. The simulation ran fine for my IP but when I tried the Implemented Simulator, I'm seeing exactly what I see on my o-scope which is a 12nS pulse. I have no experience in troubleshooting between simulator and implemented design. Any suggestions? Cheers
  11. Yesterday
  12. Hi All ! I am trying to build Analog Discovery 2 from Gitlab that is cloud base ruby server. what is the command line that I can install Adept and Waveform on a cloud server NON- Windows-based and build python project based on that. I tried many ways but it keeps on complaining can not find libdwf.so file. OSError: libdwf.so: cannot open shared object file: No such file or directory Please advise. Thank you! Rozita
  13. Hi @newkid_old, I would suggest using the ILA module. Here is a Xilinx forum that discusses this. Here is the Integrated Logic Analyzer v6.2 LogiCORE IP Product Guide that should also be helpful. Best regards, Jon
  14. Hi @jpeyron, Thank You! Best wishes, Harshith
  15. Hi @thk3695, I sent you a PM about this. best regards, Jon
  16. I am using a nexys A7: fpga trainer board and the piezo is a dt series with lead attachment. Thank you, John
  17. Hello guys, I had the same issue today. I accidentally erased the FTDI chip on the HS3 when I was trying to program another FTDI device (FT2232H) on the same machine. Please if possible let me know the instructions to reprogram the FTDI chip on the HS3. Thanks in advance. Harshith
  18. Hi @brian.dig, Glad to hear that you were able to to download the SOV. best regards, Jon
  19. Perhaps I misunderstood your question. Since Digilent doesn't make any FMC mezzanine boards using the transceivers their basic constraints file ignores these pins. One possibility is to look at one of the ADI FMC 204B project files and see what they use for IOSTANDARD property values. ADI does target the KC705 and the Genesys2 heavily borrows from that design. I don't know if there even is a Kintex transceiver Application Note for transceivers as neither Intel or Xilinx is particularly interested in help users use transceivers for any but the high end devices. Perhaps the @elodgDigilent engineer who characterised and tested the Genesis2 FMC transceivers has some information. I don't believe that the transceiver pins support any IOSTANDARD but are dedicated for use as transceiver IO.
  20. JColvin

    Help for project

    Hello @johnsan1, I responded to your other thread here. Thanks, JColvin
  21. Hi @johnsan1, I'm not certain which exact piezo sensor you are looking at (since the datasheet for the piezo sensor had a variety of sensors), but based on the one that matches the image, I think it would be compatible with the system board. Realistically, the piezo sensor would not affect the functionality of either the Pmod TC1 or the Pmod WiFi and it would matter if it is compatible with your intended system board. Do you happen to know what system board you are intending to use? Thanks, JColvin
  22. Jon, I was able to download the PM'd version of the file, thanks. I don't know why the PDF linked in the above post doesn't work for me. Thanks for the help!
  23. Hi @AndyCap, Glad to hear you were able to get past this issue. Thank you for sharing what you did. best regards, Jon
  24. Hi @brian.dig, Welcome to the digilent forums.! I have PM'd you a copy of the SOV for the JTAG-HS3. Please let us know if you were able to download this. Best regards, Jon
  25. I wasn't referring to IOSTARDARD when I was mentioning pin name/functionality. Everything that you need to know about IOSTANDARD capabilities of any IO pin is in Xilinx UG-471. Note that the Genesis2 uses the Kintex device and has both HP and HR IO banks. Digilent FMC equipped boards use a user settable Vadj voltage for FMC IO and this influences what possible IOSTANDARD you can opt to use. Just read the Xilinx literature.... JESD204B is great but uses transceivers so... if you want to use those you need to read through UG-476 as well. I'm not aware of any Ti FMC ADC EVMs that target Xilinx FPGA boards. I'm assuming that you are making your own FMC mezzanine card. ??? I am also not aware of anyone offering JESD204B IP for free. Make sure that you know what you are doing as there are lot's of unhappy surprises for the uninformed and unprepared. The best chance of success is to choose a third party ADC FMC mezzanine board from a vendor that supplies some source code operability for a Xilinx board compatible with the Genesis2. Given the licensing issue you might find this advice hard to act on. [edit] Analog Devices offers JESD204B ADC devices and a few FMC cards with them. They generally have some good FPGA support but good luck trying to change their demo source to fit a custom application. You might want to snoop around the ADI website. Caution!!! The devil is in the details.. and the vital details are usually hard to come by without a lot of work. Pin assignments by FPGA board vendors can break a project so expect to spend some time tracking down each pin on the schematic for compatibility. Been there, done that on a few occasions. MAKE NO ASSUMPTIONS!!!
  26. Hi @Y_H, The Jupyter Notebook platform along with adding additional Pmod's to this platform is supported by PINQ.IO . You will need to reach out to PYNQ.IO Support here. best regards, Jon
  1. Load more activity