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Hello Check below steps Understand Hardware: Know Nexys A7 FPGA board and Pmod AQS sensor. Learn VHDL Basics: Get familiar with VHDL syntax and data types. Study I2C Protocol: Learn about I2C communication. Implement I2C Communication: Set up basic communication between devices. Interface with Pmod AQS: Read air quality data from the sensor. Calibration and Testing: Ensure accurate measurements and test functionality. Documentation and Support: Document your work and seek help if needed. Hope it helps

In Network Analyzer you can set Source: External and control the sweep from Wavegen or external equipment. The NA will look for peak in the spectrum and consider this the signal frequency. Under Options menu you can adjust the External Threshold, the minimum peak magnitude. Depending or number of Steps, set the sweep time to seconds or minutes, for wide logarithmic scales you can adjust the sweep frequencies manually. When all the step points are captured it will draw a line, until this only dots.

Thank you!!! can you please post me any link or document to interface high speed ADC with zynq soc

Hi, I am trying to design an ethernet controller for my Genesys 2. From specifications (RGMII, Realtek RTL8211E-VL PHY) or other projects (special thanks to @zygot and his Ethernet PHY Test Tool project), I have successfully implemented the Tx transmitter part: I can now see the different packets with WireShark. However, I am now facing a problem in the Rx receiver part. After analyzing the signals, I've noticed that the issue seems to come from the signals that are received from the PHY. Below is a screenshot of a received packet observed from an ILA: the sampling clock is at 500MHz (so the waveform accuracy must be put into perspective). The original packet starts with: ff ff ff ff ff ff a4 b1 c1 31 d8 05 08 00 45 00 ... But as early as the preamble/SFD, it seems that a shift exists with the first 4 bits received on a falling edge. So my frame becomes 5X 55 55 55 55 55 55 fd ff ... instead of the expected 55 55 55 55 55 55 55 5d ff... And it stays like that until the end of the frame, and for all the received frames. Here are the corresponding Verilog and constraints parts inspired by the previously mentioned sources: // Verilog top file input logic i_eth_mii_rx_clk; // Input Rx Clock input logic i_eth_mii_rx_ctl; // Input Rx CTL input logic [3:0] i_eth_mii_rx_data; // Input Rx Data logic w_eth_mii_rx_clk; // Internal Rx Clock logic w_eth_mii_rx_rst; // Internal Rx Reset logic [1:0] w_eth_mii_rx_ctl; // Internal Rx CTL logic w_eth_mii_rx_en; // Internal Rx Enable logic w_eth_mii_rx_err; // Internal Rx Error logic [7:0] w_eth_mii_rx_data; // Internal Rx Data ... assign w_eth_mii_rx_clk = i_eth_mii_rx_clk; ... IDDR #( .DDR_CLK_EDGE ( "SAME_EDGE_PIPELINED" ), .INIT_Q1 ( 1'b0 ), .INIT_Q2 ( 1'b0 ), .SRTYPE ( "SYNC" ) ) m_IDDR_eth_mii_rx_en ( .Q1 ( w_eth_mii_rx_ctl[0] ), .Q2 ( w_eth_mii_rx_ctl[1] ), .C ( w_eth_mii_rx_clk ), .CE ( 1'b1 ), .D ( i_eth_mii_rx_ctl ), .R ( w_eth_mii_rx_rst ), .S ( 1'b0 ) ); assign w_eth_mii_rx_en = w_eth_mii_rx_ctl[0]; assign w_eth_mii_rx_err = w_eth_mii_rx_ctl[1] ^ w_eth_mii_rx_ctl[0]; genvar et; generate for (et = 0; et < 4; et = et + 1) begin IDDR #( .DDR_CLK_EDGE ( "SAME_EDGE_PIPELINED" ), .INIT_Q1 ( 1'b0 ), .INIT_Q2 ( 1'b0 ), .SRTYPE ( "SYNC" ) ) m_IDDR_eth_mii_rx_data ( .Q1 ( w_eth_mii_rx_data[et + 0] ), .Q2 ( w_eth_mii_rx_data[et + 4] ), .C ( w_eth_mii_rx_clk ), .CE ( 1'b1 ), .D ( i_eth_mii_rx_data[et] ), .R ( w_eth_mii_rx_rst ), .S ( 1'b0 ) ); end endgenerate # Top constraints file ... ## Ethernet PHY set_property -dict { PACKAGE_PIN AK16 IOSTANDARD LVCMOS18 } [get_ports { i_eth_int_b }]; set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { i_eth_pme_b }]; set_property -dict { PACKAGE_PIN AH24 IOSTANDARD LVCMOS33 } [get_ports { o_eth_phy_rstn }]; set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS15 } [get_ports { o_eth_mii_mdc }]; set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS15 } [get_ports { t_eth_mii_mdio }]; set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS15 } [get_ports { o_eth_mii_tx_clk }]; set_property -dict { PACKAGE_PIN AK14 IOSTANDARD LVCMOS15 } [get_ports { o_eth_mii_tx_ctl }]; set_property -dict { PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15 } [get_ports { o_eth_mii_tx_data[0] }]; set_property -dict { PACKAGE_PIN AK11 IOSTANDARD LVCMOS15 } [get_ports { o_eth_mii_tx_data[1] }]; set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15 } [get_ports { o_eth_mii_tx_data[2] }]; set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS15 } [get_ports { o_eth_mii_tx_data[3] }]; set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS15 } [get_ports { i_eth_mii_rx_clk }]; set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS15 } [get_ports { i_eth_mii_rx_ctl }]; set_property -dict { PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15 } [get_ports { i_eth_mii_rx_data[0] }]; set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS15 } [get_ports { i_eth_mii_rx_data[1] }]; set_property -dict { PACKAGE_PIN AK13 IOSTANDARD LVCMOS15 } [get_ports { i_eth_mii_rx_data[2] }]; set_property -dict { PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15 } [get_ports { i_eth_mii_rx_data[3] }]; ## Clocks create_clock -add -name CLK_ETH_MII_RX -period 8.00 -waveform {0.0 4.0} [get_ports {i_eth_mii_rx_clk}]; create_generated_clock -name CLK_25MHZ [get_pins m_MMCME2_BASE/CLKOUT1] create_generated_clock -name CLK_50MHZ [get_pins m_MMCME2_BASE/CLKOUT3] # Design Cock create_generated_clock -name CLK_125MHZ [get_pins m_MMCME2_BASE/CLKOUT4] # Tx Clock create_generated_clock -name CLK_125MHZ_P90 [get_pins m_MMCME2_BASE/CLKOUT5] # Tx Clock with 90 Phase Shift create_generated_clock -name CLK_500MHZ [get_pins m_MMCME2_BASE/CLKOUT6] # ILA Clock set_clock_groups -asynchronous -group {CLK_50MHZ CLK_ETH_MII_RX CLK_125MHZ} After several checks, I seem to have used the same blocks (IDDR) and constraints as in the examples I've seen. However, what I'm observing doesn't seem to be consistent with what I expected. Any idea what I might have missed as a problem or constraint? I'm pretty sure it must be an obvious problem, but impossible for me to identify it ... Thanks for your help!

yes, I would need to have a fixed offset. Example: An input frequency of ~14MHz would be mixed to 900kHz. I would like to sweep the input frequency within a span of ~5MHz and measure the amplitude of the resulting frequency. Is it possible to use a script for this purpose?

Hi @Andreas Schröck This is currently not possible. Do you need a fixed offset between the two frequencies?

I would need to measure a mixer using the Network functionality. Currently, it is not possible to set a frequency offset between the wavegen and the measurement. Any suggestions where I can start to search for additional information?

Hi @gcb As you can see in the changelog, beta versions are frequent updates that add new features and fix bugs. The release version comes out about twice a year, usually in sync with a product release, and is tested a bit more. These are useful in class so that everyone uses the version over the course of a semester.

I have trying to interface PMOD AD1 to CoraZ7 , board but im facing issue with genarating bitstream , ERROR Implementation Write Bitstream DRC Pin Planning [DRC NSTD-1] Unspecified I/O Standard: 8 out of 138 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ja_pin10_io, ja_pin1_io, ja_pin2_io, ja_pin3_io, ja_pin4_io, ja_pin7_io, ja_pin8_io, and ja_pin9_io. [DRC UCIO-1] Unconstrained Logical Port: 8 out of 138 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ja_pin10_io, ja_pin1_io, ja_pin2_io, ja_pin3_io, ja_pin4_io, ja_pin7_io, ja_pin8_io, and ja_pin9_io. [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

can you please help me with that?

Yep, Pmod I/Os are generally general purpose. Just make sure that whatever circuit you're connecting to shares a ground with the board.

Hi @loser Try pushing some known points in and see what the result is - change the testbench input and see what happens. Below is a testbench that just counts through all bit values that phase could be, using your IP settings: module cordic; reg clk; initial begin clk = 0; forever #0.5 clk = ~clk; end reg [15:0] din; wire [31:0] dout; wire dout_valid; initial begin din <= 0; forever @(posedge clk) din <= din + 1; end cordic_0 dut ( .aclk(clk), .s_axis_phase_tdata(din), .s_axis_phase_tvalid(1'b1), .m_axis_dout_tdata(dout), .m_axis_dout_tvalid(dout_valid) ); endmodule Waveform Style -> Analog Settings for dout: Radix -> Real Settings for dout: Thanks, Arthur

I have ordered 4 ARTY-Z7-20 boards in the last few years. I bought 2 a month ago (Rev D), and 2 several years ago (Rev B). There seem to be some build quality issues, or perhaps someone can explain why out of *Four Arty-Z7 boards*, *NONE* of them work completely. They fail in 3 different ways: OTP memory doesn't work, ethernet PHY doesn't work, or the ARM program will not launch at all. I developed a simple telnet interface running on the ARM (from a simple TCP echo example), utilizing lwip library and the RJ45 network connection. It echoes a few commands and gets some data from the FPGA. However, all 4 boards have problems. Only board #1 can successfully run the telnet program on the ARM. However, this board cannot read the OTP memory, which has a unique ID that I need to read (EUI-48ID). Boards #2 and #3 cannot run the telnet program. They fail during the ethernet PHY autonegotiation, with the message: Start PHY autonegotiation Waiting for PHY to complete autonegotiation. autonegotiation complete Phy setup error Phy setup failure init_emacps Board #4 immediately fails after programming (via the PROG USB) with a strange error in a VITIS popup dialog: Error while launching program: Memory write error at 0x109000. MMU section translation fault I am extremely frustrated by this. With 4 boards, none of them work 100%, each with different failure modes. Can someone please explain? Otherwise, it seems Digilent has a serious problem with build quality and board testing.

The Nexys A7 only supports 5 V power at the barrel jack input. You might be able to use a DC-to-DC converter to step your input voltage down to 5 V. That said, we don't have any particular converters that we've tested to recommend.

I found those examples - great! What is in the beta version of Waveforms that I need? I will download it, of course - just curious...

Hello, I bought a Basys 3 two months ago, the problem is the basys is not turning on, yesterday it was ok, I tried everything, I changed the USB Port with I was working, I connected it directly to the light and nothing

It will not be a problem to access ther FPGA over a USB Hub. Take a look into the Device Driver of your PC, all serial connections to the USB will be separately listed.

This helped a lot to me too. Just for additional info for those who cannot manage to force push it to the connector, I found what I needed was to physically bend (or straighten) the pins. I used a pin socket, push it towards the desktop. I needed to be cafeful to not let it be pushed too much and have it stuck. I still needed big pliers to remove it.

Hi @VictorV Please use Vertical Scale: Decibel instead of expressions: Using expressions to convert from a ratio to decibels is unnecessary, and as seen, produces incorrect results. We were told that this is due to the fact that the underlying representation of Vout and Vin is a complex number rather than just the magnitude. The same odd result of trying to calculate a ratio by dividing complex numbers like this also occurs in other SPICE-based simulators. You could calculate the magnitude with an expression of "Mag=sqrt((real(Vout))^2+(imag(Vout))^2)" and produce the expected high-pass plot (as seen below), however, there's not much reason to when the dB scale exists. Thanks, Arthur

I am a novice FPGA and Vivado user and I am facing some problems. I need to apply a Cordic phase to get an output signal. To do this, I added Cordic in Vivado 2019.1 and selected its "Sin and Cos" mode of operation. I've been studying testbench for a long time, but I still haven't figured out what I need to change in order to supply a phase input and get a sine wave output. And I also don't understand why the input is a sine and cosine, and the output is a signal of an incomprehensible shape. Inputs: s_axis_cartesian_tdata[31:0], s_axis_phase_tdata[15:0]. Output: m_axis_dout_tdata[31:0]. I hope someone can help.

I want to get a USB hub because my laptop doesn't have enough USB ports. I'll connect a keyboard, mouse, a USB cable for UART communication, and another cable for programming the FPGA. So let's say I connect 4 USB cables. What concerns me is that ultimately these 4 USB inputs are connected to the same USB port at the final. In this case, would it be possible to both program the FPGA and communicate via UART through the same USB port? and at the same i will be using keyobard, mouse I hope I've explained it clearly. As far as I've researched on the internet, a USB hub should be of high quality, meaning it should be able to provide high power (some USB hubs can be powered by an adapter). However, the question I'm asking is a bit more specific. Because UART is a serial communication protocol. I don't know the internal structure of USB, but I don't think we can perform parallel processing. Please correct me if I'm wrong. @asmi @zygot

Hi @rain, I have split your post off into a new topic. You could just use some sort of external module, be it a Pmod SWT or something else, as a replacement option for the collection of on-board switches, but there are a few catches with this method. One is that you will inevitably lose out on total available pins that are available to the user. This might not always be an issue if a design doesn't use all of the general purpose input/output pins, but it feels like kicking the problem further down the road. The second is .xdc file (file that tells the Xilinx software which ports in a design are connected to what physical pin on the FPGA) that Digilent provides will no longer be correct. While you can certainly edit the .xdc file to instead say that all (or just a select few) of the switches are instead attached to some other FPGA pin that goes to a Pmod port (and sets up a good habit of checking and becoming familiar with the .xdc file), this can become a hassle to have to correct every time, especially if the external switches move to different Pmod ports and it is a different collection of switches on the Nexys that are being exchanged out. It's been a few years since I've had to do any soldering and I wasn't an expert by any stretch of the imagination, so take this next bit with a grain of salt: I do not know which Nexys board you are using (Nexys A7, Nexys Video, etc.) nor do I know your set up or if you are just replacing the slide switches for different ones or with entirely different I/O devices or whatever, but I would probably look to get some sort of clamp stand (maybe even one designed to hold up an iPad rather than just alligator clips) to hold the board up on its side so that I could heat the underside of the through hole contacts with a soldering iron and pull out the switches with some sort of needle nose pliers. Let me know if you have any questions. Thanks, JColvin

Hi, Around month or two I trying add SD card for my project on KC-705, but all this time I can't find any information for this. All I found is Pmod ip core, which KC-705 not supported and logisdhc ip core, which I don't know how connecting to my board. I will be glad see any help with this stuff.

Hello Arthur, I am following up to my previous question. I understood that running a python script with a neural network on the ADP3450 is possible. I would like to ask the following follow-up question: Is the below doable? 1. Training a neural network to run in python script. The training can be done on a host PC. 2. Saving the trained neural network. When the neural network is trained, it has parameters that will use to predict the output when it receives a new input. 3. Running the trained neural network in a python script on the ADP3450 while running in Linux mode.

Our Data Acquisition Handbook is a great place to start. https://files.digilent.com/reference/data-acquisition-handbook.pdf