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  1. Today
  2. Hi, Vivadong69. Were you be able to resolve? Did USB cable change help?
  3. Yesterday
  4. My currently) favourite inexpensive prototyping FPGA board is the DE0 Nano with a Cyclone IV device and a 32 MB SDR SDRAM. It is a little better suited to this project because of the external memory size. I was able to use the same basic code that I used for the CMOD-A7 to test larger transactions. Performing a transaction uploading 2047 data sectors (4192256 payload bytes) to the DE0 Nano SDRAM and then downloading it resulted in no errors. I only have a measurement for the download; it averaged 42 MB/s. I hope to try out a test on the UP Squared board later this week and will report. I still haven't figured out why the Jetson Nano couldn't transfers data sectors reliably. It certainly isn't an issue of available memory.
  5. This request for help is duplicated at Xilinx forum. I started working with Xilinx Arty Z7-20 development board with Vivado 2019.1. I fail to open hardware target. The localhost is seen to be connected but Hardware Manager is said to be unconnected and after refreshing server I get the following: refresh_hw_server {localhost:3121} WARNING: [Labtoolstcl 44-27] No hardware targets exist on the server [localhost:3121] Check to make sure the cable targets connected to this machine are properly connected and powered up, then use the refresh_hw_server command to re-register the hardware targets. 1. I tried both “QSPI” and “JTAG” settings of JP4 jumper. In wain. 2. I learned from Xilinx and Digilent forums the possible culprit is poor cables drivers installation. I remember I included the cables drivers during initial installation. 3. I re-ran Vivado update without uninstall and included cable drivers again (checked their respective checkbox). But after second trial I saw they are again proposed to be installed – their checkbox is still unchecked. The hardware target wasn’t opened. 4. I followed the instructions in https://www.xilinx.com/support/answers/59128.html. I ran the cables driver installation batch file as administrator in Windows and it seemed to success. Log is attached. But in wain. The hardware target wasn’t opened. 5. Need to emphasize the cable I use to power up the board and to program it is the plainly usual USB A to micro B, wihch I connect to USB port of the board. From reading the Vivado programing and debugging ug908 document it could built up an impression that special supported JTAG cables are needed. But it would be too strange - the Arty Z7 board manual doesn't mention any need in a special cable and Digilent specifies this cable functionality is already built in into their boards. Please, help. install_drivers_wrapper.log
  6. Alexela

    Reprogramming Failure

    Hi I have a JTAG-SMT3-NC , Unfortunately I erase the eeprom on the board with FT_prog accidentally, And Now VIVADO can not find the FPGA, can anyone help me to reconfig the eeprom? Thanks
  7. @chcollin, I'm curious as to why a MicroBlaze was used for the EDID I2C connection. That seems like a rather heavy-hitting solution for a really simple interface. Are they doing more than just implementing the interface? Adjusting HDMI timing (pixel clock, screen size, etc.) for example? Or does the design use the same settings regardless? Just curious, Dan
  8. Hi FPGA gurus ! This might be my forever last question :D My project is complete, all bugs and customizations done. I wanted to get rid of the microblaze part but I realized I couldn't since HDMI In connector needs xps_iic and microblaze for the EDID thing. So, here is my question, as I didn't find any answer to it : How can I store the whole project into Atlys so that I don't need to download and run it from SDK every time ? Especially, the C program needs to be run on bootup so that EDID interrupts are handled. To resume : What's the process so that whenever I turn the Atlys on, my implementation and program run ? Can anybody help on this ? After 2 years I'm finally seeing the light at the end of the tunnel !! Many many thanks in advance. Cheers
  9. Hi @jpeyron, I can't see the article. Can you please link it again? Best regards, Toni
  10. Last week
  11. Hi, it seems I managed to erase the eeprom on my HS1 as well. 😱 Can you help me? Regards, Sabrina
  12. Everything for the Arty z7 seems to be 2 years old and will not work with any of the last two major releases from Xilinx. (SDSoc, Petalinux..etc). Do I understand this correctly after wasting two days trying to get something to work?
  13. Jon, Thanks for the reply. I am using the Digilent board files for my project. I am using the example Ethernet Echo Server that does work without my extra input on the interrupt controller. This is hooked to the 3rd input on that IP. The other two are as per the example which is the timer and the ethernet IP blocks interrupt. I've tried changing the Interrupt type from Level to Edge but get the same results. Thanks, Curt
  14. jpeyron

    JTAG-SMT2

    Hi @Wyorin, Since you are able to initialize the scan chain and configure the Spartan 6 i would first look into the Chipscope ILA. I have not used the Chipscope ILA in ISE. This AR looks to be helpful for trouble shooting the Chipscope. best regards, Jon
  15. Hi @Mats, We have reached out to a co-worker about this thread. best regards, Jon
  16. Hi @core2explore, If the board is physically connected to the PC through the USB UART bridge or the JTAG port then remote desktop should not be an issue. I use my work PC remotely and configure connected FPGA's occasionally. best regards, Jon
  17. Hi @birca123, This article breaks down the uart controller on the zynq processor for a different zynq fpga. I believe this information should be applicable here as well. best regards, Jon
  18. Azzor

    Vivado sysnthesis fail..Pcam

    Hi! I tried with another monitor... QSPI jumper option... is working I change the jumper to JTAG and I see 5 bars pink-green bars on the monitor But now i understand that the menu is frozen (the first one), i checked the code and it should change to submenus... Any ideas? thanks
  19. Hi @andylb, Welcome to the Digilent forums! Unfortunately, no work has been done on LINX since late 2016 and there are not any plans to update the LINX driver for Raspberry Pi at this time. best regards, Jon
  20. Hi @core2explore, Is your project currently working through JTAG with sdk pulling the data from a file stored in flash? Here is a forum thread that discusses reading from the QSPI FLASH. Here is a tutorial for configuring the QSPI FLASH from SDK with microblaze projects. I would suggest compressing the bitstream. best regards, Jon
  21. Hi Everyone! Any plans for a new version of LINX for the Raspberry Pi? Cheers, Andy.
  22. Hello, I am having a hard time using Labview to set up the digital output drive mode to be the same as push-pull mode within the Waveforms GUI. Seems like when using Labview, when an Analog Explorer 2 pin is initialized as an output, the output goes to high Z. I need it to go to 3.3V (or whatever the highest digital voltage is) or 0V when needed. Thanks for your help.
  23. Quad spi is working in normal mode for me.But my required data elf is of higher size.So I want to use XIP mode operation to bring this transfer much faster.Any one please give your valuable information here.
  24. Azzor

    Vivado sysnthesis fail..Pcam

    Hi! In the menu im choosing all the options, a led in the zybo flashes everytime i click a letter... but the monitor still says "mode not supported".. i'll try another monitor Thanks!
  25. Hi @stever You are probably getting this error from FDwfDigitalOutDataSet, which expects the countOfBits max 32768 with DD.
  26. Hi @tpaulin The Scope inputs on AD2 are protected for up to +/-50V.
  27. Hi @Jivoman The Scope inputs of AD2 have 2 gain steps about 5V and 50V. See the following script: AnalogIn_Range.py # DWF Version: b'3.11.14' dwf.FDwfAnalogInChannelRangeGet(hdwf, c_int(0), byref(vr1)) # Ch1 ~5/50V dwf.FDwfAnalogInChannelRangeGet(hdwf, c_int(1), byref(vr2)) # Ch2 ~5/50V print("Ch1: "+str(vr1.value)+" Ch2: "+str(vr2.value)) # Ch1: 60.70607306692946 Ch2: 60.86322581568005 dwf.FDwfAnalogInChannelRangeSet(hdwf, c_int(0), c_double(0.3)) # Ch1 dwf.FDwfAnalogInChannelRangeSet(hdwf, c_int(1), c_double(50.0)) # Ch2 dwf.FDwfAnalogInChannelRangeGet(hdwf, c_int(0), byref(vr1)) # Ch1 ~5/50V dwf.FDwfAnalogInChannelRangeGet(hdwf, c_int(1), byref(vr2)) # Ch2 ~5/50V print("Ch1: "+str(vr1.value)+" Ch2: "+str(vr2.value)) # Ch1: 5.518196625058977 Ch2: 60.86322581568005 dwf.FDwfAnalogInChannelRangeSet(hdwf, c_int(0), c_double(10.0)) # Ch1 dwf.FDwfAnalogInChannelRangeSet(hdwf, c_int(1), c_double(0.3)) # Ch2 dwf.FDwfAnalogInChannelRangeGet(hdwf, c_int(0), byref(vr1)) # Ch1 ~5/50V dwf.FDwfAnalogInChannelRangeGet(hdwf, c_int(1), byref(vr2)) # Ch2 ~5/50V print("Ch1: "+str(vr1.value)+" Ch2: "+str(vr2.value)) # Ch1: 60.70607306692946 Ch2: 5.536143355938114
  28. Was there any progress on this? I'm getting a warning and then errors building petalinux with 2017.4 using 2019.1 PetaSDK. I'm trying to avoid going back multiple years in the tool chain.. or something else is wrong? Related post of mine with screen dump:
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