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  2. Hi @osti I have added two frequency synthesizer modules in series for DD firmware/FPGA to able to generate fine resolution of frequencies. This adjusts the system frequency, applies for both Logic Analyzer and Pattern Generator. https://forum.digilentinc.com/topic/8908-waveforms-beta-download
  3. Hi @tdavismn Adding (n)V/vHz : https://forum.digilentinc.com/topic/8908-waveforms-beta-download/
  4. Hi @bixie const Index = 1 function dir(){ var now = new Date(), year = '' + (now.getFullYear()%2000), month = '' + (now.getMonth() + 1), day = '' + now.getDate(), hour = '' + now.getHours(); if (year.length < 2) year = '0' + year; if (month.length < 2) month = '0' + month; if (day.length < 2) day = '0' + day; if (hour.length < 2) hour = '0' + hour; var dirbase = "~/Desktop/SeeIfIWork/#"+day+month+year+"/#"+hour for(var i = 0; i < 1000; i++){ var dirname = dirbase; if(i!=0) dirname += " "+i; var test = File(dirname) var exists = test.exists(); delete test; if(!exists) return dirname; } return ""; } Impedance.single(); Impedance.wait(); var filename = dir()+"/Messung"+Index+".png"; print(filename); Impedance.Export(filename);
  5. Calculating data rates from clock frequencies for most PC interfaces is not as straight-forward as it might seem. For USB 2.0 the peak transfer rate might be 60 million bytes per second (about 57.22 MB/s) but you'll never achieve anything close to that as an average for any payload size. This is partly due to the nature of the USB protocol and OS overhead. Also, there are latency issues if you want to stream data at some minimal rate. If you look around I've been posting lately on a project to use inexpensive single-board computers with FPGA boards like the CMOD. At best I can get around 42 MB/s data rates; if you ignore OS overhead. And this is with an FTDI device using the fastest synchronous 245 FIFO mode. The Cypress USB interface that is on the Altas FPGA board is more capable than the FTDI devices and provides somewhat better average performance. For Ethernet there are the same OS latencies as well as packet format overhead so even 1G Ethernet is likely to provide at most around 30 MB/s data rates; unless you do something very creative. UART data rates are the easiest to quantify. They don't work on 8-bit words. At least you will have 1 start and 1 stop bit per baud; so actual data rates are at best 8/10th the raw bit rate. It is possible to stream data at a rate that meets your requirements using USB 3.0. If using Digilent boards you need to have a board with an FMC connector and add a USB mezzanine board with a USB 3.0 interface. Fortunately, FTDI and Cypress both offer inexpensive development boards that work with the Nexys Video or Genesys2. Unfortunately, these FPGA boards are in a different price range than the one the you have. Other vendors offer FPGA boards with a USB 3.0 interface such as Opal Kelly but again the price is usually much higher than Digilent boards and have a lot less in terms of interfaces.
  6. Hi @HoWei See the SDK/ samples/ py/ DigitalOut_BinrayCounter.py CustomBus.py examples I have replied to the clock question here:
  7. Hi @HoWei The WF application uses a kind of 'pulse' configuration to generate clock, like it is in the DigitalOut_Duty.py example See the SDK/ samples/ py/ DigitalOut_Duty.py Phase.py Pins.py Pulse.py iChannel = 0 hzFreq = 1000 # PWM freq Hz prcDuty = 1.23 # duty % hzSys = c_double() maxCnt = c_uint() dwf.FDwfDigitalOutInternalClockInfo(hdwf, byref(hzSys)) dwf.FDwfDigitalOutCounterInfo(hdwf, c_int(0), 0, byref(maxCnt)) # for low frequencies use divider as pre-scaler to satisfy counter limitation of 32k cDiv = int(math.ceil(hzSys.value/hzFreq/maxCnt.value)) # count steps to generate the given frequency cPulse = int(round(hzSys.value/hzFreq/cDiv)) # duty cHigh = int(cPulse*prcDuty/100) cLow = int(cPulse-cHigh) print("Generate: "+str(hzSys.value/cPulse/cDiv)+"Hz duty: "+str(100.0*cHigh/cPulse)+"% divider: "+str(cDiv)) dwf.FDwfDigitalOutEnableSet(hdwf, c_int(iChannel), c_int(1)) dwf.FDwfDigitalOutTypeSet(hdwf, c_int(iChannel), c_int(0)) # DwfDigitalOutTypePulse dwf.FDwfDigitalOutDividerSet(hdwf, c_int(iChannel), c_int(cDiv)) # max 2147483649, for counter limitation or custom sample rate dwf.FDwfDigitalOutCounterSet(hdwf, c_int(iChannel), c_int(cLow), c_int(cHigh)) # max 32768 dwf.FDwfDigitalOutConfigure(hdwf, c_int(1))
  8. Hi @JohnBee I'm not aware of AD3 or USB 3.1 plans. It won't be released such product in the near future.
  9. In the Waveforms GUI there is a pattern generation mode "clock", that allows to setup the output as clock. What would be the equivalent using the SDK (e.g. with python) ? Does "DwfDigitalOutTypeCustom" provide the "clock" function ? Also in Waveforms GUI there is an option to create a "bus" of signals - is there an equivalent in the SDK ?
  10. @saif91, I like your picture. You've picked a wonderful choice for many reasons. From your comments above, though, it sounds like you are stuck in FPGA Hell. Your biggest problem is not that you don't know where your bug is though, your biggest problem is in your design process. Desk-checking like this is really the wrong way to debug a design. Why so? Because with desk checking alone, you aren't guaranteed to ever find your bug. This was one of the reasons why I wrote my beginner's tutorial--to introduce a beginner to a better design process from the very first lesson. That said, I found the first bug in your design. This is what's known as a "Logic clock". You should never create "logic clocks" in your design. 1) the tools don't know how to handle them, 2) such clocks rarely get promoted to the global clocking network where they belong, 3) leading to subtle and uncontrolled timing violations within the design that the tools may (or may not) detect, and 4) it tends to hide/obscure clock-domain crossing issues. (Have you seen my list of "rules for beginning designers"? PROCESS (clk) BEGIN IF (clk'EVENT AND clk='1') THEN pixel_clk <= NOT pixel_clk; END IF; -- ... You really need to get this to work in a simulation first. Debugging is just *so* much easier in simulation. (It's even easier with formal methods ....) Dan
  11. Hi @jpeyron Like in this example https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/gpiops/examples/xgpiops_intr_example.c?_ga=2.11499126.33107880.1566472821-1015055952.1563367754 they are using input pin = 14 which I believe would be the pin connected to the swtich. How can I determine which mine would be connected to which MIO ? Regards, Hasan helloworld.c
  12. Seems like the correct command is #Set output mode to push pull dwf.FDwfDigitalOutOutputSet(hdwf, c_int(4), DwfDigitalOutOutputPushPull) I found it by luck in one of the forum discussions.
  13. Impedance1.Export("~/Desktop/SeeIfIWork/"#ddmmyy"/"#hh index"/Messung"+Index+".png")
  14. In the SDK manual (4th April 2019) on page 83 the command "FDwfDigitalOutModeSet" is mentioned. I did not find any documentation of this command in the docu, nor did I find any example using this command. I want to set the DIO output mode to "PP" - like I can do it within the Waveforms application. Can you please provide information how to do it - perferrably in python ?
  15. Hi @jpeyron I am still a bit unsure regarding using Vivado, so just to make sure my understanding is correct. If I want to use the GPIO on the PS (lets say IO35), how will I know which MIO pin is this connected to ? Also, the IOMODULE made will be using the IO hardware which is already on the Zynq or will this make an IP block on the fabric ? Regards, Hasan
  16. Hi @bixie Where do you want the hour to be ? Where do you want the '1,2,3' suffix to be ? In the directory or in the file name ?
  17. And if so, will it work on USB 3.1?
  18. Hi @attila Thanks a lot! I'm also a bit confused about this part, please help I want also a folder which has time specified in side the date folder, only showing what hour it is of that day 24 h format and if there's already an existing folder with that hour eg 12, then it should have something like "12 1"
  19. I am using a Windows 10 laptop to connect to a Raspberry PI 3 B+ (Raspbian OS) with LINX. I have managed to connect to the Target, but once connected, I try to install Labview but I always get the following message: " Installation failed. If this is the first time the installation has failed try again. If this error persists search, then post on the LabVIEW MakerHub forumsat labviewmakerhub.com/forums/linx. Target configuration updated." LOG: Connecting to target... Successfully connected to target. Successfully connected to the target. Target configuration updated. OS Version: 10.0 CPU: Systemd Version: Has Internet Access: True Device Type: Unknown Adding MakerHub feed... MakerHub Feed Already Exists Updating package index. This may take over 30 seconds depending on your internet speed... Ign:1 http://feeds.labviewmakerhub.com/debian binary/ InRelease Hit:2 http://archive.raspberrypi.org/debian buster InRelease Err:3 http://feeds.labviewmakerhub.com/debian binary/ Release 404 Not Found [IP: 54.86.245.246 80] Hit:4 http://raspbian.raspberrypi.org/raspbian buster InRelease Reading package lists... Installing LabVIEW... Reading package lists... Building dependency tree... Reading state information... Checking target status... Installation failed. If this is the first time the installation has failed try again. If this error persists search, then post on the LabVIEW MakerHub forumsat labviewmakerhub.com/forums/linx. Connecting to target... Can anyone please help? Any help is greatly appreciated.
  20. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; LIBRARY lpm; USE lpm.lpm_components.all; ---------------------------------------------------------- ENTITY vga IS GENERIC ( Ha: INTEGER := 96; --Hpulse Hb: INTEGER := 144; --Hpulse+HBP Hc: INTEGER := 784; --Hpulse+HBP+Hactive Hd: INTEGER := 800; --Hpulse+HBP+Hactive+HFP Va: INTEGER := 2; --Vpulse Vb: INTEGER := 35; --Vpulse+VBP Vc: INTEGER := 515; --Vpulse+VBP+Vactive vbp Vd: INTEGER := 525); --Vpulse+VBP+Vactive+VFP PORT ( clk: IN STD_LOGIC; --50MHz in our board red_switch, green_switch, blue_switch: IN STD_LOGIC; pixel_clk: BUFFER STD_LOGIC; Hsync, Vsync: BUFFER STD_LOGIC; R, G, B: OUT STD_LOGIC_VECTOR(9 DOWNTO 0); nblanck, nsync : OUT STD_LOGIC); END vga; ---------------------------------------------------------- ARCHITECTURE vga OF vga IS SIGNAL Hactive, Vactive, dena: STD_LOGIC; SIGNAL address: STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL intensity: STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL hPos: integer; SIGNAL vPos : integer; SIGNAL videoOn : STD_logic; constant picture_size : Integer:=9000; -------------------------------------------------------------- begin ------------------------------------------------------- --Part 1: CONTROL GENERATOR ------------------------------------------------------- -- --Static signals for DACs: nblanck <= '1'; --no direct blanking nsync <= '0'; --no sync on green --Create pixel clock (50MHz->25MHz): PROCESS (clk) BEGIN IF (clk'EVENT AND clk='1') THEN pixel_clk <= NOT pixel_clk; END IF; END PROCESS; --Horizontal signals generation: PROCESS (pixel_clk) VARIABLE Hcount: INTEGER RANGE 0 TO Hd; BEGIN IF (pixel_clk'EVENT AND pixel_clk='1') THEN Hcount := Hcount + 1; IF (Hcount=Ha) THEN Hsync <= '1'; ELSIF (Hcount=Hb) THEN Hactive <= '1'; ELSIF (Hcount=Hc) THEN Hactive <= '0'; ELSIF (Hcount=Hd) THEN Hsync <= '0'; Hcount := 0; END IF; END IF; END PROCESS; --Vertical signals generation: PROCESS (Hsync) VARIABLE Vcount: INTEGER RANGE 0 TO Vd; BEGIN IF (Hsync'EVENT AND Hsync='0') THEN Vcount := Vcount + 1; IF (Vcount=Va) THEN Vsync <= '1'; ELSIF (Vcount=Vb) THEN Vactive <= '1'; ELSIF (Vcount=Vc) THEN Vactive <= '0'; ELSIF (Vcount=Vd) THEN Vsync <= '0'; Vcount := 0; END IF; END IF; END PROCESS; -- ---Display enable generation: dena <= Hactive AND Vactive; ------------------------------------------------------- --ROM instantiation: myrom: lpm_rom GENERIC MAP ( lpm_widthad => 9, --address width lpm_outdata => "UNREGISTERED", lpm_address_control => "REGISTERED", lpm_file => "2colom", --data file lpm_width => 10) --data width PORT MAP ( inclock=>NOT pixel_clk, address=>address, q=>intensity); --Create address (row number): PROCESS (Vsync, Hsync) VARIABLE line_counter: INTEGER RANGE 0 TO Vd; VARIABLE line_counter2: INTEGER RANGE 0 TO Hc; BEGIN -- IF (Vsync='0') THEN -- line_counter := 0; -- ELSIF (Hsync'EVENT AND Hsync='1') THEN -- IF (Vactive='1') THEN -- line_counter := line_counter + 1; -- END IF; -- END IF; IF (Vsync='0') THEN line_counter := 0; ELSIF (Hsync'EVENT AND Hsync='1') THEN IF (Vactive='1') THEN line_counter := line_counter + 1; END IF; END IF; IF (Hsync='0') THEN line_counter2 := 0; ELSIF (pixel_clk'EVENT AND pixel_clk='1') THEN IF (Hactive='1') THEN line_counter2 := line_counter2 + 1; END IF; END IF; address <=conv_std_logic_vector(line_counter , 9); end process; -------- --Assign color values to R/G/B R<=intensity WHEN red_switch='1' AND dena='1' ELSE (OTHERS=>'0'); G<=intensity WHEN green_switch='1' AND dena='1' ELSE (OTHERS=>'0'); B<=intensity WHEN blue_switch='1' AND dena='1' ELSE (OTHERS=>'0'); ------ END vga; now am doing simple display image i save at rom as .mif to display to VGA and use clock 24 mhz but image not display not clear ?
  21. D@n thanks a lot Take advantage of your comment and your tutorials
  22. Managed to connect the laptop (windows 10) using LINX to the Raspberry PI 3B+ (Raspbian), but whenever I try to install Labview (2014 Home edition) to it, it fails. Worse, the Raspberry PI's also looses its ability to connect the internet with the WiFi Lan and cannot set it up, having to re-install the Raspbian again. Any help is GREATLY appreciated.
  23. Hello all, I've been searching about this a lot, but could not find information all at one place. So I am creating this thread. I am currently using Spartan XC3S50A in Master SPI mode, that is connected to AT45DB021D SPI flash. I have iMPACT 11.1 installed through which I perform direct SPI programming. I am recently out for testing JTAG-HS2 for this very purpose, but iMPACT 11.1 does not shows up JTAG-HS2 cable in cable setup options. I followed the manual that comes with Digilent plugin and have copied the DLL and XML files into the folder specified, but still no luck. Unfortunately, this manual only documents complete procedure for adding cable to ChipScope, but not iMPACT 11.x. Even the digilent adept 2 does not give me option for direct SPI programming. The GUI only has two tabs named config and settings. Am I missing on any of the steps or am I not using proper software versions? I am stuck. Any step by step instructions would prove very useful for me. Thank you in advance!
  24. Yesterday
  25. tgvho

    JTAG-SMT3-NC UART usage

    I'm concidering adding a JTAG-SMT3-NC to my next design so I can have access to both the UART and the JTAG interface. Hoever, it is not clear how to use the UART. I've read over the ADAPT2 API and the SMT3 documentation pages, but it's not very clear to me. So, What drivers are needed? Does the device enumerate itself as a serial device so that it can be used with standard OS serial device utilities (I'm guessing a virtual com port driver)? How does one set the baud rate? For example, if I want to use this as a data dump debugger at the megabuad rate, how would I go about enumerating the serial device?
  26. Hi @RFtmi, Under the release tab here download the zip and open in the version listed, with projects version matters. best regards, Jon
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