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  1. Yesterday
  2. Hi, I'm trying to reproduce tutorial Nexys 4 DDR - Getting Started with Microblaze Servers for my Nexys A7. I have included the Nexys A7 board definitions in the Vivado. When I try the Generate Bitstream, so I receive these error messages: Implementation -> Write Bitstream -> DRC -> Pin Planning: [DRC NSTD-1] Unspecified I/O Standard: 15 out of 71 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: mii_rtl_rxd[3:0], mii_rtl_txd[3:0], mii_rtl_crs, mii_rtl_rst_n, mii_rtl_rx_clk, mii_rtl_rx_dv, mii_rtl_rx_er, mii_rtl_tx_clk, and mii_rtl_tx_en. [DRC UCIO-1] Unconstrained Logical Port: 15 out of 71 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: mii_rtl_rxd[3:0], mii_rtl_txd[3:0], mii_rtl_crs, mii_rtl_rst_n, mii_rtl_rx_clk, mii_rtl_rx_dv, mii_rtl_rx_er, mii_rtl_tx_clk, and mii_rtl_tx_en. They are ok board pinout definitions? How to correctly fix this problem?
  3. Last week
  4. Hi, >> So can any be give me suggestions how i can correct the debounce concept in the code. regular solution: count consecutive, identical input states and reset the counter on change of input state. Signal change of output state when counter reaches predetermined value. sneaky / suboptimal solution: sample the switch on a 100 Hz grid. I have to keep reminding myself that there is nothing inherently wrong with VHDL ... in Verilog, the whole task could be solved cleanly in one screen length of code, give or take some.
  5. I am completly new for the FPGA and basys3 development board. I have a project for Counter on the 7 segment displays on the board. We got 3 different layers as a design. cntr cntr_rtl cntr_top cntr_top_struc io_ctrl io_ctrl_rtl And in the project it has to diplay on the 7 segment controlled by the switches : count up / count down / hold / reset options: The priorities for these switches are: 1. reset 2. hold 3. count direction top level VHDL file cntr_top.vhd Port Name Direction Description clk_i In System clock (100 MHz) reset_i In Asynchronous high active reset sw_i(15:0) In 16 switches pb_i(3:0) In 4 buttons ss_o(7:0) Out Contain the value for all 7-segment digits ss_sel_o(3:0) Out Select a 7-segment digit io_ctrl clk_i In System clock (100 MHz) reset_i In Asynchronous high active reset cntr0_i(n:0) In Digit 0 (from internal logic) cntr1_i(n:0) In Digit 1 (from internal logic) cntr2_i(n:0) In Digit 2 (from internal logic) cntr3_i(n:0) In Digit 3 (from internal logic) sw_i(15:0) In 16 switches (from FPGA board) pb_i(3:0) In 4 buttons (from FPGA board) ss_o(7:0) Out to 7-segment displays of the FPGA board ss_sel_o(3:0) Out Selection of a 7-segment digit swclean_o(15:0) Out 16 switches (to internal logic) pbclean_o(3:0) Out 4 buttons (to internal logic) cntr.vhd clk_i In System clock (100 MHz) reset_i In Asynchronous high active reset cntrup_i In Counts up if signal is ‘1’ cntrdown_i In Counts down if signal is ‘1’ cntrreset_i In Sets counter to 0x0 if signal is ‘1’ cntrhold_i In Holds count value if signal is ‘1’ cntr0_o(n:0) Out Digit 0 (from internal logic) cntr1_o(n:0) Out Digit 1 (from internal logic) cntr2_o(n:0) Out Digit 2 (from internal logic) cntr3_o(n:0) Out Digit 3 (from internal logic) I will attach also the file to the attachment. Now my code is working and do all the funcitionality correct but there is only one issue which is the DEBOUNCE code part. I didnt use the clk signal for the code and i have to change it. The certain given clock signal has to be used. So can any be give me suggestions how i can correct the debounce concept in the code. io_ctrl_rtl.vhd -code down below: library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; architecture rtl of io_ctrl is constant COUNTVALUE : std_logic_vector(16 downto 0):= "01100001101010000"; signal s_enctr : std_logic_vector(16 downto 0):="00000000000000000"; signal s_2khzen : std_logic :='0'; signal s_1hzen : std_logic :='0'; signal s_2khzcount : std_logic_vector(3 downto 0) := "0000"; signal swsync0 : std_logic_vector(15 downto 0):="0000000000000000"; signal pbsync0 : std_logic_vector(3 downto 0):="0000"; signal swsync1 : std_logic_vector(15 downto 0):="0000000000000000"; signal pbsync1 : std_logic_vector(3 downto 0):="0000"; signal swtmp : std_logic_vector(15 downto 0):="0000000000000000"; signal pbtmp : std_logic_vector(3 downto 0):="0000"; signal swdebounced : std_logic_vector(15 downto 0):="0000000000000000"; signal pbdebounced : std_logic_vector(3 downto 0):="0000"; signal s_ss_sel : std_logic_vector(3 downto 0) := "0000"; signal s_ss : std_logic_vector(7 downto 0) := "00000000"; begin -- rtl ----------------------------------------------------------------------------- -- -- Synchronize the inputs -- ----------------------------------------------------------------------------- p_sync: process (clk_i, reset_i) begin if reset_i = '1' then swsync0 <= (others => '0'); pbsync0 <= (others => '0'); swsync1 <= (others => '0'); pbsync1 <= (others => '0'); elsif clk_i'event and clk_i = '1' then swsync0 <= sw_i; pbsync0 <= pb_i; swsync1 <= swsync0; pbsync1 <= pbsync0; else null; end if; end process; ----------------------------------------------------------------------------- -- -- Generate 1 KHz enable signal. -- ----------------------------------------------------------------------------- p_slowen: process (clk_i, reset_i) begin if reset_i = '1' then s_enctr <= (others => '0'); s_2khzen <= '0'; elsif clk_i'event and clk_i = '1' then if s_enctr = COUNTVALUE then -- When the terminal counter is reached, set the release flag and reset the counter s_enctr <= (others => '0'); s_2khzen <= '1'; s_2khzcount <= std_logic_vector(to_unsigned(to_integer(unsigned( s_2khzcount )) + 1, 4)); else s_enctr <= std_logic_vector(to_unsigned(to_integer(unsigned( s_enctr )) + 1, 17)); -- As long as the terminal count is not reached: increment the counter. if s_2khzen = '1' then s_2khzen <= '0'; end if; end if; if s_2khzcount = "1010" then s_1hzen <= not s_1hzen; s_2khzcount <= "0000"; end if; end if; end process p_slowen; ----------------------------------------------------------------------------- -- -- Debounce buttons and switches -- ----------------------------------------------------------------------------- p_debounce: process (s_1hzen, reset_i) variable dbouncecntr : integer:=0; begin if reset_i = '1' then swdebounced <= "0000000000000000"; pbdebounced <= "0000"; dbouncecntr :=0; -- Change clocking the process with signal from sens list. else if (dbouncecntr = 0) then swtmp <= swsync1; pbtmp <= pbsync1; dbouncecntr := dbouncecntr + 1; elsif (dbouncecntr = 1) then if (swtmp = swsync1) then swdebounced <= swsync1; end if; if (pbtmp = pbsync1) then pbdebounced <= pbsync1; end if; dbouncecntr := 0; end if; end if; end process p_debounce; swclean_o <= swdebounced; pbclean_o <= pbdebounced; ----------------------------------------------------------------------------- -- -- Display controller for the 7-segment display -- ----------------------------------------------------------------------------- p_displaycontrol: process (clk_i, reset_i) variable v_scancnt : std_logic_vector(1 downto 0):= "00"; variable v_output : std_logic_vector(3 downto 0):="0000"; begin if reset_i = '1' then v_scancnt := "00"; s_ss <= "00000000"; elsif clk_i'event and clk_i = '1' then if s_2khzen = '1' then case v_scancnt is when "00" => v_output := cntr0_i; s_ss_sel <= "0001"; when "01" => v_output := cntr1_i; s_ss_sel <= "0010"; when "10" => v_output := cntr2_i; s_ss_sel <= "0100"; when "11" => v_output := cntr3_i; s_ss_sel <= "1000"; when others => v_output := "1111"; s_ss_sel <= "0001"; end case; case v_output is --ABCDEFG, when "0000" => s_ss <= "11111100"; --0 when "0001" => s_ss <= "01100000"; --1 when "0010" => s_ss <= "11011010"; --2 when "0011" => s_ss <= "11110010"; --3 when "0100" => s_ss <= "01100110"; --4 when "0101" => s_ss <= "10110110"; --5 when "0110" => s_ss <= "10111110"; --6 when "0111" => s_ss <= "11100000"; --7 when "1000" => s_ss <= "11111110"; --8 when "1001" => s_ss <= "11110110"; --9 when others => s_ss <= v_scancnt & "000000"; end case; if v_scancnt = "11" then v_scancnt := "00"; else v_scancnt := std_logic_vector(to_unsigned(to_integer(unsigned( v_scancnt )) + 1, 2)); end if; else null; end if; else null; end if; end process p_displaycontrol; ss_o <= not s_ss; ss_sel_o <= not s_ss_sel; end rtl; The code for : cntr_top_struc.vhd library IEEE; use IEEE.std_logic_1164.all; architecture rtl of cntr_top is component cntr -- component of cntr port (clk_i: in std_logic; -- 100 MHz system clock reset_i: in std_logic; -- async high active reset cntrup_i : in std_logic; --counts up if signal is '1' cntrdown_i : in std_logic; --counts down if signal is '1' cntrreset_i : in std_logic; --sets counter to 0x0 if signal is '1' cntrhold_i : in std_logic; --holds count value if signal is '1' cntr0_o: out std_logic_vector(3 downto 0); -- Digit 0 (from internal logic) cntr1_o: out std_logic_vector(3 downto 0); -- Digit 1 (from internal logic) cntr2_o: out std_logic_vector(3 downto 0); -- Digit 2 (from internal logic) cntr3_o: out std_logic_vector(3 downto 0)); -- Digit 3 (from internal logic) end component; component io_ctrl ---- component io_crtl port (clk_i: in std_logic; -- 100 MHz system clock reset_i: in std_logic; -- async high active reset cntr0_i: in std_logic_vector(3 downto 0); -- Digit 0 (from internal logic) cntr1_i: in std_logic_vector(3 downto 0); -- Digit 1 (from internal logic) cntr2_i: in std_logic_vector(3 downto 0); -- Digit 2 (from internal logic) cntr3_i: in std_logic_vector(3 downto 0); -- Digit 3 (from internal logic) swclean_o: out std_logic_vector(15 downto 0); pbclean_o: out std_logic_vector(3 downto 0); ss_o: out std_logic_vector(7 downto 0); -- Contain the Value for All 7-Segment Digits ss_sel_o: out std_logic_vector(3 downto 0); -- Select a 7-segment digits pb_i: in std_logic_vector(3 downto 0); --4 Buttons sw_i: in std_logic_vector(15 downto 0) ); --16 Switches end component; -- Declare the signals that are used to connect the submodules. signal s_cntr0 : std_logic_vector(3 downto 0); signal s_cntr1 : std_logic_vector(3 downto 0); signal s_cntr2 : std_logic_vector(3 downto 0); signal s_cntr3 : std_logic_vector(3 downto 0); signal s_cntrup : std_logic; signal s_cntrdown : std_logic; signal s_cntrreset : std_logic; signal s_cntrhold : std_logic; signal s_overflow : std_logic_vector(11 downto 0); begin --Instantiate the counter that is connected to the IO-Control i_cntr_top1 : cntr port map (clk_i => clk_i, reset_i => reset_i, -- cntrdir_i => s_cntrdir, --swsync_o(13); cntrup_i => s_cntrup, --swsync_o(13); cntrdown_i => s_cntrdown, --swsync_o(12); cntrreset_i => s_cntrreset, --swsync_o(15), cntrhold_i => s_cntrhold, --swsync_o(14), cntr0_o => s_cntr0, cntr1_o => s_cntr1, cntr2_o => s_cntr2, cntr3_o => s_cntr3); --Instantiate the IO control to which it is connected i_io_ctrl : io_ctrl port map (clk_i => clk_i, reset_i => reset_i, swclean_o(12) => s_cntrdown, swclean_o(13) => s_cntrup, swclean_o(15) => s_cntrreset, swclean_o(14) => s_cntrhold, swclean_o(11 downto 0) => s_overflow(11 downto 0), cntr0_i => s_cntr0, cntr1_i => s_cntr1, cntr2_i => s_cntr2, cntr3_i => s_cntr3, ss_o => ss_o, ss_sel_o => ss_sel_o, sw_i => sw_i, pb_i => pb_i); end rtl; Please waiting for your suggestions. Any help would be great appricated thanks for all. here down below example for debounce but couldnt find to way to implement. ----------------------------------------------------------------------------- -- -- Debounce buttons and switches -- ----------------------------------------------------------------------------- p_debounce: process (clk_i, reset_i) begin -- process debounce if reset_i = '1' then -- asynchronous reset (active high) elsif clk_i'event and clk_i = '1' then -- rising clock edge end if; end process p_debounce; swsync_o <= swsync; pbsync_o <= pbsync; ------------------------------------------------------------ Final Project-Decimal Count -1Hz.rar
  6. Update 3 - Major step in progression ! I finally ended up programming the SPI Flash I can confirm the Flash is correctly written. Jumper 11 was removed from the Atlys board so I turned it off and on again. I can tell the Atlys does boot on the Flash and load things to memory. The hardware implementation does start (my design uses LEDs and I can see them turning on). However, it seems like the software part doesn't start. The microblaze program doesn't seem to be started (it is supposed to send EDID information to the connected HDMI input device). Unfortunately, I couldn't find a way to get Bootloader outputs, this might give me hints on what's going on. For some unknown reason, when I plug Atlys' jtag cable to my host USB port and turn the board on, no /dev/ttyUSB0 appears. There must be something wrong with my installation although SDK and IMPACT have no problem programming the board. My System configuration is as follows : Centos 6 x86_64 libusb1-1.0.9-0.7.rc1.el6.x86_64 digilent.adept.runtime_2.13.1-x86_64 ftdi.drivers_1.0.4-x86_64 libCseDigilent_2.4.4-x86_64 [root@localhost share]# dadutil showinfo -d Atlys Product Name: Atlys User Name: Atlys Serial Number: 210178457950 Product ID: 00C0010C Firmware Version: 0303 Device Transport Type: 00010001 (USB) Device Capabilities: 0000000D DJTG - JTAG scan chain access DEPP - Asynchronous Parallel Input/Output DSTM - Streaming Synchronous Parallel Input/Output Yet, no /dev/ttyUSB0 shows up so I don't know how to connect to JTAG to get bootloader outputs... 😢 Does anybody have any suggestion ? This would be convenient to read bootloader output, it might point me out what's wrong with loading/starting the microblaze application. Cheers
  7. Hi @JohnA., The PS_SRST_B is available on the JTAG header on pin 14; there is a reference image showing where it is on the Xilinx JTAG header on the JTAG HS3 reference manual here: https://reference.digilentinc.com/jtag_hs3/refmanual#xilinx_zynq-7000_and_soc_support. I think for the jumpers you will need to change MIO2, as per the the Zedboard User Guide (pg 28) the current setting puts it in Independent JTAG mode which as per AR# 47599 from Xilinx the PS on a Zynq chip cannot be accessed through the ARM DAP which is affected by the CES chip versions. Could you try setting this value to be in Cascaded JTAG (settings the signal to ground)? Thanks, JColvin
  8. Hi, you can search for the keyword "blocking" vs "non-blocking" assignment in Verilog. You can get a hint at the answer (also the "always @(posedge clk) if you look at the schematic in your post. Note the triangle, "C" is an edge sensitive input (which goes down to the transistor level electronics that ultimately define the foundations of "synchronous" logic design as we know it). This only as sneak preview to what a web search will reveal 🙂
  9. Hi JColvin, The company I work for, ASSET-InterTech, is in the business of Boundary Scan software and hardware for testing boards and ICs. We interface with devices through their JTAG ports. I think the debugger being in the boundary scan chain is definitely an element. I am not sure if we could reach the PS_SRST_B signal, unless it is reachable through the JTAG chain somehow. According to the documentation that came with the ZedBoard, it's version 1.1 with the XC7Z020-1CSG484CES FPGA. I've attached images showing my board setup and the positions of the jumpers--it's the configuration I use that enables me to get the FPGA loaded. And, just to be sure, its the software I was wandering if could be loaded and booted via the PS UART. But loading it and booting it from QSPI, or SD card would do just as well.
  10. Hi @JohnA., I don't have ISE available to directly test this (since I'm on Windows 10), but on Vivado and SDK, I was able to to successfully load the .bit file and the application project launched. If I have a second USB cable attached to the PROG port (J17), then I am not able to readily choose to load the application. I don't know what tool you are using to load the file via the standard JTAG board, but do you happen to know if the tool you are using as the capability to drive the PS_SRST_B low? Xilinx tools occasionally require the processor core to be reset during debug operations (of which launching on hardware (system debugger)). As an additional question, what version of the Zedboard do you have and how are the mode jumpers configured on it (I realize you tried a number of options already, but in the interest of being on the same page. I do not think there is a way to load it through the UART USB as it is not connected to the necessary programming lines. Thanks, JColvin
  11. I'd like to use a ubuntu-based rootfs on top of a petalinux boot partition. If I do this, where can I find the kernel header files for the petalinux kernel so that I can compile drivers on the board?
  12. Hi, I try to learn verilog. There are a few things I don't understand about the following code(2., which is long.). I would appreciate if you help. Not: I'm a vhdl user 1-)What is the purpose of the always block used here? 2-) "assign count_next = count_reg + 1; // increase the count " how work this piece of code? Isn't it expected to grow rapidly by adding one? without stopping. How and when does count_next and count_reg get the new value? 3-)I would write something like this; // this is my code module counter (clk, reset, count); input clk, reset; output [3:0] count; reg [3:0] count; always @(posedge clk or posedge reset ) if (reset) count <= 4'b0000; else count <= count + 1'b1; endmodule ----------------------------------------------- module binaryCounter #( parameter N = 3 //N bit binary counter ) ( input wire clk, reset, output wire complete_tick, output wire[N-1:0] count ); localparam MAX_COUNT = 2**N-1; // maximum value for N-bit reg[N-1:0] count_reg; wire[N-1:0] count_next; always @(posedge clk, posedge reset) begin if (reset == 1) count_reg <= 0; // set count to 0 if reset else count_reg <= count_next; // assign next value of count end assign count_next = count_reg + 1; // increase the count // generate tick on each maximum count assign complete_tick = (count_reg == MAX_COUNT) ? 1 : 0; assign count = count_reg; // assign value to output port endmodule
  13. I purchased a HS2 JTAG programmer to replace a Xilinx programmer whose software is not going to be updated to support the XC3S50AN on Windows 10. This FPGA reads its program from internal flash memory on power up and starts running it. When I use the HS2 to program it using the software I downloaded here https://store.digilentinc.com/digilent-adept-2-download-only/ it appears to load the BIT file into the FPGA, but it does not appear to be able to program the BIT file into internal flash memory like Impact does. How do I program FPGA's internal flash memory?
  14. Hi @NicoloR, I personally haven't seen this error before and it looks you've tried all of things I would typically recommend (and you didn't directly say it, but I presume you only have the Analog Discovery 2 connected to your PC while trying to get it to work again). @attila, do you have a suggestion for what else they might try? Thanks, JColvin
  15. zbd

    HDMI demo design for Zybo Z7-20

    Thank you! @JColvin
  16. You're welcome @snes369, anytime! Do not hesitate to post again on the forums if you need any help. We are happy do to so. AndrewHolzer
  17. Hello everyone, after months of perfect operation, the Analog Discovery 2 I am using now behaves like this. When I start WaveForms I see the usual opening device window. But after this window I get the following error message. Up to now, to solve this problem, I have already attempted: - changing USB ports; - changing USB cables; - changing PC and operating system (tried Win10 Pro and WinXP Pro SP3); - adding an external power supply; - restarting PCs; - reinstalling WaveForms (I am currently using version 3.12.2); - force programming, from the Device Manager, each of the available channel configurations; but I didn't succeed. Do you have any further suggestion? Thank you very much!
  18. Hi @Robert Craven, For the Pynq-Z1, you can also use IO26-IO41 as digital output (or input) pins; there is an image showing where these pins are located on the Pynq Z1 in it's Reference Manual here: https://reference.digilentinc.com/reference/programmable-logic/pynq-z1/reference-manual#arduinochipkit_shield_connector. Let me know if you have any other questions about this. Thanks, JColvin
  19. I'm glad you found out what the problem was; thank you for sharing what you found!
  20. Hi JColvin, Thanks for the prompt reply. We have a software tool to load the SVF into the FPGA by way of the standard JTAG port. What's got me tripped up is, after I get the FPGA loaded, I can't figure out how to get the software loaded and booted. Attempts to do so by way of the QSPI and the the USB JTAG produce an error that I believe comes down to the fact that I am using the standard JTAG port to load with the FPGA. I have attached the error message I receive. I've experimented with moving jumpers and even disconnecting the JTAG cable after I load the FPGA, but I haven't found the right solution. Is there a way to load the software through the PC UART USB? Thanks! ErrorMessage.docx
  21. Thanks! I will only have one digital output line on at a time (sequenced through quickly) so I think the power requirements will be easy to meet. I see lines associated with sockets on the PYNQ Shield marked d0-D13 for 14 output lines, but am not sure what other lines can be used for digital outputs to make up the 20? I'm scared that some are dedicated to analog I/O? If not, which ones can be used for digital outputs? Thanks
  22. Hi. I'm a new user, my objective is to sample more than the two channel scope by multiplexing the input with external multiplexer drive'd by two digital output of the device. Actually the question's is how i can save the digital input/output in the same record logged? Thanks. Alberto.
  23. Hi I am working on HDMI pass through example from Digilent work shop manual i connected as shown in manual but getting error showimg [BD 41-237] Bus Interface property FREQ_HZ does not match between /v_axi4s_vid_out_0/video_in(100000000) and /v_vid_in_axi4s_0/video_out(200000000) can any one please help in in solving the issue clk out_1 is set to 200Mhz after going through the Xlinx Forum if AXi is made external then its frequency goes to 100Mhz, But how to change i dont know ...
  24. Hello JColvin, thank you for reply. While I writing a long answer I discovered the cause of the problem I have connected the Nexys A7 board by USB cable, but in another USB port I have connected (unused) Xilinx USB cable. When I connecting to FPGA (bitstream upload), so Vivado and SDK using USB cable and all works fine. When the System debugger is started, so unused Xilinx USB cable is discovered and debugger is crashed. I disconnected the Xilinx USB cable from the PC and the big problem is solved Yet thank you again for your answer. Regards, Michal
  25. @D@n I am sorry! The frequency is 50 kHz. My FFT resolution would be (100*10^6)/4096 about 24.5 kHz. X[3] would be the frequency bin with spike.
  26. Oh ok thanks. So the FFT isnt actually computed on the Analog Discovery itself?
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