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  1. Past hour
  2. Digilent Pmod IA impedance analyzer

    Hi @sebastiansuresh, Yes, you can connect the pmod IA to an arduino. We haven't had time to make a library for the Pmod IA. Here is a forum thread that has a link to a Raspberry pi project using the PmodIA. thank you, Jon
  3. Engineer

    Hi @cucchi, We do not provide the Altium files for the Arty board. Here is the resource center for the Arty board which has the schematic, xdc,3D CAD files, reference manual, demo's, tutorials and projects. thank you, Jon
  4. Digilent Pmod IA impedance analyzer

    Hello I want to purchase a PmodIA board for some impedance analysis on batteries. I was wondering if I could connect the Pmod IA to an arduino to carry out the testing. Thank-you
  5. Today
  6. Pynq board/ Disconnection from Jupyter

    Hi @tunghn1, Unfortunately, the Digilent engineers here on the Forum do not have a lot of experience with using the Pynq board and Jupyter notebook. The engineers on the Pynq support forum will be better able to answer your question. Thanks, JColvin
  7. disconnect_hw_server and connect_hw_server commands

    Hi @anurag, When the Cmod A7 is connected please attach a screen shot of the device manage under ports and universal serial bus controller? Did you download Adept 2? Does Adept 2 recognize the Cmod A7? thank you, Jon
  8. Basys2

    Hi @UOB, I found a number of different web pages that discuss this or something similar (1, 2, 3, 4, 5, 6), but the general consensus that I have seen is that there is not an alternative tool paid or otherwise that will do all of the implementation and routing for the FPGA and then generate a bitstream that can be loaded onto the FPGA, much as I would like to say that I'm aware of one. A number of synthesis tools do exist, but that isn't the same as loading the project onto the FPGA. I believe there are a couple of non-Xilinx FPGAs with some open source tools (I think it's called Project IceStorm), but I'm not familiar with the tools or the FPGA itself to be able to offer much input on it. Thanks, JColvin
  9. Engineer

    Hi, Is it possible to get the board layers in Altium for Part Number 410-319 Arty board?
  10. DjtgEnable and DjtgDisable take a long time to complete

    Hi @Jim H, I reached out to one of our design engineers about this forum and they responded with: "I’m somewhat surprised that it takes longer to perform a disable call than an enable call, but that could be the result of flushing a PC side buffer and waiting for synchronization with the USB device. I’m not really surprised that enable is somewhat slow. Each time the port gets enabled we have to make and sure the PC side and the serialization engine on the device side are in sync. If they aren’t in sync then we have to perform a bunch of extra steps. What would be interesting to see is how long it takes to perform the enable operation the first time, disable the port while keeping the application open, and then re-enable it again in the same application. I’d expect it to be considerably faster the second time through than it is the first time because we should be skipping some initialization steps. In any case I don’t think there’s a lot that we can do to speed it up. Interleaving access this way is going to be slow. If you truly need to interleave access between multiple applications then I think the only way to get good performance is design your application following a client/server model and have the server manage access to the HS2. The server can enable the port and keep it enabled and then provide interleaved/serialized access for the clients. I do find it very interesting that dpcutil is faster since it’s simply a wrapper dll that makes calls into dmgr and djtg. However, now that I read the post again they say “old Digilent cable” which I think means the original JTAG USB Cable. If that’s the case, then sure it makes sense. The old cable has a different USB controller and a completely different host side USB driver than the HS2. The USB protocol is completely different. Unfortunately there is no way to make the HS2 work the same way as the older cables when it comes to enable and disable." thank you, Jon
  11. Analog Discovery troubleshooting

    thanks @JColvin - I read that as "no desoldering components or warranty is void" What I was experiencing was nothing. Waveforms didn't see the device, neither did 'lsusb' nor 'dmesg' (running on Linux). Tried with several USB ports and cables, on two computers. Nothing. I found an external power supply, and powering the AD2 from that it seems to work again. So probably some protection ferrites/diodes/fuses were blown as attila suggested above? I'd really wouldn't want to ship the device back for maintenance - an external power supply is just a minor inconvenience. But I'd hate to burn something more unrepairable than ferrites/diodes if I use the device with external power supply, and the same thing that caused this occurs again. So any info on what to replace and with what sort of components would be appreciated. Even if it voids warranty Oh, and everything in my setup was powered from just one extension cord (i.e. computer and target power supply). So that should not be the cause for this failure. Unless my laptop docking station (Dell TB16) does something clever with isolating the USB lines... thanks, kalle
  12. Zybo Z7 SDSoC platform?

    Hey thanks for the quick reply. I have the Zybo-Z7-20 model
  13. Nexys2 Cypress eeprom iic file request

    Hi @rsip, I am tagging the engineer that handles EEPROM issues( @Bianca). thank you, Jon
  14. Zybo Z7 SDSoC platform?

    Hi @royal55flush, We do not as of yet have an SDSoC platform or an ETA for either of the Zybo Z7 boards. What version of the Zybo Z7 do you have, the Zybo-Z7-20 or the Zybo-Z7-10? thank you, Jon
  15. Zybo Z7 SDSoC platform?

    Hey, I just got my new Zybo today with the camera kit and SDSoC voucher. I got everytthing set up, but I couldn't find the right SDSoC platform files. maybe someone can point me in the right direction? I did see there were some platform files for older versions of SDx & one for the Arty Z7. I don't need any peripherals for the project I'm working on, just terminal access and computing. Will the Arty one suffice for my needs? Any help would be great thank you.
  16. Usign multiple PmodACL with Zedboard by SPI

    Hi @rockxito32, The process is very similar to this forum thread. You will need to instantiate multiple structs. Something like: PmodACL acl; PmodACL acl1; In the DemoInitialize() function you will need to call the functions twice. So for example ACL_begin twice one for acl and one for acl1 thank you, Jon
  17. I am using the Digilent HS2 cable on a Windows10 machine, using dmgr.dll and djtg.dll. I am able to call DmgrOpen and DjtgEnable to initialize my JTAG. I can then perform reads and writes to my FPGA without issues. But since we have multiple programs accessing the same JTAG port, I need to call DjtgEnable before each read, and DjtgDisable after each read. This works fine except it takes a long time to complete the enable and disable calls (rough measurements show 63 msec for the enable, and 140 msec for the disable). Switching to the old Digilent cable and drivers (dpcutils.dll) shows a much faster completion rate. Any ideas?
  18. Usign multiple PmodACL with Zedboard by SPI

    Hi everyone, In this opportunity I want to establish a SPI communication between two PmodACL and a Zedboard, in Vivado software I done it this way: And I got the Bitstream file without any mistake. But how can I do the SDK configuration for read two PmodACL at the same time?
  19. As far as I remember correctly, you need to program PL through SDK in Zynq
  20. GPIO[41:26]

    Hello, I am trying to drive GPIO's 41 to 26, any of them, having trouble understanding what channels are how they correspond to the banks on the schematic and how to configure them in hardware, when I try to drive them via the following api's: int Status; //Inst. GPIO to be output high Status = XGpio_Initialize(&GpioOutput, XPAR_AXI_GPIO_0_DEVICE_ID); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* Set the direction for all signals to be outputs */ XGpio_SetDataDirection(&GpioOutput, 1, 0x0); /* Set the GPIO outputs to high */ XGpio_DiscreteWrite(&GpioOutput, 1, 0x0); I cant find the output. I feel that I'm not initializing the correct ones. I am using Arty7-35t, Vivado 2016.4. Ive had an with the SPI constraints in that I had to assign the MOSI,MISO,SCK,SSn[0:0] pins manually in the same constraints file that i generated to drive the Eth PHY clock. Should i do the same for these pins?
  21. Physical connection to breadboard.jpg

    That's a good looking right angle header
  22. Hello from Lithuania:)

    Hi @Ignacas, Welcome to our Forums!
  23. Analog Discovery troubleshooting

    Hi @kraiskil, You can take out the screws and remove the frame without voiding the warranty (though I guess if you physically break the case that'll be a different story ). What are you experiencing specifically with the AD2? Is it detected by the WaveForms software? What do you see in the device manager (if you are using a Windows based device) when you connect/disconnect the AD2 from your computer? Thank you, JColvin
  24. FPGA, ADC and DAC

    @Ignacas Your project idea sounds nifty to me. I like the idea of using parts from a drawer; this could be challenging or at least very interesting for experienced engineers. I like your idea of using separate audio DAC and audio ADC devices from a project perspective ( not necessarily from an audio perspective ). I assume that you will be breadboarding your FPGA interface through the Arty regular PMOD. For best results you will have to pay attention to how this is accomplished. I suggest that you visit the Cirrus Logic website for application notes on this. Other audio IC vendors will have good guidance as well. As Cirrus Logic evaluation boards are priced to exclude the hobbyist element I assume that you will be breadboarding discrete chips. I'd make my own evaluation board using something like Express PCB. You may find this to be more expensive than you plan unless your parts drawer is stuffed with a lot of parts as buying small quantities of passive components isn't cost effective. As far as clocking goes, you have already discovered that getting precise clock frequencies from an arbitrary input clock is not always possible using FPGA clock generator resources. The JD PMOD has a number of pins that connect to the Artix clock routing resources if you want to use the correct clock for your ICs. As far as having multiple clocks is concerned the answer is more complex than I can address here. I'll suggest that you do your homework to understand the difference between derived and unrelated clocks as well as the general concepts in digital design. Basically, multiple clock domains can be tricky even for seasoned FPGA developers. If these clock domains are unrelated then it can be tricky for the Xilinx synthesis and place and route tools as well unless you know how to present them with good constraints. I'd start off keeping all of the ADC, DAC, processing etc. logic in one clock domain preferably at a clock frequency preferred by the devices in your design. As you get farther along in your project you can experiment with ways to move data into another clock domain for extracting information to say, a PC for post-processing. This comment: "I'll try routing output of the ADC to my ARTY A7 input and pass that signal directly to the DAC. At this point I would like to see a low noise, low jitter signal passing thru" bothers me a little as your audio source is NE555 based, but I'm not sure what you mean by "low jitter" or "low noise". Anyway, this could develop into quite an interesting enterprise; there are a lot of ways this could go in the future. Best wishes.
  25. Analog Discovery troubleshooting

    I'm looking at a completely dead AD2 device on my desk (one week of excellent service), and wondering if there is any way of checking (or replacing?) these myself, before starting the hassle of warranty & replacement. Or does even thinking about opening the device void warranty instantly :)? thanks, kalle
  26. Hi, I need the .iic file in order to upload the eeprom IC5, where the Cypress CY7C68013A firmware is stored, by means of CyConsole tool. Currently IC5 does not assert the USB-ON signal, which enables the power on the board. Sincerely, Radek (rsip)
  27. FPGA, ADC and DAC

    Good day wizards, I've tried to introduce myself here, but now I would like to ask for a comment on my thoughts. My goal is to master audio processing (mainly routing and level controls for a beginning) on FPGA. The diagram will be very simple: Audio signal generator => ADC => FPGA => DAC => Analyzer (Spectrum, THD, Level) Audio signal generator will be made of two NE555 clocks with different frequencies (say 1kHz and 15kHz) to have a difference between L and R channels. ADC will be CS5381 (24bit@48k), I2S output. DAC will be CS4390 (24bit@48k), I2S input. (later maybe something better, but for now I'll use whatever I have in a drawer). Once I get this AD-DA conversion running properly, I'll try routing output of the ADC to my ARTY A7 input and pass that signal directly to the DAC. At this point I would like to see a low noise, low jitter signal passing thru. Next step could be mixing L and R signals together, adding more converters generating AES/SPDIF signals on FPGA, etc.. But at very beginning, I have a fundamental problem with clocks. I want to run this setup at 48kHz, so I obviously need this clock and 48k*256=12.288MHz MSCLK. Playing around with PLL Clock wizard didn't gave me the desired result (still + or - couple MHz). I understand that it would not be a massive problem and I could run any weird frequency, but there will be a sync problem with external digital equipment if I get around to do, say AES/SPDIF interface. Finding XTAL trimmed to 12.288 is not a problem, but can I just hook it up to any desired pin and use it? I have also seen some posts (if I got it right) discouraging of using multiple clocks as it can get messy (inter-sync problems?). Before I dive into this, I would appreciate Your insights and critics. I will post all my story here as soon as I have something to share with You:) Thank You!
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