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  2. Piotr Rzeszut

    Digital Discovery - some questions.

    Hi @attila, The support is one of the fastest I experienced, so there is no reason to say sorry 1. Thank you for the second link - it explained everything I wanted to know. 2. So the input number is limited to 15 lines. 3. Right, this would require changing FPGA configuration 4. Yes, the best option would be to design own probe adapter with dedicated transceivers 5. Thank you for pointing out the paragraph - I noticed only information about AnalogIO DIOPP/PE
  3. Jens

    NexysVideo PHY-MAC routed delay path

    Hello, since one can see only a small amount of the routed wires on the PCB top and bottom layer the only confident source of the delay values is the PCB layout. In this case, the absolute delays are not of interest but the difference in delays between the data lines and clocks (rx and tx). The delay of the rx-clk-line may also be influenced by C23 (22pF to GND). Jens
  4. Tickstart

    NexysVideo PHY-MAC routed delay path

    :'D reminds me of: https://youtu.be/vH2-sXTmzWI?t=20m13s
  5. qwaserdf

    Zybo-Z7-20-pcam-5c many include files missing

    That was. Now I don't get anything from the cam, but I hope being able to achieve it before asking again. Best regards.
  6. Today
  7. Hello, i am having trouble using the chipkit uc32 together with the analog shield here : https://store.digilentinc.com/analog-shield-high-performance-add-on-board-for-the-arduino-uno-retired/ When i connect the Shield to my Arduino UNO one samples needs about 10 microseconds witch should be right. Instead if i connect it to the chipKit uc32 it takes about a 150 microseconds. I guess the SPI communication is not working properly but i dont know why. Since i dont know wether the board is the retired version or the newest i thought it might not work if its the old one. Did anybody else have a similar problem or is there a way to find out wether my uc32 is the old or new revision. Thx in advance
  8. Nurseda

    AD2 Network Analyzer Differential Sweep

    Thank you very much @attila , this is what I was looking for :)
  9. attila

    Patterns 1

    Hi @Poseidon For VGA 640x480 you need 300k RAM per bit (or just logic for vector graphics) and 25MHz pixel clock. For such projects you can use FPGA/HDL development boards , like: https://store.digilentinc.com/basys-2-spartan-3e-fpga-trainer-board-limited-time/ https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/ https://store.digilentinc.com/nexys-3-spartan-6-fpga-trainer-board-limited-time-see-nexys4-ddr/ https://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/ https://store.digilentinc.com/fpga-programmable-logic/ ...
  10. s71239@

    NexysVideo PHY-MAC routed delay path

    It's look like , that the delay path on the board is routed as shown. See picture. But i need if it is possible, a exact value of delay time for they paths. Thanks s71239
  11. attila

    FDwfAnalogInChannelRangeSet specifics

    Hi @mobigital See the related post:
  12. attila

    Digital Discovery - some questions.

    Hi @Piotr Rzeszut Sorry for the late reply but I was busy with some urgent project... 1. You can define the state machine using the Patterns/ROM Logic/Truth table https://reference.digilentinc.com/learn/instrumentation/tutorials/ad2-pattern-generator/start https://reference.digilentinc.com/waveforms_-_rom_logic 2. The inputs for the ROM logic are used to address the buffer, so having 32k (2^15) buffer you have 15 inputs, DIO 0-14 aka DIO 24-39 on Digital Discovery 3. The input line are hardcoded. It would be complicated to implement and even more complicated to use configurable input order... 4. No LVDS. Such would require dedicated connector, line termination... basically a different device for each protocol... 5. Please use the manual in the SDK installed by WaveForms: C:\Program Files (x86)\Digilent\WaveFormsSDK\ WaveForms SDK Reference Manual.pdf 12.4 Digital Discovery For the DigitalOut and IO functions, and AnalogIO DIOPP/PE the indexing 15:0 refers to DIO39:24. ...
  13. Marzhan

    Digilent PMOD CON2

    Thank you for your reply, by external source you meant level shifter or maybe level converter? In this case if I use MAX14850 as external resource is that suits ? And still I can use PMODs as input port to PL?
  14. attila

    Testing RS485 bacnet

    Hi @Numbawunfela The WaveForms application and device features can be explored in demo mode. The software can be downloaded from: https://reference.digilentinc.com/waveforms3 The Logic Analyzer Custom Decoder supports "Value to Text" script, which you can use to create such 'link file' feature.
  15. BogdanVanca

    NetFPGA Sume micro usb replacement

    Hello @jorge23, This is the Micro USB Connector that you are looking for : WMRU2AB-05FLB2DSR-4.0. I'm attaching you the mechanical document , in case is hard for you to find this specific part. Best Regards, Bogdan Vanca 163-451 WMRU2AB-05FLB2DSR-4(1.0mm) (2).pdf
  16. Dear all Unfortunately the SUME card micro USB connector was damaged. Although we tried to solder it again, the board is no longer recognized. I would like to replace the micro USB connector but I could not found any reference of the part number. Could you provide me the part number? or any that could fit to the PCB, since there are many type of micro USB PCB connectors. Best Regards
  17. Hi @tadius I have just verified with WaveForms v3.8.2 the AWG and Scope calibration is working for me on the Analog Discovery 2. Which device and software version are you using? Here you have a tutorial https://reference.digilentinc.com/learn/instrumentation/tutorials/ad2-calibration/start Instead the Wizard, I recommend using the step by step method by clicking on the links in the list like: "Waveform Generator 1 Low Gain"
  18. attila

    LabVIEW custom waveform with set run time (burst)

    Hi @Christopher Arena The wait should work just like the run and repeat does, the order does not matter. FDwfAnalogOutWaitSet(HDWF hdwf, int idxChannel, double secWait); In case you use trigger, the trigger-repeat selects to work as: trigger-wait-run-wait-run... or trigger-wait-run-trigger-wait-run... FDwfAnalogOutRepeatTriggerSet(HDWF hdwf, int idxChannel, BOOL fRepeatTrigger);
  19. Hi @kojak I added Script function for the next version for synchronous execution, save/open file/directory dialog With the currently released software you can dump the app output to a file and use Tool.getText var file = File("C:/temp/"+Tool.getText("File:", "log.txt")) file.deleteFile() if(!Tool.start("cmd.exe", ["/c", "ping 192.168.0.1 >> "+file.getPath()])) throw "error" while(wait() && !file.exist()); // wait for the file to be created wait(5) // additional wait for the app to finish writing, it depends on the app print("File", file.read())
  20. elodg

    Zybo-Z7-20-pcam-5c many include files missing

    @qwaserdf, you are wrongly assuming that Vivado 2016.4 without SDK installed will work with SDK 2018.1. Because it does not, Vivado is giving you an error during project creation: "couldn't execute xsct...". Since that fails, you are left with an old hardware handoff (.hdf) in the sdk workspace. You are importing the same old hdf when creating a new hardware platform in the workspace. That explains why it is looking for an nonexistent DDYNCLK variable, which is for an IP that does not exist in the hardware project anymore. The rest of the SDK errors are due to the wrong SDK version. You can try importing the hdf from hw_handoff instead and go through with manually re-creating the BSP for 2018, but do yourself a favor and install SDK 2016.4 instead.
  21. theAsker

    Program code on PetaLinux

    update: i figured out, that I can not write to the XADC registers the configuration. Can someone tell me why?
  22. qwaserdf

    Zybo-Z7-20-pcam-5c many include files missing

    Now I have the pictures of the errrors exporting the hardware from vivado and including the bitstream.
  23. Dear attila, I launched Waveform from DMG package, but the situation is the same. When I put the mouse onto the device name, the same dialog as yours except for SN was appeared. Here shows syslog messages at launching and exitting the application. Jun 21 16:04:34 kwbimac WaveForms[8459]: BUG in libdispatch client: kevent[mach_recv] monitored resource vanished before the source cancel handler was invoked Jun 21 16:04:45 kwbimac systemstats[51]: assertion failed: 17E199: systemstats + 914800 [D1E75C38-62CE-3D77-9ED3-5F6D38EF0676]: 0x40 There is no message on plugging AD2. According to other posts like me, the problem seems to be the FTDI driver, but I cannot find any solution from them. Is it confirmed that the driver works well on 10.13.x?
  24. qwaserdf

    Zybo-Z7-20-pcam-5c many include files missing

    I attached some images showing the process. I this example I open the projects, but I have also tried importing it instead, as the tutorial says. The error was the same. Now I will upload also screenshots importing the project from Vivado, but it will take a while untill I have them all.
  25. Poseidon

    Patterns 1

    Hi @Attila, I tried the constant type and it seems like it isn't fast enough to bit-bang a display signal out using constants. If I were to do it with patterns, what would be the trigger to know if a pattern has finished so I can load the next pattern since we are only limited to 32k samples. If you were to try and output a VGA signal, would you have suggestions on how to go about it with the Digital Discovery device? Many thanks for the prompt replies.
  26. Hi @Aki It looks like the application can't find the configuration files (firmware) for the device which are embedded in the app. Did you install (drag & drop) the WaveForms to the macOS Applications folder? Try launching the application from the DMG package.. Bring the mouse over the device name to see the device IDs.
  27. attila

    Patterns 1

    Hi @Poseidon In Patterns you could use Constant type, but for such simple purpose you could also use StaticIO
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