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  3. Today
  4. Getting started with Vivado

    I solved this. I had input 'clk' in the source and 'CLK' in the constraints file.
  5. Getting started with Vivado

    I have uploaded the file here. blinky.v
  6. Waveforms Linux install?

    @RTC, You mean waveforms 2015, right? Digilent used to offer a product called just "waveforrms" which isn't what you'd want to install. I've downloaded waveforms 2015 and installed it on Ubuntu 16. The trick was that you needed to use apt-get to install the .deb file. Don't forget to install the adept utilities and adept runtime as well. Dan
  7. Hello - trying to install waveforms on Ubuntu. Downloaded the .deb package but it has a myriad of conflicts and dependencies. Any help around? Thanks,
  8. Yesterday
  9. Matrix reception module in vhdl

    @cristian_zanetti, The link(s) above shows you how to build an readi function that you can use to read from the FPGA just like a memcpy, and an fwritei that you can use to write to your FPGA just like a memcpy. Both are very similar to an fread(). Dan
  10. Matrix reception module in vhdl

    What I want is to send a matrix to the FPGA and the FPGA to read it. How can I store or receive this data in the FPGA, since these come in an 8-bit package ?. I wish to have a fread in vhdl as would be done in MATLAB if I make myself understood
  11. Matrix reception module in vhdl

    @cristian_zanetti, Is this the sort of thing you are looking for? Something with a host interface that looks something like this in C++? I put a series of articles together discussing how to build it. While the code is all in Verilog, the articles break it down far enough that, in my most humble of opinions, you should be able to rebuild the interface in VHDL should you wish to do so. Let me know, Dan
  12. Matrix reception module in vhdl

    Good morning, I am currently using the uart protocol to communicate my Nexys 4 DDR with Matlab, but I have the inconvenience that I need to send signals of more than 8 bits, someone knows how to receive matrices in vhdl by uart (something like the function fread de matlab). Thank you for your attention
  13. Zynq-7000 TTC counter and RC

    Hello all. I have some misunderstanding with TTCs on zynq-7000. I used this guide to understand how TTCs are working, but seems like a quite subtlety which I don't understand. I have to use 2 TTCs with PWM (match value) and change RC in handlers to make CNC. After trying to make it like get new RC in handler and change RC I got unstable error for about 0.5s for 25s of changing RC and some impulses haven't generated but handler was called instantly after changing RC (I took into account that (RC - match value) should be greater then 0). I thought it can be because I have to: 1) reduce time we waste in handler (some code fragments like change RC made by asm); 2) consider some information we lose when we shift RC to prescaler; 3) consider counter of my timer because there are sometimes another handlers or something; 4) when we change RC we should reset counter (special bit in XTTCPS_CNT_CNTRL register); 5) see if RC is less then counter - make RC as match value (never happens). After this manipulations I saw that my timers with same amount RC (before counter compensation) ends in different time (I used different counters so timers have different number of RC). Can someone help me? P.S. I tried to use inline functions with asm() to change RC. Universal (by transmit using timer number) and 2 different functions with same (different only address to timer) asm code, and I got different results. I don't understand why. Thanks!
  14. Pmod OLED

    @hananson, Having made a PMod OLEDrgb run from an FPGA, I think you'll find the documentation you need in a couple of places. Perhaps the first and primary place is in the SSD1331 datasheet. This will tell you what all of the commands are that can be issued to the device, and what those commands do. This wasn't enough for me, however, since the initialization sequence of the SSD1331 is not trivial. I also needed to examine the MPIDE code for the PModOLEDrgb to get that part up and running. You can see my project here. The Verilog portion of the OLED controller is here. The controller responds to the wishbone bus, so you might find that controller kind of sparse regarding what you need to know. That wishbone bus is controlled by the ZipCPU, rather than microBlaze, and you can find the software for a ZipCPU OLEDrgb demo here. For the most part, the only thing I ever did was copy images to the OLEDrgb using a DMA controller, so I haven't gotten so deep a to write text to the device (yet), but I may do so in the future. Hopefully this helps. If not, let me know what more you need. Dan
  15. Dear FPGA experts, Good day! We want some expert advice of our present hardware setup. The setup is to connect the ublox SARA U270 into the xilinx FPGA board. The connection is from the DB9(RS232) of the Ublox SARA U270 into the pmod pins of the xilinx zedboard. Since it has different voltages, ublox SARA U270 is a 1.8V while the pmod pins of xilinx zedboard is 3.3V, we need to used the RS232 converter and a pmod RS232. In RS232 converter cable, we have in doubt of what to use between straight-through and a crossover cable connection. My understanding in the straight-through cable connection is good for unlike devices while on the crossover connection is good for like devices. Based on the issues aboved, we want some enlightenment advices of the expert in this forum: 1. Is my understanding between straight-through and crossover cable connection is correct? 2. In our hardware set-up, what cable connection should we used to connect between ublox SARA U270 and xilinx FPGA board? Thank you very much. God bless and more power!!! Thanks. Best regards, Glenn
  16. Anvyl Spartan-6 FPGA Trainer Board

    I did this step many times before posting in this forum, but today I succeeded with this step.
  17. Anvyl Spartan-6 FPGA Trainer Board

    @elodg Thanks for your reply! I tried with Antivirus (Avira) turning off and other networks (Wi-Fi) and doing the same by generating new bsp and project. Fortunately, it is successful and I could open it up with telnet also. I repeat the whole with turning on the antivirus and Wi-Fi, but it gives the below result. Thanks for your support. I guess that the regenerating of bsp and project made it right. Thanks again. If I am not wrong I think I need to modify echo.c for adapting the code for my own applications.
  18. How to sent data buffer?

    Hello Expert, Good day! I am a newbie in hardware design(FPGA). right now we're interfacing between camera(OV0706) and zedboard using pmod RS485 as bridge. We created successfully the block design in vivado and generated bitstream file for SDK environment as input. Upon running in SDK environment. My objective is to sent a hexadecimal command and camera will give acknowledgement if the data sent is already receive. Your response is highly appreciated! Thank you and Godbless! Best regards, EV Here's my code below; #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "xstatus.h" #include "ps7_init.h" #include "xscugic.h" #include "xparameters.h" #include "xuartlite.h" #define TEST_BUFFER_SIZE_SEND 5 #define TEST_BUFFER_SIZE_RECV 500 u8 SendBuffer[TEST_BUFFER_SIZE_SEND] = {56, 00, 36, 01, 00}; /* Buffer for Transmit Command */ u8 RecvBuffer[TEST_BUFFER_SIZE_RECV]; /* Buffer for Receiving Data */ XUartLite UartLite; /* Instance of the UartLite Device */ int UartLitePolledExample(u32 DeviceId) { int Status; /* * Initialize the UartLite driver so that it is ready to use. */ Status = XUartLite_Initialize(&UartLite, DeviceId); if (Status != XST_SUCCESS) { xil_printf("UARTLITE DRIVER FAILED"); return XST_FAILURE; } /* * Perform a self-test to ensure that the hardware was built correctly. */ Status = XUartLite_SelfTest(&UartLite); if (Status != XST_SUCCESS) { xil_printf("SELF TEST FAILED"); return XST_FAILURE; } return XST_SUCCESS; } int main() { unsigned char Sent_Count; unsigned int ReceivedCount = 0; int sentloop = 0; int index; int i; init_platform(); //INITIALIZE ps7_post_config(); //ENABLE TO PL UartLitePolledExample(XPAR_UARTLITE_0_DEVICE_ID); //ENABLE UARTLITE xil_printf("Start Looping....\n"); for(index = 0; index < TEST_BUFFER_SIZE_SEND; index++){ SendBuffer[index] = SendBuffer[index]; xil_printf("Send ......[%d] = %u\n" ,sentloop,SendBuffer[index]); sentloop++; Sent_Count = XUartLite_Send(&UartLite,SendBuffer,TEST_BUFFER_SIZE_SEND); xil_printf("Send Count... %u\n", Sent_Count); } if (Sent_Count != TEST_BUFFER_SIZE_SEND){ xil_printf("Sent Failed!"); return XST_FAILURE; } while(1) { ReceivedCount = XUartLite_Recv(&UartLite,RecvBuffer,TEST_BUFFER_SIZE_RECV); xil_printf("Received count %x\n", ReceivedCount); for(i=0; i < ReceivedCount; i++) { xil_printf("Received Buffer[%d] = %x\n" ,ReceivedCount,RecvBuffer); } } cleanup_platform(); return XST_SUCCESS; }
  19. Getting started with Vivado

    Hello, Can you please send me your project sources ?. In this way it will be easier for me to find out what causes this problems. cheers, Vanca Bogdan
  20. Last week
  21. Getting started with Vivado

    I did the "Getting started with Vivado" tutorial. When I went to generate a bitstream I got two error. They are: ERROR: [DRC NSTD-1] Unspecified I/O Standard: 2 out of 2 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk, and led. ERROR: [DRC UCIO-1] Unconstrained Logical Port: 2 out of 2 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk, and led. I have attached the xdc file. I has been edited per the tutorial instructions. I don't know why the IOSTANDARD is DEFAULT in the errors. The XDC file displayyed in Vivado shows IOSTANDARD LVCMOS33. Nexys-4-DDR-Master.xdc
  22. AD2 I2C via C++

    @attila Thank you for the quick response! So, it is possible to do it in C++ using the same methodology as WaveForms application uses? If so, would you be able to give me a small idea on how exactly or some pointers? I assume that I should create a clock at 100k with 50% duty cycle for SCLK, but my main questions comes in how do I generate the SDA line? I would be more than happy to post my I2C module here or send it to you guys after I've finished so that other people can use it as well. Thank you once again and Happy Thanksgiving!
  23. Anvyl Spartan-6 FPGA Trainer Board

    Indeed, the project included in the workspace does not work. But if you create a new "lwip echo server" example project in SDK along with a new BSP, that works. Make sure any software firewall is off or allows ping packets.
  24. Anvyl Spartan-6 FPGA Trainer Board

    I tried binding in three ways: 1. Attaching ELF in Microblaze through EDK and downloading bitstream. 2. Downloading bitstream without ELF file in EDK and Program FPGA in SDK. 3. I had another attempt as per Anvyl_demo_doc.pdf. After programming the bitstream without ELF file and then issuing the command connect mb mdm via XMD , it gives the following error in connectmbmdm.jpg. By running "xdisconnect -cable" and starting over again gives the same error. Is there any other way to check for the binding? By selecting the COM4 (from Device manager) port and the following settings (from Anvyl_demo_doc.pdf), Putty is never getting connected to the FPGA board. I tried with a simple hello world display also. a. Baud rate: 115200 b. Parity: none c. Data bit: 8 d. Flow control: none e. Stop: 1 bit
  25. How to detect and handle UIO interrupt.

    That link was for adding UIO. For AXI follow the above code.
  26. Pmod OLED

    Hi, I'm starting to work with my new zybo with all kinds of Pmods - using Vivado and SDK. In the SDK - I'm using the the c code examples and trying to understand them. I've been wondering - where can I get some additional information about the Pmods built-in library functions? for example: OLED_DisplayOff (&myDevice); - is very clear. but: OLED_SetDrawMode(&myDevice, OledModeXor); - is not that clear, and I would like to know what it does, and what parameters do I have. Is there a list of functions and parameters for all the Pmods? Thanks!
  27. AD2 I2C via C++

    Hi @primesc 1. The WaveForms application/Protocol tool uses the Digital In/Out functions to implement UART, SPI, I2C. At the moment there is no WF SDK example for I2C. 2. You might be reading "constant" value because the temperature is changing slowly. As noted in the AnalogIO_AnalogDiscovery2_SystemMonitor.py example, use the FDwfAnalogIOStatus to fetch readings from device. The FDwfAnalogIOChannelNodeStatus returns value obtained by the last AIOStatus call.
  28. Analog Discovery 2

    Hi @cyberjjk The serial number is unique for each device and it is programmed during the test procedure. The is no public method to changed this. The name of the device name can be changed in WaveForms/Settings/Device Manager.
  29. pmodoledrgb not displaying on nexys4 ddr

    i'l try my hands on all this hint.......get back to you on how it goes...thanks
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