FPGA

5,440 questions in this forum

1. Nexys 4 Board Rev 4 death

   Asked by miezekatzen_dompteur, August 22, 2017

   • nexys4
   • death
   • rev4
   0 votes
   3 answers
2. SDK Debugger Not Stopping at Main ZYBO

   Asked by swimteam, August 21, 2017

   0 votes
   10 answers
3. Transfer of data from PS to PL in Zynq 702 SoC

   Asked by vvk, December 1, 2016

   0 votes
   4 answers
4. Change ROM COE

   Asked by dcc, August 19, 2017

   • data2mem
   • rom
   • coe
   0 votes
   10 answers
5. Impact 13.2

   Asked by Jennifer, August 23, 2017

   • jtag
   • usb
   • impact
   • jtag-hs2
   0 votes
   1 answer
6. Connecting two Nexys 2 boards with USB

   Asked by sunny441, August 22, 2017

   0 votes
   3 answers
7. Vivado 2016.2 ERROR: [Xicom 50-38] xicom: Core access failed

   Asked by new_user, August 22, 2017

   0 votes
   1 answer
8. How to input entries from cmd or a computational application (or Matlab) to a VHDL file in ISE 14.7?

   Asked by cristian_zanetti, August 19, 2017

   • fpga
   • nexys 4
   • console
   • inputs
   0 votes
   3 answers
9. Arty Z-20 create_project failing in Vivado 2016.4

   Asked by jigish, August 20, 2017

   • arty z-20
   0 votes
   5 answers
10. Pynq Heating Issues

    Asked by omn0mn0m, August 15, 2017

    • pynq
    • temperature
    • heat
    0 votes
    4 answers
11. Why switches have been used in this project?

    Asked by fpga_123, August 20, 2017

    0 votes
    1 answer
12. ZYBO Getting Started Tut UART Ouput Is Junk

    Asked by swimteam, August 19, 2017

    0 votes
    5 answers
13. Is it possible to adjust the number of samples acquired and the sample rate of the Nexys 4 DDR ADC?

    Asked by JessPlazas, August 18, 2017

    • adc
    • nexys 4 ddr
    • sample rate
    • frequency
    0 votes
    7 answers
14. FPGA getting started

    Asked by Mark1000, August 17, 2017

    • newbie
    0 votes
    6 answers
15. Cannot Export Hardware w/ GPIO demo (Arty / Ubuntu Linux / Vivado 2016.4)

    Asked by stewart, August 17, 2017

    • arty
    • vivado
    • 2016.4
    • ubuntu
    • linux
    • .sysdef
    0 votes
    4 answers
16. CMOD A7 35T Does not boot from SPI flash

    Asked by jpiat, August 16, 2017

    1 vote
    2 answers
17. Creating a Custom IP core using the IP Integrator Tutorial problems

    Asked by FarmerJo, August 16, 2017

    • vivado
    • 2017.2
    • creating a custom ip core
    0 votes
    5 answers
18. PYNQ rev B & rev C

    Asked by desmond, August 16, 2017

    • pynq
    0 votes
    1 answer
19. Ways of connecting 2 Zedboard?

    Asked by gutielo, August 15, 2017

    • connection
    • zedboard
    0 votes
    3 answers
20. XADC working without power supply?

    Asked by gutielo, August 5, 2017

    • xadc
    • zedboard
    0 votes
    7 answers
21. Retargeting Xilinx ISE Design Suite 13.2 based on a Nexys3 board to a Zybo or Spartan 6

    Asked by fank, August 12, 2017

    • pmodsf
    • zybo
    • spartan6
    • zynq
    • flash
    0 votes
    10 answers
22. Least PL logic intensive data gathering

    Asked by StudentAmsterdam, July 10, 2017

    • zybo
    • adc
    • interface
    • interrupt
    • zynq
    0 votes
    17 answers
23. Anvyl Ethernet

    Asked by Andy Bradley, August 12, 2017

    0 votes
    5 answers
24. Arty Z7-20 hello world / BSP regeneration

    Asked by jacobfeder, August 5, 2017

    • arty
    • uart
    0 votes
    2 answers
25. How to use the ADC of nexys 4 (Artix 7) in VHDL to acquire signals?

    Asked by JessPlazas, August 10, 2017

    • nexys 4
    • adc
    • artix 7
    • vhdl
    0 votes
    3 answers