Jump to content

FPGA

Digilent Forum Rules

The rules for the Digilent Forum can be found here: https://digilent.com/reference/forum-guidelines.

Subforums

  1. Embedded Linux

    3k
    posts

Explore Questions

5,429 questions in this forum

  1. Keyboard keys -> momentary buttons

    Asked by Razvan1203,

    0 votes
    3 answers

  2. TIMING #1 The clocks DcoClk_1 and DcoClk_0 are related (timed together) but they have no common primary clock.

    Asked by Xband,

    0 votes
    3 answers

  3. FMC PCAM demo 2023.1-1 path entry problem

    Asked by Ansh Waikar,

    0 votes
    2 answers

  4. Data Transfer between PC and Zedboard

    Asked by RHCHOW,

    0 votes
    1 answer

  5. Some questions about API in DMGR

    Asked by erick.chang,

    0 votes
    1 answer

  6. Interfacing FT2232 with Spartan 7

    Asked by SCguy,

    0 votes
    1 answer

  7. JTAG-HS3 setup

    Asked by ekallal,

    0 votes
    1 answer

  8. Can't select Basys3 board in Vivado 2023.1

    Asked by Trevorskie,

    0 votes
    11 answers

  9. Issue with custom UART, looking for debugging paths

    Asked by sweeneyal,

    0 votes
    3 answers

  10. Nexys-4 board, confused about xdc file and migration to Nexys-4 DDR/Nexys A7-100t

    Asked by dravenchrist,

    0 votes
    1 answer

  11. Genesys2 FMC complete pinout missing in .xdc file

    Asked by DanielMtz,

    0 votes
    2 answers

  12. Zedboard gerber files needed!

    Asked by Leon18,

    0 votes
    5 answers

  13. The output waveform of the Eclypse Z7 Low-Level Low-Pass Filter Demo is not same as the reference example projects

    Asked by omara,

    0 votes
    0 answers

  14. NetFPGA-7 1G CML

    Asked by Duy Trung,

    0 votes
    1 answer

  15. Eclypse Z7 zmodlib undefined reference error

    Asked by BFritz,

    0 votes
    2 answers

  16. Eclypse 1410 ADC constraint file name mismatch issue, IO placement Infeasible

    Asked by Xband,

    0 votes
    3 answers

  17. Trying to modify the constraints file to accommodate 2 ADC 1410 modules, do not see how the schematic and baseline files match?

    Asked by Xband,

    0 votes
    12 answers

  18. NetFPGA-SUME bom file

    Asked by nvdatx1,

    0 votes
    2 answers

  19. I2C interfacing with Zybo Z7020

    Asked by Niranjana,

    0 votes
    0 answers

  20. CMOD A7 15T: unable to start from Flash

    Asked by Guest,

    0 votes
    17 answers

  21. Arty Z7 user manual or working steps

    Asked by Prakash,

    0 votes
    3 answers

  22. How can I store data in Basys 3 and use it in my DUT

    Asked by 222mzb,

    0 votes
    1 answer

  23. AXI_ZmodADC1410_v1_0.dcp is not suitable for use with incremental synthesis for this design. Please regenerate the checkpoint for this design with -incremental_synth

    Asked by Xband,

    0 votes
    1 answer

  24. Implementation of GNSS receiver based on MAX2769 and ZedBoard

    Asked by Jozef,

    0 votes
    14 answers

  25. Reset signal as a clock signal

    Asked by NotRandom,

    0 votes
    3 answers
×
×
  • Create New...