FPGA

5,431 questions in this forum

1. Is this how I'm meant to use flash storage in my design?

   Asked by pdw, April 8

   0 votes
   11 answers
2. How to restore FT2232 EEPROM back to factory settings?

   Asked by mixsemi, November 29, 2016

   • arty
   • ft2232
   • vivado
   • eeprom
   1 vote
   299 answers
3. Arty A7 Microblaze DMA Hangs on send

   Asked by jmckinney, Yesterday at 03:04 PM

   • microblaze
   • axidma
   • arty7
   • ddr
   • freertos
   0 votes
   1 answer
4. Zybo Z7 Ethernet project

   Asked by Oscar O., March 20

   0 votes
   22 answers
5. Signal Generation through DDS and analyzing the generated signal through FFT IP core in Vivado

   Asked by amna, March 14

   • dds
   • fft
   0 votes
   4 answers
6. Ethernet connection of Genesys -ZU 5EV board with host linux PC

   Asked by Dharmendra, Tuesday at 11:52 AM

   0 votes
   0 answers
7. Zedboard Rev. C OOB image booting problem

   Asked by mopplayer, January 12

   0 votes
   1 answer
8. PS PL communication using BRAM for sending 30 bytes of data in intervals

   Asked by pepeok, April 12

   0 votes
   3 answers
9. XADC configuration

   Asked by MOHD RIZWAN, January 30

   0 votes
   8 answers
10. PYNQ Z1 Rev F Phy Support

    Asked by Lance Manly, April 11

    0 votes
    1 answer
11. Problem with connection between the Nexys a7 and a 4x4 matrix keypad

    Asked by gabster, April 13

    0 votes
    1 answer
12. Genesys ZU 5EV Support

    Asked by shaur, April 8

    • genesys
    • petalinux
    • zu5ev
    0 votes
    2 answers
13. Difficulty implementing Nexys 4 DDR OOB project (synthesis runs okay !).

    Asked by Nevermnd, March 30

    0 votes
    4 answers
14. 3EG IRPS5401 Programming Files

    Asked by DBT, April 10

    0 votes
    1 answer
15. FPGA Verilog Project - Saving values for future processing

    Asked by Razvan1203, April 12

    0 votes
    1 answer
16. Is there any function in Vitis that can directly read the values from the ZmodADC1410 registers?

    Asked by Mamatchai, March 5

    0 votes
    13 answers
17. Genesys 2 Kintex-7 FPGA Board Voucher Period and Allowed Features of Vivado

    Asked by mulzem, April 4

    • genesys 2
    • kintex-7
    • voucher
    • vivado
    0 votes
    2 answers
18. timing A critical warning for create_generated_clock：Invalid inverted waveform on a clock tree

    Asked by youshanlian, April 11

    0 votes
    1 answer
19. Restore EEPROM for Diligent PYNQ-Z1 (XC7Z020) board

    Asked by Jason Tan, April 3

    0 votes
    1 answer
20. Kintex 7 Genesys 2 Board Vivado Design License validity

    Asked by Ganesh Surampalli, April 4

    1 vote
    1 answer
21. Rebuilding Genesys ZU out-of-box demo with Vivado 2023.1 not ready for prime time?

    Asked by BMiller, December 14, 2023

    • gensys zu
    • oob
    0 votes
    6 answers
22. What are the Steps Required to JTAG Boot Genesys-ZU3 Petalinux Project

    Asked by DaleD, October 21, 2022

    • fpga
    • embedded linux
    0 votes
    15 answers
23. XADC Example with Vivado block diagram?

    Asked by engrpetero, March 26

    0 votes
    19 answers
24. One Process FSM vs Next State Logic FSM

    Asked by digility, April 8

    0 votes
    2 answers
25. Zmod 1410 demo on vivado19.1

    Asked by stc Leuven, March 19

    • adc1410
    • adc
    • demo
    • vivado 2019.1
    0 votes
    3 answers