FPGA

1,492 questions in this forum

1. how can i convert a axi lite transactionto a axi full transaction ??

   Asked by sandy3129, 14 hours ago

   • vivado
   • axi lite
   • axi full
   • slave master
   0 votes
   1 answer
2. Mount SdCard XSDK

   Asked by mihai5, 11 hours ago

   • zedboard
   • xsdk
   • bare metal
   0 votes
   0 answers
3. BD-5-336 BD-design is locked

   Asked by riche, 21 hours ago

   0 votes
   1 answer
4. Arty Z7(-20) schematic discrepancies

   Asked by sapperlott, 15 hours ago

   0 votes
   0 answers
5. FPGA file types

   Asked by Gra, June 15

   • fpga file types
   0 votes
   4 answers
6. ARTY Bootloader in flash: ERROR in SREC line

   Asked by breinhold, June 15

   0 votes
   7 answers
7. Zedboard Zynq 7000 XADC Header

   Asked by Sam Bergami, June 19

   • xadc
   • xadc header
   • zynq 7000
   0 votes
   9 answers
8. PModAD1 documentation

   Asked by riche, Friday at 06:24 PM

   0 votes
   2 answers
9. Cmod S6 reset

   Asked by nixiebunny, Friday at 08:16 PM

   0 votes
   1 answer
10. Zybo demo projects in Vivado 2017.1

    Asked by mehdiru, June 11

    0 votes
    2 answers
11. Timer on bare metal app

    Asked by mihai5, Friday at 02:10 PM

    • zedboard
    • fpga
    • zynq
    • xsdk
    0 votes
    1 answer
12. Zybo serial port in Ubuntu

    Asked by jacobfeder, June 18

    0 votes
    4 answers
13. Compare a string with data stored in FPGA

    Asked by mihai5, June 19

    • fpga
    • vivado
    0 votes
    14 answers
14. missing include files xgpio.h

    Asked by egnanam, March 9

    0 votes
    13 answers
15. how can i input data bytes in Bram in verilog

    Asked by Rlohan, Thursday at 11:35 AM

    0 votes
    2 answers
16. Running XAPP1079 on Zybo

    Asked by vic, June 15

    • bare-metal
    • amp
    • xapp1079
    • zybo
    0 votes
    5 answers
17. Arty-Z7 GPIO0 access

    Asked by dbkincaid, Wednesday at 04:31 AM

    • zynq
    • arty
    • sdk
    0 votes
    2 answers
18. Init PS

    Asked by mihai5, Wednesday at 07:12 PM

    • fpga
    • zedboard
    0 votes
    1 answer
19. zybo Can't power up Zybo FPGA Board

    Asked by Kawnine, Wednesday at 03:51 PM

    • no power
    • zynq7000
    • fpga
    0 votes
    1 answer
20. ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:ip:clk_wiz:5.2

    Asked by Lisset, Wednesday at 04:51 PM

    0 votes
    1 answer
21. SPI Slave Select Examples, or 2nd SPI port?

    Asked by RichardV, June 19

    • cmoda7
    • spi ss
    • qspi ss
    0 votes
    9 answers
22. Using HLS OpenCV in Arty hdmi_in reference design

    Asked by RajatRao, June 17

    • hls
    • opencv
    • hdmi_in
    • arty
    0 votes
    3 answers
23. UART Interrupt in zybo queries

    Asked by K_Ashish, June 14

    • uart
    • zybo
    • interrupt
    0 votes
    8 answers
24. Nexys Video Differential IO standard error

    Asked by Robert Finch, June 19

    • nexy video io differential
    0 votes
    2 answers
25. Setting FTDI (USB to JTAG) IO drive strength

    Asked by Carson, Tuesday at 03:07 PM

    • ftdi
    • adept
    0 votes
    1 answer