FPGA

3116 questions in this forum

1. Pmod wifi

   Asked by kavya@iiitn, March 5

   • https://youtu.be/ktetmv3oipw
   0 votes
   11 answers
2. Output Port on IP Core

   Asked by newkid_old, Saturday at 06:30 PM

   0 votes
   3 answers
3. Genesys 2 FMC contraint file

   Asked by Saad1993, Yesterday at 02:55 PM

   • genesys2
   0 votes
   5 answers
4. PROBLEM WITH NEXYS A7 EVB

   Asked by Alex_V, Yesterday at 07:17 AM

   0 votes
   2 answers
5. JTAG HS2 Letter of Volatility

   Asked by JColvin, June 10, 2016

   0 votes
   13 answers
6. Zybo_Z7_20 SDX. Cannot build platform

   Asked by AndyCap, Saturday at 09:38 AM

   0 votes
   2 answers
7. Add DA3 PMOD to Pynq-z1 default Overlay

   Asked by Y_H, Friday at 03:47 PM

   • pynq
   • pynq-z1
   • da3
   • pmod
   0 votes
   3 answers
8. Can't get any output from my FPGA when programming it.

   Asked by mptcultist, Yesterday at 05:29 AM

   0 votes
   4 answers
9. BASYS-3 BOM specs on FPGA Power and Power Schematics

   Asked by Gabriel Uribe Romero, Yesterday at 05:03 PM

   0 votes
   0 answers
10. How do I change XDC files?

    Asked by hiroowada, Sunday at 01:03 PM

    0 votes
    1 answer
11. Nexys Video DPTI Virtual Screen

    Asked by robfinch, Saturday at 12:45 PM

    0 votes
    10 answers
12. Arty A7 - Bootloader does not load

    Asked by TomF, June 14

    0 votes
    7 answers
13. Zynq (Ettus E310) + ADC AD9361 (via LVDS) ???

    Asked by andre19, Thursday at 10:22 PM

    • lvds
    • zynq
    • adc
    0 votes
    2 answers
14. ZYBO Z7-20 Getting Started - no Uart

    Asked by user2051, Thursday at 08:42 PM

    0 votes
    4 answers
15. Arty S7 - Changes from Rev B to Rev E

    Asked by Mike Reynolds, June 19

    0 votes
    4 answers
16. Pmod da3 reconstruction filter

    Asked by lwew96, Thursday at 04:53 AM

    0 votes
    3 answers
17. pmod wifi

    Asked by harika, December 5, 2018

    0 votes
    34 answers
18. FIR compiler 7.2 stopband

    Asked by Ahmed Alfadhel, June 14

    • fir
    0 votes
    13 answers
19. Translating "DjtgTwoWireDemo.cpp" to 4-Wire JTAG from DigilentSDK

    Asked by YaBoyRock, Thursday at 01:53 PM

    • jtag-smt
    • raspberry pi
    • xilinx
    • kc705
    • jtag-smt1
    • 4wire
    0 votes
    5 answers
20. microblaze pointer alignment (gcc)

    Asked by Zorroslade000, June 19

    • microblaze arty
    • gcc
    0 votes
    3 answers
21. Implementation Error when using two sepatate MIG instances and leaving one disconnected on Nexys 4 DDR

    Asked by dmishins, June 19

    0 votes
    4 answers
22. Arty - Axi ethernet lite VHDL

    Asked by rakeshm55, June 19

    0 votes
    3 answers
23. Measure Clock on Arty

    Asked by PoojaN, June 17

    0 votes
    7 answers
24. Reset required for MicroBlaze design to start on Cmod A7 board

    Asked by stunix, December 26, 2018

    0 votes
    13 answers
25. UART does not work on Nexys 4 DDR when following tutorial

    Asked by dmishins, June 17

    0 votes
    8 answers