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  1. Today
  2. I just received my new Arty A7-35 and it didn't take long to create my first design and program the FPGA. So far so good. But I cannot figure out how to program the flash so the configuration loads at power-on. The Hardware Manager seems to have a setting for the memory but it wants a "configuration file" and I'm at a loss on how to create one. I am not finding any mention of this in the Digilent docs and I've been searching though the Vivado docs without luck. What am I missing? Thanks!
  3. Yesterday
  4. Hi @Brent, My initial guess (I haven't seen evidence of this, pure conjecture only) would be that the newer Macbooks are expecting some sort start up communication with the device which the Basys 3 is not set up to do. Alternatively, it could be that these newer Macbooks do not have the D2XX drivers from FTDI and for whatever reason the D3XX drivers (if those are the ones that are installed anyways), so I would probably recommend trying to install those drivers: I do not know if this will solve the problem though since the drivers would pre
  5. MattC

    Can't Program Arty A7-35T

    Thanks for the response Bianca. Sorry it took awhile for me to respond since for some reason I didn't get an email that you replied even though I was following the thread. Nothing shows up in hardware manager when I plug it in on both my desktop and laptop.
  6. In Wavegen, turning the mouse scroll wheel on the "phase" box scrolls in 15 degree increments. It would be great if there was a Setting that would let the user change that increment. I've been working with antenna phasing circuits where having a one degree incremement would have been great. I guess this could really be a request for configurable mouse wheel steps for all values in all WaveForms instruments. Alternatively, if you don't make this a Setting, then maybe switch to a finer increment when the mouse wheel is turned while holding a key like Ctrl, Shift, or Alt
  7. Was wondering if anyone could confirm what OS's are supported with the JTAG-HS3 with Z7000s? Mainly interested if this works natively with Windows 10 as I could not find it in the product documentation.
  8. JColvin

    Cmod A7 STP file

    Hi @jHoneyo, I was able to locate the 3D model for the Cmod A7; it is now uploaded and available on the right-hand side of it's Resource Center under Design Resources. Thanks, JColvin
  9. Thanks. I honestly kind of assumed that HSx support entire range of possible configuration voltages (which are 1.5, 1.8. 2.5 and 3.3 V), hence why I asked when noticed inconsistencies. 1.5 V is required for 7 series FPGAs if you need to use bank 14 (and maybe 15, depending on config mode) for DDR3, as it's the only way to reach required memory bandwidth in certain packages (like x32 for BGA-256, or SODIMM x64 for 484 or 676 package). It's not really a showstopper as it's possible to just add a few more level shifters onto such board (there will be some for QSPI Flash already, as 1.5 V versions
  10. Hi @mgal, The community on the website will be the best resource in terms of getting these older materials as they maintain and create the Pynq images, not Digilent. It looks like you can find the older materials on the Pynq GitHub though: Thanks, JColvin
  11. I will let our design engineers know that there is some interest for 1.5V signal support, in case that is something that can be relatively easily integrated into any future versions of the HSX products that might be made. I realize it'll be too little too late for you by then, but perhaps (if Digilent does make it) it will help somebody else. Thanks, JColvin
  12. Thanks for you response - delayed response is still infinitely better than no response at all. It's a shame 1.5 V is not supported - I guess I will have to splash up for Xilinx official programmer. HS3 served me well over years, but it looks like it's time to move on.
  13. Hi @iyer25, It is 2019.1 code; the readme was not updated. You can confirm this is 2019.1 from the tcl script that creates the block design which specifies the 2019.1 version of Vivado. Thanks, JColvin
  14. Hi attila, I find the thread posts on the forum resolves my confusion: Problem setting CH. 2 Voltage Range AD2 - Scopes & Instruments and the WaveForms software - Digilent Forum (
  15. Hi. I have a query about the connection that I must do to work correctly with a uc2 chipkit and a wifi shield chipkit. When I connect the two components, I can see through the serial port of the uc32 chipkit that it detects the connection with the wifi shield chipkit, however, for example, with the wifi scan program no network is detected, I also observe that no led lights up on the shield wifi when I make the connection. I don't really find much information about it. I appreciate your help. Regards, Jesus
  16. Great! I understand. That really help me. Thanks!
  17. Dear Sir or Madam, Is it possible to provide the default/factory bitstreams for both Nexys 4 and Nexys 4 DDR boards? Sometimes students need to reprogram the board’s FLASH, but it is useful to restore the factory configuration. Thank you for your attention. Best regards Arnaldo Oliveira
  18. Is this v2019.1 code? when I check on the read me it says 2018.2
  19. The RS-232 PMOD is OK if you have a really, really old PC with an RS-232 serial port and DB-9 connector. They haven't made a PC motherboard with those for a long time. Useful baud rates are limited to about 115200 baud. The USBUart PMOD is similar to the TTL USB Uart breakout boards and cables that I referred to. For most Digilent programmable logic boards this is a a fine alternative. The only issue would be that it uses 4 PMOD pins whether you want to or not. The connector is suitable for use with a PMOD. The options that I mentioned just need 2 GPIO pins plus a ground pin so these are more
  20. Hello @Kyle_ISL, Firstly, you can check the video resolution by double-clicking the Video Timing Controller and going over to Default/Constants. There you can see the Video Format. For more information on the Video Timing Controller, AXI-Stream to Video Out and the RGB2DVI ips you can check out the user guides here:
  21. Hello @Marycruz, Firstly, I have also encountered the vivado launcher error from time to time. It is nothing serious and can be ignored. Secondly, Vivado and the SDK can have problems if the paths to the project contain whitespaces I would recommend extracting the project in a folder that does not contain whitespace such as "Marycruz_Blas_Hder" or something equivalent. Best wishes, Eduard
  22. Hello @aams, Was the project working before on the zedboard? Or are you talking about the HLS ip? If the HLS testbench results were correct, maybe the problem is the clock period with which the design was constrained. Can you tell me the clock period of the HLS ip? Can you also attach the HLS code? Thanks, Eduard
  23. Hello, Are you sure that everything is okay with the new .bin file? From what I recall, boot.bin consists of .bit & .elf files. Maybe there have been changes to the .bit file which affect the behaviour of the GPIO. Best wishes, Eduard
  24. jHoneyo

    Cmod A7 STP file

    Where can I find stp file for Cmod A7? I can't find in Resource Center page. Thanks and Best Regards, jHoneyo
  25. Hello @rajareanne, I would say it is possible to use the DDR to write a long sequence representing the sine wave. For streaming purposes, I think it would be best for you to use a DMA module. I have found this demo, which does something quite similar to what you are looking for Best wishes, Eduard
  26. Hi, Thank You for your reply. I am planning to buy the below. Could you please let me know if these two would be fine for CoolRunner II board? Thanks in advance.
  27. Hi, there! I'm trying to utilize the pcam to test my convolution module. My plan is adding ip block between AXI4-Stream to Video Out where Video(RGB) data is come from memory(DRAM) and RGB to DVI Video encoder, just like a picture below. To do so, I need to know the information of video data(RGB). My questions are, -What is the resolution of the video is? -What is the frequency of pixclk? -How many clock should be counted to stream out 1 row, and how many rows are there for 1 frame? -How long vsync and hsync becomes 'HIGH' to distinguish each column and r
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