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  2. gotcha, thanks for the thorough answer. Yes okay, sounds like it would work. I havent spent any time with larger scale FPGAs, and I was just concerned that it would take like 1 or 2 hours to synthesize and implement a design. Sounds like it wont unless its reeally big. and yes I use up the synthesis time to do other things as you mentioned like answer emails and do calculations. Thanks for the advice :)
  3. Yesterday
  4. Hi @Sean Kelly, I'll need double check this, but I believe this how some of the hardware configuration is done based on Section 7.7 of the datasheet (the one I'm looking at is here: This enables all communication speeds, enables the 2 ns TXC delay required for RGMII, and allows the module to work with 1.8V. Thanks, JColvin
  5. @Paul Howard, The Nexys Video and Genesys2 allow user selection of Vccio on banks with IO connected to the FMC connector. The FMC connector isn't easy to design an add on board for. A better choice might be SYZYGY based boards. I have had good experience with the Opal Kelly XEM7320. Digilent also makes an Artix based SYZYGY FPGA board with 1 standard SYZYGY port ( I haven't used this board so I have no opinion on it ). The SYZYGY connector footprint isn't trivial to work with either but is suitable for high speed IO.SYZYGY standard ports by definition have a mix of single-ended and diff
  6. Hi @rvxprj, I would probably recommend taking a look at the Out-of-Box demo for the Nexys A7 then; this and other demos are available in the Nexys A7 Resource Center: Let me know if you have any questions. Thanks, JColvin
  7. Hi @Coder, You may be able to store the .wav files on an SD card and then read them off the SD card into RAM and then play them out through an audio codec, but the implementation of how this might be done will vary on what board you are using (a microcontroller, a microprocessor, a FPGA, a SoC, etc). Thanks, JColvin
  8. What do you think of as too much time for the tools to create a configuration file? I have a Genesys2 and have never had an issue with any version of Vivado ( I don't use Vivado 2019.2 or later ). There are a lot of factors that decide how long the synthesis and P&R need to work. Most of it revolved around meeting, or more accurately trying to meet, timing constraints. If you have a design with a lot of clock domains tied to IO and use a lot of block memory it can take an unusual amount of time. In the old days very large FPGA devices might have taken more than 45 minutes for this process.
  9. I need an FPGA board that supports 3.3V LVCMOS I/O and 1.2V LVCMOS I/Os. Spartan7 & Artix7 FPGAs can support that, but are there any boards available that support changing the FPGA I/O banks Vcco? If not directly supported, reasonable hardware mods would be fine too. Thanks!
  10. Hi @eeoh, I learned that you'll actually be able to update the Digilent Agent yourself. You can do this by copying the contents of the .zip file from your other post into the following folder: Let me know if you have any questions about this. Thanks, JColvin
  11. Hi all! I am thinking of purchasing a genesys 2 Board which has a kintex-7 part on it. I have 3 FPGA boards (started with a small lattice board, then a medium altera board, then got a new laptop and a zynq board) and want to move up significantly from the Arty z-7 (which is still a great board) for some of my projects. The problem is, Im wondering if some FPGAs are too much for some computers with not enough resources? specifically Im worried about synthesis and implementation time. If you put the same design on different sized chips, does the larger chip take longer to synthe
  12. Hi @svaughn442, The schematic is the best place to determine correct FPGA pins. That being said, it looks like you have an old version of the .xdc file; the current Eclypse Z7 xdc on our GitHub has this particular error you pointed out fixed: Thank you, JColvin
  13. Hi @White Horse Software, A couple of things. The first is that you don't actually create a clock within the xdc (despite the naming convention of the "create_clock" constraint); it just formally defines the existing clock on the board so that the tools can properly handle the design. You will need to keep this create_clock as defined in the Basys 3 xdc (available here: What you can do though is create a counter and clock divider to update the state of the LED after a set number of clock cycles. How you might d
  14. JColvin


    Hello, I responded to your other thread here. Thanks, JColvin
  15. I did a little more digging and found that the Digilent made IP for the CSI-2 interface follows version 1 specification as per here: I wasn't able to find anything definitive for the hardware itself as of yet though.
  16. JColvin


    Hi @Leo_W, That is an odd error if Adept is successfully able to detect (and based on your screenshot) and program the downstream A7-200T (I presume this a custom board as opposed to a Digilent or Xilinx evaluation board?), but Vivado is not able to detect the downstream FPGA. Xilinx tools tend to forcibly take over enumeration of the FPGA even if Adept is already connected, at least from what I tested in with a JTAG HS2 in Vivado 2018.3. Based on your screenshots it looks like you are using Windows; do you know if you installed the Digilent cable drivers during the Vivado installati
  17. Can anyone explain why the dev kit has 4k7 pull ups on the RxD 0-3 lines? I can't find anything in the PHY datasheet to indicate the need and I have never seen this done before. Thanks.
  18. Hi, there seems to be discrepancy between the Eclypse schematic and the Eclypse XDC file. JA1 is B15 and JA2 is C15 here is the XDC which shows the JA1 is H17 and JA2 is H18. Which is right ?
  19. Hi @Mirko Pfitzner, I reached out the other day to the design engineer of the Pcam 5C about your question, but am still waiting to hear back. Thanks, JColvin
  20. Hi @LorenzoFPGA, Which FPGA are you referring to in particular? Thanks, JColvin
  21. Hello xc6lx45, Thanks for your help. To your question: I've tried with the jumper in all 3 positions, but typically we run it in SD. Actually, we have an SD card with our standalone app and a linux image which is booting and working correctly on our system (a stewart platform running inverse and forward kinematics). It's really quite wonderful the latency and performance we're getting from the Zynq. However when I try and boot that SD card on this particular Zybo, nothing happens. To recap: we have 3 Zybos in total: 2 function as expected when debugging or booting from the
  22. @attila, Thank you so much for the help; really appreciate how quickly you answered. Couldn't respond until now, but Scope.Time.Samples.value was exactly what I needed! I wasted too much time trying to do what I could have already saved in my workspace (If only I had read your response sooner), but for anyone who stumbles here looking for recording/capture code, here's some code I made to record an arbitrary pulse length for a heating/cooling machine. You'll have to modify the Wavegen1 parameters though, the control scheme for the machine was inverted (off->Heating, on->Off/Coo
  23. Hi @kazu You could use Phase measurement or FFT phase for sine/periodic signals. The following script looks for value on channel 2 which at least as high as the value in the middle of channel 1 var rg2 = var c = rg2.length var c2 = c/2 var v1 =[c2] print("Voltage:", v1) for(var i = c2; i < c; i++){ if(rg2[i]<v1) continue print("Time:",(i-c2)/Scope.Time.Rate.value) break }
  24. Hi @jtoakes52 I'm not sure if it worth repairing if the FPGA is damaged, other ICs may be damaged too... Yes: XC6SLX16-L1CPG196
  25. Hi, did you check the boot mode configuration section (QSPI vs SD)? See section 2 - Is the jumper set correctly? - if QSPI, is there a valid FSBL in one board and not the other? I wouldn't be surprised if there a default FSBL in the working board that tries multiple options until it finds the first bootable image. An easy way to check is to clear the flash of the working board. If it stops working, you've found the root cause (obviously it'll "break" the working board temporarily but b
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