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  2. Hello all, First of all thank you for clicking this post, and please if you are knowledgeable in the network analyzer functions read this if you have time. I am having some trouble with the gain reading of the network analyzer. I am currently a student with a simple project of designing an inverting op-amp with a gain of approximately 32 db (and no this is not me trying to get someone to do my project for me). As far as I can tell the network analyzer must be reading it wrong or I have some setting that is off. I will try to summarize: I designed the circuit by hand, hand calculations check out. I designed the circuit in B2Spice, software simulations confirm my calculations. I build the circuit on the electronics explorer board and test with oscilloscope and network analyzer. Oscilloscope results are fairly normal (lower than the theoretical results, Network analyzer is not. Below I have attached images of all my info and I will summarize calculations at the end (although I really doubt the fault lies there) So gain in this case is calculated by Vo/Vi or -R2/R1 which in either case should at least get me 30db. If going with the oscilloscope output we have (1.6/.05)=32 V/V. And db=20*log10(32)=30.1 db. But alas, I get 20 db over and over. More to my dissatisfaction is a fellow student using an Analog Discovery 2 has made nearly the same circuit (only differences are the resistor values, but it has same ratio) with almost exactly the same results except the network analyses comes out correctly. Thank you so much for your time if you made this far, and I would greatly appreciate any ideas.
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  5. AD2 Equivalent time sampling

    O.k. makes sense now. I looked for it in the manual but couldn't find it there. Given it is a very useful feature and extends its capability significantly, it's probably worth giving it a specific note.
  6. Microblaze Xintc_SelfTest Failure w/ Baseline ARTY BSD

    Hi @macgyverque, I was able to get the testperiph.c to run without an issue using the Arty-BSD project as shown below. Make sure to press buttons when asked in the terminal text. I was also able to run the xintc_example.c here with a small change to the BSD project in Vivado. I had to add one more input on the xlconcat going from In0-In6 to In0-In7 inputs. Then I connected In7 to the interrupt on the UARTLITE IP Core. I successfully ran the xintc_tapp_example.c here as well. Could you take a screen shot of your block design and attached the SDK code. cheers, Jon
  7. Zybo demo projects in Vivado 2017.1

    Hi @chrislafave, Glad to hear you were able to get the IP's to upgrade. cheers, Jon
  8. Zybo demo projects in Vivado 2017.1

    Booyah! I ran "upgrade_ip [get_ips *]" and it upgraded them all! Saved by the command line again! Thanks again, jpeyron!
  9. Zybo demo projects in Vivado 2017.1

    I ran "Show IP Status" in order to find out that I can't upgrade the "locked IP's". As you can see in the screenshot, the "Upgrade Selected" button is grayed out. ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design '' is locked. Locked reason(s): * BD design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. List of locked IPs: hdmi_out_auto_pc_0 hdmi_out_s00_regslice_0 hdmi_out_xlconstant_1_0 hdmi_out_axi_mem_intercon_0 ... hdmi_out_processing_system7_0_axi_periph_0 hdmi_out_processing_system7_0_0 hdmi_out_xlconstant_0_0 ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.
  10. Hello All, Have been attempting to enable interrupts on a project using the Arty and was running into issues with the intc_SelfTest failing. I loaded the Arty BSD from github thinking I had some issue with the project itself but am getting the same exact result. Any suggestions as to what I may need to change? I changed nothing in the BSD so I'm assuming it should be correct. Also followed multiple online tutorials and have been unable to solve the issue. All suggestions are greatly appreciated. Thx!
  11. Hi @Jagbandhu Sahu, I do know that the JTAG-HS2 works with the ARC processors. Unfortunately we do not have any information about the ARC processor. You will need to contact Synopsys for assistance in developing an application which can read and write RAM memory of the controller using Digilent HS2 JTAG cable. thank you, Jon
  12. PikeOS project on ZC702

    Hi @Atir, Unfortunately, I am not aware of anyone at Digilent that is familiar with PikeOS. We support Petalinux. Hopefully one of the more experienced embedded linux community members might have some information about this. I would also suggest reaching out to SYSGO here since they are the creator of PikeOS. thank you, Jon
  13. This is just follow up: I found that if you disconnect with the terminal program before plugging the USB cable back in and then reconnect right after plugging in the USB cable, all of the messages get presented. This way it seems to be ready before the FPGA DONE LED is presented. Considering the actual amount of the room in the flash that is required for the 35T FPGA load, an offset of 0x00218000 can be used to maximize the flash space that will still available for program code. This is 48% of the N25Q032 flash whereas the offset of 0x00300000 only leaves 25%. Again, I did not compress my image. I did program this new offset into blconfig.h and used it in the elf program flash step just to test it out and insure that it still worked.
  14. Micro SD Card Slot on ZYBO Board

    Hi @talentlyb, I have sent you a PM about the next step for this situation. cheers, Jon
  15. JTAG-SMT2 usb tabs

    Hi @tbonnefond, I had talked about this with our senior layout and design engineers previously about a similar thread here and their response was that the electrical keep out areas are flush with the PCB and will not cause issues with it seating on the target PCB. You should not need usb slots. cheers, Jon
  16. Anyone know the name of the connector? I can't find one with the indexing tab. Looks like I have pins and a crimp tool and would like to build a couple task specific cables Thanks Cory
  17. Zybo demo projects in Vivado 2017.1

    Hi @chrislafave, Are using our original Zybo HDMI-OUT project here made in Vivado 2015.4? The tcl script is here: hdmi_out/src/bd/system.tcl? I just completed bitstream on the zybo hdmi-out project in Vivado 2017.1. I would suggest to used a project that you have not made changes to or opened with vivado yet. Make sure you are using the Vivado 2016.4 version of the Zybo HDMO-OUT here. Make sure that you have downloaded and added the contents of the vivado library from here in the repo\vivado-library folder here: Zybo-hdmi-out-master\repo\vivado-library. Then edit the hdmi_out_bd.tcl from 2016.4 to 2017.1 here: Zybo-hdmi-out-master\src\bd\hdmi_out\hw_handoff. After editing load the project in Vivado 2017.1 , upgrade the IP cores by going to tools->reports-> report ip status. Next create a wrapper and then generate a bitstream. cheers, Jon
  18. JTAG-SMT2 usb tabs

    Hello, I was wondering if someone can tell me if the usb mtg tabs protrude out the bottom side of the module? The recommended footprint has 2 electrical keep-outs for these tabs, but no slots. The 3D step pic shows the tabs sticking out approx. 14 mils on the bottom side which would keep the module from sitting flush on the pcb. Any help would be greatly appreciated! Tim
  19. Electronics Explorer Troubleshooting

    Thanks @attila, Updating the driver by following your instructions worked splendidly!
  20. Zybo demo projects in Vivado 2017.1

    Thank you very much for that. I followed that post, having fixed the tcl files and updated the IP's with "report IP status". There is no "hdmi_out_bd.tcl" in .../hdmi_out/hw_handoff (as mentioned in the post), only hdmi_out_wrapper.hdf. Unfortunately adding a wrapper stopped at: make_wrapper -files [get_files /home/chris/digilent_git_zybo/Projects/hdmi_out/proj/hdmi_out.srcs/sources_1/bd/hdmi_out/] -top ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source: /axi_dynclk_0/REF_CLK_I /axi_dynclk_0/s00_axi_aclk /axi_gpio_btn/s_axi_aclk /axi_gpio_hdmi/s_axi_aclk /axi_gpio_led/s_axi_aclk /axi_gpio_sw/s_axi_aclk /axi_mem_intercon/ACLK /axi_mem_intercon/S00_ACLK /axi_mem_intercon/M00_ACLK ERROR: [BD 41-1031] Hdl Generation failed for the IP Integrator design /home/chris/digilent_git_zybo/Projects/hdmi_out/proj/hdmi_out.srcs/sources_1/bd/hdmi_out/ ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.
  21. FPGA based PWM generation

    @Piasa, Back to this comment I don't believe that testing of the algorithm on hardware quite agrees with the above description. The description might be correct but I don't believe that the implementation does exactly what it should be doing to agree with the description. Of course I've been wrong about other aspect of this topic. Here is my test project. I do hope that anyone interested in this conversation will look it over and try it in simulation and on hardware if they can.
  22. Hi @gm_, I was mistaken with question 1, to clarify: The JTAG-HS2 works in Vivado and iMPACT under Fedora. Sorry for the confusion, Jon
  23. No Compatible Board Interface

    Hi @FarmerJo, Certain parts of the Zybo are tied directly to the Zynq processor such as the UART. I have attached a screen shot of the zynq processor. This makes the task of learning Microblaze much more difficult on the Zybo. You will need to research how to use the Zynq and Microblaze processors together. Unfortunately, I have no experience with this. edit: Here is a Xilinx forum thread that deals with this issue on a Zedboard with has a ZYNQ processor as well. thank you, Jon
  24. Zybo demo projects in Vivado 2017.1

    Hi @chrislafave, Here is a forum that has the process to get the Zybo projects working in the new versions of Vivado. In the thread I am doing it for Vivado 2017.2 but you just need to use 2017.1 instead. So far I have not had any issues with this process. Let me know I you are not able to get the project working. cheers, Jon
  25. Zybo demo projects in Vivado 2017.1

    I just now achieved success with the dma_audio demo. I changed the "set scripts_vivado_version 2016.4" to 2017.1 in line 23 of system.tcl and changed the "Vivado Synthesis 2014" to 2017 in lines 72,75,88,91 of create_project.tcl. I'd also taken the advice, 'Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script.' in line 28 of system.tcl. I'd erased the project and run the create_project.tcl each time I tried something new until it worked. Unfortunately, this same procedure didn't fully work on the hdmi_out demo. It errored before it got to wiring the blocks together: ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source: /axi_dynclk_0/REF_CLK_I /axi_dynclk_0/s00_axi_aclk /axi_gpio_btn/s_axi_aclk /axi_gpio_hdmi/s_axi_aclk /axi_gpio_led/s_axi_aclk /axi_gpio_sw/s_axi_aclk /axi_mem_intercon/ACLK /axi_mem_intercon/S00_ACLK /axi_mem_intercon/M00_ACLK ERROR: [BD 41-1031] Hdl Generation failed for the IP Integrator design /home/chris/digilent_git_zybo/Projects/hdmi_out/proj/hdmi_out.srcs/sources_1/bd/hdmi_out/ ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors. while executing "make_wrapper -files [get_files $] -top -force" invoked from within "add_files -norecurse [make_wrapper -files [get_files $] -top -force]" (file "./create_project.tcl" line 110) update_compile_order -fileset sources_1
  26. Hello, You will need the Adept Runtime, available for download here: We also have an installation tutorial for Linux based machines that you can follow along here: Let us know if you have any questions. Thanks, JColvin P.S. I also moved this topic to a more appropriate section of the Forum.
  27. I am fairly new user of Waveforms 2015 and I have both an Analog Discovery 2 and a Digital Discovery that I am trying to use for some for some tests with custom scripts. I am having difficulty finding the documentation or some example code that instructs me how to assign the pins I want to use for the Select, Clock, DQ0 (write), and DQ1 (read) functions. I have two different devices I need to communicate with through SPI but there is only one "select" line. I have two transceiver/MCU nodes connected together in a system and I need to communicate with the SPI port of one node to have it send a data packet to the second node, and then I need to switch my SPI bus pins to the second board and read verify it received the data I just sent from the first node. I am able to script up a sequence of Read/Write transactions using the pin assignments set in the Waveforms GUI for my first device, but I now need to re-assign the pins in the script so that I can configure my second device without having to manually change the pin assignments in the Waveforms GUI. For example, if I use my Digital Discovery, the SPI pin assignments I would like to use are: Node 1: Select = DIO 24, Clock = DIO 25, DQ0 = DIO 26, and DQ1 = DIO 27. Node 2: Select = DIO 28, Clock = DIO 29, DQ0 = DIO 30, and DQ1 = DIO 31. Could I get some example code to show how to assign the DIO pins for the various SPI signals Select, Clock, DQ0, DQ1 in both the Protocol/SPI/Custom script and the general Script tool in Waveforms 2015? I'm sorry if this is a newbie question or documented somewhere already, but this has been elusive to me. Thanks!
  28. Hi forum, Need help installing waveforms 2015. Deb file in the downloads page does not include necessary runtime dependencies that need to be installed prior to running the waveforms installer. This means that the installer exits prematurely due to lack of runtime libraries. Can someone provide a link to these necessary libraries on the digilent website in order to make this a successful installation? Thanks! Dimos
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