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  1. Past hour
  2. FFT

    @D@n - "ddsAnalog" is the output signal of the DDS core (displayed as signed decimal) and is the input for the FFT core. - "FFT_RAW" shows the output of the FFT core (signed decimal). -> the sourroundings of the ddsAnalog and FFT_RAW signals are on both pictures the same, only the bit size is different. - "m_axis_data_last_0" shows the tlast of the FFT core. - "number_0" is a counter only to control the DDS output lenght I hope this helpts to easier follow my question. .....actual i am most confused about the data input size. If i set the XFFT core input size to 16bit i need a 32bit signal input, is this right?
  3. Today
  4. FFT

    @Weevil, I'm struggling to understand your picture. Can you explain for me what it is you are plotting? What is going into the FFT, and what is coming out? Even better, can you create a more complete trace showing the input and output FFT signaling as well? I'm hoping that would make your question easier to follow. Thanks! Dan
  5. Clarification for FFT implementation in FPGA

    Hi @subasheee, Congratulations! You are getting farther than many who have written to this blog. I often counsel folks not to use burst mode, such as you are using, but the pipeline mode instead. This is due to the added logic and complexity of properly setting up the valid and ready wires on the input, and the difficulty I personally have validating someone's design at a distance (i.e. via this forum). From what you've written above, it looks like you've solved and gotten past this problem. I'll hope so. You never told me the sample rate (or clock rate even) of the FFT. Are you running it at 1MHz? or 100MHz? (Best performance would be at 100MHz or so ...) But your question is about the FFT offset. You need to be aware that the first valid output from the FFT will not be the first sample out of the FFT, nor will it be the first sample one FFT length later. Look at the FFT manual--there's a flag that's used to note the first valid value from the FFT (and the last IIRC). You'll need to synch to that value, or you'll have these offset problems you noted above. As for whether or not you can buffer the incoming data ... of course you can! Will it help? That might depend upon what you are trying to do. I don't think you need to do this. Adjust the incoming valid signal instead, and the FFT should naturally buffer itself. Perhaps once you fill up the FFT you can give it a whole much of enable signals (I forget what the wire is called, CE perhaps?). You should be able to clock the Xilinx FFT at 100MHz or more. Your real driving factor in your computational delay is not the speed of the processing, but the speed of the input samples. As for resolution, an FFT is really a multi-rate signal processing tool. If you have samples coming in at 1MHz, but you want frequency resolution between 0-10 kHz, then you'll want to filter and downsample the FFT by a factor of (1MHz/20 kHz=) 50. Oh, back to resolution, don't forget that windowing can help. Hmm ... reading my comments above, they sound rather jumbled. Feel free to write back with more questions if this doesn't make any sense. Dan
  6. Clarification for FFT implementation in FPGA

    Hi @D@n I went through the link provide by @jpeyron for FFT which is informative. I was able to perform FFT on the synthesized sine signals using DDS compiler. I tried FFT for various frequencies of sine signals and their details are as follows. FFT implementation: Radix-2 burst I/O, Natural order, 16384, 1 channel, Fixed-point, scaled, truncation, Use 3-multiplier structure, Use CLB-logic Sine signal 1: sampling frequency: 100kHz, Signal frequency: 48.828Hz, FIFO size:16384, Transform length: 16384, Frequency resolution: 100kHz/16384 Calculated BIN index for peak value= 48.828Hz/(100kHz/16384) = 8 , XK_index for peak = 41 Sine signal 2: sampling frequency: 50kHz, Signal frequency: 48.828Hz, FIFO size:16384, Transform length: 16384, Frequency resolution: 50kHz/16384 Calculated BIN index for peak value= 48.828Hz/(50kHz/16384) = 16 , XK_index for peak = 49 DC signal: sampling frequency: 50kHz, Signal frequency: 0.7Hz, FIFO size:16384, Transform length: 16384, Frequency resolution: 50kHz/16384 Calculated BIN index for peak value= 48.828Hz/(50kHz/16384) = 0.23 ~ 0, XK_index for peak = 33 If you observe, even for DC signal (0.7Hz) the FFT bin provided by XK_index is 33 bins, if you subtract this offset for each signal then the Calculated BIN index for peak value matches with the peak value in FFT Signal 1: XK_index for peak = 41, XK_index for peak (DC) = 33, 41-33 = 8 Signal 2: XK_index for peak = 49, XK_index for peak (DC) = 33, 49-33 = 16 Signal 3: XK_index for peak = 33, XK_index for peak (DC) = 33, 33-33 = 0 So, my questions are 1. why there is a offset in XK_index values? am i missing some configuration setting ? 2. Can i buffer the signals to FIFO at low frequency (10kHz), unbuffer at high frequency 1MHz and carry out FFT ?. In this way i can reduce the FFT computation time without compromising frequency resolution. But, as the FFT block samples the signal at 1MHz, that means FFT block take the sampling frequency as 1MHZ ? Help is much appreciated. Regards, Subash
  7. Clarification for FFT implementation in FPGA

    Hi @jpeyron Thanks for your the link. I learned certain details about FFT and able to compute FFT using FFT IPcore V9.0. Regards, Subash
  8. Yesterday
  9. Zybo hdmi in demo project resolution issues.

    Hi @jpeyron, when I select 720@, It gives me bigger image and a part of the whole frame is displayed. It only gives perfect frame at 1080p settings. What did you mean by re-reacquiring? could please explain it. thank you- Shuvo
  10. VGA Pmod Tutorials

    Thanks for the feedback. I am planning to add my source code to GitHub soon. However, these two posts aren't really projects per se, but introductory guides. When I have some more substantial projects to share I'll post them.
  11. Z7 board upgrade PMU?

    Hi everyone. I am curios if there is a relatively simple modification I can do to increase available FPGA power, especially the 1V into the FPGA, on a Z7-20 board? Background, my problem is simple. I load a design into the Zynq that is expected to drain much more on the 1V supply then what the PMU inside the board can deliver, when loaded the LD13 led goes down almost instantly indicating that the supply rails can't keep up. This is easy to do, just try to use half of the Fabric at a decent frequency (200+MHz) and you will have run out of power. So I assume the PMU was dimensioned for the smaller FPGA on Z7-10 originally. Regards
  12. Hi folks! I'm thinking of buying an Analog Discovery 2. One piece of functionality I need is sniffing a serial connection between two devices. Not just a set number of samples - I mean capturing both TX and RX bytes to file/PC memory, for however many hours I need to catch my nasty little bug. The actual amount of data transfered is low. I'm actually utilizing maybe 30% of the capacity, at around 10kB/s TX and RX. On top of that, I'd like to add support for my custom software protocol that's running on the UART. Kind of like in wireshark you can see what a packet is, not just a plaintext context-less byte barf. If waveforms doesn't support this, I'm completely fine with writing an utility that, say, takes raw UART data over loopback TCP and formats it externally. Is this possible on the Analog DIscovery? What settings should I be using to make it work like that?
  13. FFT

    Hi all, i started to do a FFT from exact one sine wave with the XFFT(9.0). This works for the 32bit input signal, but for the 16bit input signal it seems not to work. By doing the FFT i would expect one peak in the frequency spectrum like i get in in the following picture: XFFT settings: - Architecture Choice -> Pipelined, Streaming I/O - Transform Lenght -> 256 - Scaling Options -> Scaled - Input Data Width -> 16 -> input signal from DDS 32bit - Input Data Width -> 8 -> input signal from DDS 16bit For generating a sine wave i use the DDS compiler at a Superious Free Dynamic Range of 96 dB and Frequency Resolution 100 Hz. The Phase Increment is in Streaming mode and set with a constant block to 4096. One sine wave is generated by 256 samples now (number_0 x2). If the settings are switched now for a 16bit sine input signal the FFT works not like i would expect. Maybe anyone has an idea? Thanky for any response!
  14. vivado interface

    how to use a spi interface as an ip in vivado please do comment
  15. Hi @Chetan The description files for the configurations where missing from the installer. The 16k digital buffer for AD is the 4th config. Descriptions are added to WF v3.7.12-2 Thank you for the observation.
  16. Unable to add modules to designs

    Hey Jon, thanks for the reply. I tried to attach the project, but it's way too big, 45 MB, and the forum site limits attachments to 1.95 MB. I used my code to implement the steps in the intc_example1 SDK project that I found in SDK somewhere, and my code is nearly identical and works perfectly with the phony (software generated using an XIntc register write) interrupt that they do. In the microblaze, there should (I hope) be an internal register where the status of the 32-bit address input and the 1-bit INT (or IRQ, or whatever they call it) input to the CPU can be read. If so, then I should be able to step through in a debug session and see if those ports are doing what they're supposed to. But this toolset and environment as well as the hardware designs are all brand new to me, so there is so much to learn on the way to getting a stupid interrupt.
  17. @attila Tested with the latest update. Now AD2 works Great for my requirement. Its a perfect combination of Analog and Digital scope now. Thank you. I should say that i am very happy with AD2 now. I observed that the latest update supports only 16x4K buffers in the device manager (is it because of Beta version?). Any idea when 16x16k buffers will be implemented for Logic analyzer.
  18. Hi Everyone, I was going to order an analog discovery 2 pro bundle but I qualify for the educational discount and wanted to figure out what accessories I really need. 1) Definitely wanted the BNC adapter board for $19.99 2) I can use any BNC probes with this, right? Like I could order them from Amazon, etc. or use existing ones that I have? 3) I need to measure current on a 5V circuit around 1-5 AMPS for a battery powered project. I bought two higher current .10 ohm resistors figuring I could connect probes against that to measure current and they would only slightly drop the voltage at these amperage ranges, but with a high resolution scope, I could go lower resistance. Or can I get probes that do this for me? 4) Do I need the Mini Grabber test clips -- what are they for? 5) What is meant by "The Analog DIscovery BNC adapter board does not have differential analog scope inputs? 6) Any other must have accessories? Thanks in advance for any help or input -- this looks like a great little device (and sniffing various protocols and simulating GPIO will be great)! MetroWestMA
  19. Qt on Zyboz7-20 via LX FrameBuffer to HDMI monitor

    So Qt can be used without X, that's interesting... Could you post the rootfs_config from your petalinux project (it should be in project-spec/config/). It might be helpful to some stuff I'm working on. Were you following any Xilinx or Embedded Linux guides or did you bake this yourself? Edit: Also, did you need to patch the Xilinx drivers or Digilent encoder?
  20. Unable to add modules to designs

    Hi @Android, I have not worked with interrupts in microblaze very much. I did not see anything wrong with the SDK code specifically. Here is a forum thread about interrupts. Here is a link that discusses using microblaze and interrupts. Can you attach your project? thank you, Jon
  21. Last week
  22. interfacing pmod cls with zybo

    Hi @Pujith Krishna, I realized that I had provided you with slightly incorrect code, the first line should instead be uint8_t setupString[] = {CLS_ESC, CLS_BRACKET, '3', CLS_DISP_EN_CMD}; but when I tested this for myself on the Zybo, I was unable to get the backlight to turn on. I was also unable to get the library for a microcontroller to turn on the backlight as well. I will look into this further, but comparing between the schematic and board itself, I'm not certain if the backlight can be turned on. I'll let you know what I find out. Thanks, JColvin
  23. Parity in chipkit wifire

    Hi @llonllon, I'm not sure if it is possible with the Digilent made boards. I was only able to get the Serial.begin(9600, SERIAL_8N1) to successfully compile for an Arduino Uno; I wasn't able to get anything to compile for any Digilent boards and couldn't find anything in the libraries to indicate the Serial.begin(speed, configure) function was available, so I'm surprised you got the Serial.begin(9600,8N1) to compile. I looked around for a bit online and the only definitive working thing that I could find to get this working was to configure the serial manually as described in this thread here: Thanks, JColvin
  24. Device Tree Failure Zybo 2017.2 BSP PetaLinux 2017.3

    It looks like you don't have the vivado-library repo. This typically happens if you downloaded the repo using the Download ZIP button on Github, which doesn't include git submodules. Two options: clone the base-linux repo with the following command line: git clone --recursive Or use you project: run the cleanup script in the proj folder, download the vivado-library repo from our github (you can use the Download ZIP button, it doesn't have submodules), and copy the vivado-library folder to the repo folder in your project. then re-run I recommend the first option, it will just make things easier in the long run if you use git. Whichever you choose, you should then run create_project.tcl, and you will see that same error again. Upgrade the IPs (it should work this time), and then close Vivado (don't forget to close Vivado). Then run the clean-up script in the proj folder (or just manually delete everything there except the cleanup scripts, release script, and create_project.tcl). Then run the create_project.tcl and all should work.
  25. I would like to know if in Arduino Ide with a chipkit wifire board is possible to configure the serial port with 8E1 (8 Stop bits, Even parity, 1 Stop bit) Serial.begin(9600,8N1) compile ok, but does not work
  26. Ready to use Linux Image for Zybo Zynq 7000

    Hello @dentiloque_roc, It also looks like Xilinx has the Petalinux downloads available here if you need those as well. Thanks, JColvin
  27. Ready to use Linux Image for Zybo Zynq 7000

    Hi @dentiloque_roc, Here is the Petalinux Support for Digilent Boards that has a newer link for the Zybo bsp . thank you, Jon
  28. XVC problem in Vivado 2017.4 with Zybo Z7-20

    Hi @rhb, Glad to here that it looks like the debian installation was successful. I have passed on your suggestions to our content team. thank you, Jon
  29. Unable to add modules to designs

    Hello again, I am a failure. I can't get interrupts working. I followed the example as closely as possible, given the differences. Xilinx support is ignoring me. Maybe you guys can get me out of this hole ... I have a block design with 1 interrupt controller, using only 1 interrupt source, which comes in from my external RTL module. Am I missing something stupid and obvious that everybody else knows about? Here is my super-simple test code:
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