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  1. Past hour
  2. Ciprian

    zybo hdmi to vga out

    Hello @Gourav, Unfortunately the issue could be in multiple locations and it's hard to determine this from the block diagram, it's probably a small bug either in the block design or in the HLS IP. Either way please send the archive with project so that I can look over it. Thank you -Ciprian
  3. zygot

    busbridge3: High-speed FTDI/FPGA interface

    What this project offers is about the best throughput for the FTDI USB 2 devices short of synchronous 245 mode. Digilent boards can't do this mode unless you modify the EEPROM settings and use the FTDI API; something that Digilent strongly discourages as you can brick your device, and hence your board if you make mistakes. I successfully did this for my Nexys Video but rarely take advantage of the effort that was involved; perhaps one or two projects. (I count learning experience as a positive project objective). Still were talking about 20-30 MB/s instead of 8 MB/s sustained average throughput which is rarely worth the effort. I still get a lot of mileage out of my ATLAS and Genesys Virtex V boards because they use the significantly more usable Cypress device and I can get 35+MB/s for large data transfers. More importantly, they have a number of modes that you can write HDL to support optimizing a particular requirement. For USB you should understand that throughput is not the only, or for some applications, the most important metric to creating a successful application involving an FPGA/PC application. Ahhh, sometimes change isn't all that wonderful....
  4. jcloiacon

    USB Host with Arty Z7 2017.4.1 Prebuilt Images ???

    Thank you for your quick response. My board clearly has some hardware problems. IC9 caught fire when I plugged the board in today, and the former input to IC9 is found to be short to input power (12V). I suspect regulator IC24 has failed. USB device has been successfully enumerated by shorting IC9 pin 1 to IC9 pin 5, and running off 5V USB in power.
  5. zygot

    ethernet communication with pc

    I forgot to mention that unlike some interfaces you can download copies of the Ethernet standards which provide (almost, they won't provide code to implement a robust PHY interface in HDL for you FPGA board for instance) all of the information that you need to implement a workable application. Well you can get the standards for others if you pay to become a member of the organization that maintains them. I have nothing against using wikipedia, I do so frequently, but it's not always the best, or most reliable, source for information. Really, parsing the packet structures for Ethernet is not a big deal or close to the being a significant part of the work involved in creating a usable application.
  6. jpeyron

    How to restore FT2232 EEPROM back to factory settings?

    Hi @mishu, I sent you a PM about this. thank you, Jon
  7. Today
  8. zygot

    ethernet communication with pc

    @PhDev Perhaps you'd be willing to provide a simple application to the Project Vault demonstrating your positive experience with these cores that come in the form of pre-compiled netlists. It's been my experience that becoming invested in such IP with very limited documentation is, in the long run, not very productive. There are, obviously, quite a few people out there who just need a quick and dirty solution to solve a problem and don't have long term interest in developing standard Ethernet based projects.
  9. aeon20

    Confusion regarding Xilinx cable drivers

    What exactly are the "cable drivers"? Guides such as https://www.xilinx.com/support/documentation/user_guides/ug344.pdf and https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug973-vivado-release-notes-install-license.pdf also don't clearly state what it is. Are they loadable kernel modules? Device files under /dev? Are they user space utilities? This is not clear to me. Running the install script prints out some information that doesn't really help me either. For an FPGA beginner like me that can't get this to work, and doesn't even know how the "cable driver" system is intended to work, and with documentation being scarce and sometimes misleading (e.g. referring to readme files that don't exist), this is hard. What should a functional system that has the "cable drivers" look like? What (if any) cable driver related prosesses should be running? What (if any) loadable kernel modules should be present on the system? What does a successfully detected Digilent FPGA device look like when listing USB devices using lsusb? For a modern Linux distro, it is even needed at all to install the cable drivers, with a modern kernel? Again, this question only makes sense once I know what the "cable drivers" are. Are they user space or kernel space related? I've also been told this before: What exactly is the "Digilent runtime", and how does it relate to the cable drivers? What install.sh files should I run? There are several available after installing Vivado. I'm an experienced Linux user, if someone could walk me through this that would be very nice and helpful.
  10. mishu

    How to restore FT2232 EEPROM back to factory settings?

    Hi there, As many users, I have a problem with my JTAG SMT3 device, it seems to stop working and to be seen in Vivado, for unknown reasons at this time. I would like to make it work again, so please maybe somebody can send me a PM message with the steps needed to be done to achieve this. Thanks, M.
  11. Kris Persyn

    Digital Twin

    Hey, For a quite challenging project I am planning on using a zybo z7-20 to drive immersive visuals on a HDMI display (probably this monitor Lenovo L27i-28). Simultaneously I would want to collect sensor data through digital pins (digital signals are provided by an external uP) and also interface with matlab (used for speech recognition) via USB. My question thus is: Is this baby powerful enough to deal with all this load? Kg, Kris
  12. I can also add that I've now tried a different physical computer with a fresh Debian 9.7 install. I get the same result: "No devices detected on target". I'm not using an emulated USB controller. The board "partially" shows up though, just as before (same screenshot as above, but identical results, just didn't bother making a new screenshot when there is nothing new):
  13. Cristian.Fatu

    USB Host with Arty Z7 2017.4.1 Prebuilt Images ???

    Hello, We have booted using the bsp you specified. We have used external power (and suggest you to do so), having set the JP5 to REG. The dmesg messages seem similar in our case to the ones you posted. Also, the first item listed by lsusb is identical to yours. Obviously we cannot plug the USB device you use (class-compliant MIDI device). We have tried an USB Flash drive, properly recognized as mass storage device. So, everything seems to be OK on our side. Please read chapter 8 (USB Host) from the reference manual. There are some details about how the USB port behaves. Maybe this is useful for you.
  14. kotra sharmila

    sdsoc_opencv error

    hi, yah i removed that function and doing modifications insert haar cascade but still gort th errors filter2d_cv.cpp
  15. Danny Armstrong

    Pmod library not found in Vivado 2014.4

    Hi Jon, "Add IP" button works! Although I have not got time to implement an FPGA design yet today, I believe it will work with 2014.4, with proper external connection and Pmod constraints. I forgot totally the "Add IP" button, when the board tab did not show the Pmod modules. Thanks Jon. Best Regards, Danny
  16. Ciprian

    Hdmi out from zybo

    Try adding this: &i2c0 { clock-frequency = <100000>; status = "okay"; }; Here: <petalinux_project>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi -Ciprian
  17. bogdan.deac

    sdsoc_opencv error

    As I mentioned here, you cannot use cv::VideoCapture() function to acquire a video stream from the webcam. For this reason you must to start from a sample project that implements video stream acquisition from HDMI/MIPI.
  18. StuE

    Maximum continuous sample rate

    @attila as you suggested I used the python example. For some reason it wasn't working; wouldn't stream off the buffer. Something I did randomly made it work but I'm not entirely sure what I did (although since it's working it doesn't really matter) One thing, though. Looking at the waveform of the data stream running at 100kHz or 200kHz, I can see that there ARE some missed samples. I think I can work around these, but it's worth noting. I did wonder whether I could split my signal across the two AnalogIn channels and pull data down at different times to characterise how much is dropped but haven't tried it yet. Thanks for the advice re doubling the buffer size, that's the first thing I'm going tomorrow while my laser warms up. Thanks for your advice.
  19. @attila thanks, I actually found it after digging around for a while. Sorry to have asked a question without looking into things myself first.
  20. This link: https://forum.digilentinc.com/nec-xhci. doesn't lead anywhere. I tried removing the "." at the end, same.
  21. aeon20

    How to install and use djtgcfg?

    I'm sorry, I meant that the link you posted in the other thread doesn't go anywhere. I don't know why I replied here, I got confused.
  22. jamesW

    PMOD MTDS text font sizes

    Ah, yes - thanks. I should have paid more attention to the manual! Thank you for looking into this and providing the answer.
  23. MSchleeh

    Pmod MTDS Display dark Display after 10-20min

    Hi @jpeyron I created a custom application, in which i use the PmodMTDS_v1_0 library to load Bitmaps from the micro SD card onto the display. The other parts of my project still works as expected, even when the display screen goes dark. Today i also tested the display with the Demo "MyDispDemo1.cc" and still get the same effect. (Works fine for 10-15 min, before the screen goes dark) Are there any known issues of the MTDS, that may explain why the display screen goes dark after a while? thank you for your help, Maurice P.s Additionally I installed a ferrite choke around the connection cable between the display and the Zedboard to minimize the interferences of high frequency noises.
  24. Lakshmi Tejas M A

    Error with enabling DIO channel

    Hi @attila thank you on checking on it. We think analog discovery 2 is getting disconnected because of noise entering USB. Not sure. wanted to know if we can close the device which is opened and reopen in this scenario. because WF is not open and some function are running but in middle this scenario is created. This doesn't happen every time. ty LT
  25. kwilber

    artix nexys 4 and keyboard

    There is a companion website for Pong Chu's books here. You can find the source code from the book there. Part IV of the book covers video systems and the VGA interface.
  26. gummadi Teja

    artix nexys 4 and keyboard

    could you please provide a source code for the keyboard interfacing using nexys4 board and vga synchronization sir.
  27. gummadi Teja

    artix nexys 4 and keyboard

    Thank you sir ,(FPGA Prototyping by SystemVerilog Examples: Xilinx MicroBlaze MCS SoC Edition by Pong Chu.) how to get a solutional manual for this book. but we want to implement on monitor using vga synchronization.
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