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  2. Hi @danny, Before I can answer your question I need to know if you are planning on using it in an embedded linux or not. The solution might vary depending on this. -Ciprian
  3. Today
  4. @Dan, I managed to find the 'average' option rather than 'decimate' which has stopped high frequency noise showing up in the spectrums, giving a more reasonable noise floor.
  5. Then I misunderstood the PCB schematic. I will try out! Thanks!.
  6. Thanks Colvin ! After I posted and shut down the system and re-started all things fell in place. Possibly in the first instance I was changing too many parameters on the fly with both Streaming and WavGen running and the system became unstable. Now its fine. I would like to make make all my settings on the right side as Default settings to be pulled up when the WaveForms live loads .. I think Profiles are stored in flash. Will selecting Log on Booting do that ? Also I get a "Error Starting or Running " if I try to log to a SD Card. Its a Sandisk 32GB MicroSD formatted for FAT32. The filename is there but filled with gibberish.
  7. HI @Ryu, Unfortunately we are not familiar with building Xillinux-2.0 and therefor I can't really help you to the full extend of what you need, you might be right regarding the frequency, but not the right one. The input frequency is used for generating the internal frequencies of the PS which in turn generates the frequencies of the PL, the HDMI is handled in the PL which means that there might be some issues there. Either way there is a external clock on the board which provides the input frequency for the PS (schematic page 10) which is 33.333 MHz. You should not change the settings in the PS files which describe the input frequency because those are used to set the PLLs in the PS which generate all the other frequencies, basically if you change that one all of them change. The way you should go about this (if you really want to change the input frequency, although that's not the were your problem is) is by using Vivado to change it, within the PS configuration, which should automatically reconfigure all the clock at build. Regarding your actual issue, each Linux project has a underlying Vivado project which describes the HW used by Linux, you need to create that project for the Zybo Z7-10 first and then base you Xillinux-2.0 build on it.... Like I said we don't have experience with this, you will need to contact Xillinux for it. For the UART make sure that the right settings are used baud, parity, etc. -Ciprian
  8. From ug585 pg. 310: For DDR3 DCI calibrates the termination impedance and not the driver impedance. Series termination resistors is a form of drive impedance adaptation.
  9. Hello @mukunda, Did you manage to find out the problem?
  10. Quoting from What makes you think it is only for FPGA configuration? Instantiate the AXI Quad SPI IP and map it to the pins called out in the RM and schematic.
  11. Yes, I've already give him the link with some Reference projects which contains also pdf files with documentation for each project, and it explains very well the Uart component which is used with the PmodRS232 (in Interface Reference Component from the Reference projects). The info is there...
  12. Hi @abcpt The two and four point measurements are hardware and not software facts. The WF Impedance Analyzer can work with four point setup. The current flow is between Wavegen and GND. You can connect the Scope 1+/2+ to DUT and 1-/2- to Resistor GND side. Such setup is also used on the IA Adapter.
  13. Hi @Barry I have just tested the installer with a standard user. This requires elevation and after entering an admin user credentials it installed correctly.
  14. Hello, As it stands, the current impedance analyzer software is made for two point measurements meaning the wavegen and the pick up electrodes occur at the same terminals. I would like to know if it is possible to change the software to perform stimulation and measurement at different pins. Kind regards, André
  15. Hi, I want to develop a simple subsystem that is shown on the picture below. Basically, I need one producer that would generate a picture(s) and one consumer that would display the picture. The consumer is easier part, it's VGA block that reads the pictures from the memory. I want to use a bigger resolution, so I cannot use BRAM and I have to go for DDR. I'm planning to use MIG for this job. The question is whether I can configure DDR as a dual-port ram (one port for generator and one port for consumer). Is it possible? If not, I think that I have to go with multi-master bus, so the consumer is another master on the bus... Other memories that Nexys A7 has are too small (and I guess also to slow). Any help is appreciated. Thanks, Dannny.
  16. Pier

    Zybo z7 evaluation

    How could be possible to implement the design shown in attached video? in the video the arrays are 600 samples each, but i would go for bigger arrays as possible and 24 or 32 bit values i'm planning to use a zybo z7 board exxample.mp4
  17. BASYS3 + PMOD Breadboard + Analog Discovery 2. It was just a hack, so the table was a quick formula in a spreadsheet, yes, I assume the + and - sides are both rounding towards zero causing some asymmetry, but with 11 significant bits that should be somewherere about -60dB at a guess. Most of the noise is just the shoddy physical implementation. Flying wires on a breadboard, on PMODs, just the shielded wires on the AD2 and so on. If I leave a wire hanging around it will pick up most the noise too, maybe 6dB lower than on the channel that is under measurement. This was just a quick experiment, just using the 100MHz clock rate. If I use a slower clock (e.g. update only every 8 cycles so 12.5MHz) the noise floor actually drops a lot.. Also using the AD2 on a different laptop to the one programming/powering the FPGA removes a lot of noise too. I assume that this is due to voltage drops and noise on the USB cables. Plenty of room for experimentation and improvement.
  18. I noticed that on the Cora dev kit there are series termination resistors on the address and control nets and wondering why. Does not Bank 502 not have the ability to use DCI to create the 40 ohm output impedance? Why are the VRP/VRN resistors 80 ohms instead of 40? Thanks, Sean
  19. Hi @DaveS, I'm glad a different cable worked, though as to why this is the case (or why different boards work with different cables) I do not know. I believe (I haven't gotten confirmation) that Digilent changed out the micro B USB cable that we sell to one that was tested to work consistently, though I have personally been using the same cable that was found to problematic for the last 5 years without any issues. So I'm glad you were able to find an easy solution. Thanks, JColvin
  20. Yesterday
  21. @MikeA I just connected a JTAG-HS3 to J15 of the Zed board and Vivado 2019.2 was able to detect both the ARM and PL on my Windows 10 PC. It's rather odd that Adept can see the 7015 on your board but Vivado cannot. I looked at the PicoZed schematic and the JTAG lines are referenced at 3.3V with 4.7K pull-ups to 3.3V. Do you have any additional pull-up or pull-down resistors on your board? What about series resistors or buffers between the 14-pin header and the JTAG lines? One other thing: are you supplying power (probably should be 3.3V) to pin 2 of your 14-pin JTAG header? Thanks, Michael
  22. Hi, thanks for the reply. I tried ignoring these and nothing is displayed or has any message. I cant activate the camera also nor displays any message on the screen. Could you please help me with this?? Could you please give me link for four cameras. I have checked with the link here, I cant find hls code ( --Download the most recent release ZIP archive ("FMC-Pcam-Adapter-2018.2-*.zip") from the "repo's releases" page.-- I cant find the code. also this says out of date synthesis. Is that okay to run the code ??
  23. Hi @[email protected], The 4 camera connection is the same GitHub link that is provided in this specific post here: The dual camera GitHub link is available here: The warning and 2 infos/tasks I presume you have (the warning and 2 infos I have on my 4 camera FMC project are: warning: this statement may fall through [-Wimplicit-fallthrough=] ZedBoard_FMC_Pcam_Adapter_DEMO_bsp line 246 C/C++ Problem Info 1: #pragma message: For the sleep routines, Global timer is being used xtime_l.h /ZedBoard_FMC_Pcam_Adapter_DEMO_bsp/ps7_cortexa9_0/include line 89 C/C++ Problem Info 2: here ZedBoard_FMC_Pcam_Adapter_DEMO_bsp line 247 C/C++ Problem) can likely be ignored as they are informing you of details that are directly built into the Xilinx material; i.e. the first info message is simply repeating line 89 in xtime_l.h verbatim. I am a little confused on your tasks. Each of the ports on the FMC Pcam adapter already use the same power enable, PWUP. Additionally, the purpose of the demo is to facilitate the MIPI and CSI-2 communication. The D-PHY was already taken care in the layout of the board. Thanks, JColvin
  24. zygot

    PMOD I2S2 IP

    You are probably correct about that. But if you walk over to the desk of one of your compatriots who's been around for a while ( not raising the subject of age ) they will remember the old days when FPGA boards, even those from Digilent, came with one or more RS-232 ports. This was way before ARM was born but Digilent did provide code for a UART that worked well enough to include in its support. You may have to sit through a few boring discourses but the code is there, somewhere.
  25. zygot

    PMOD I2S2 IP

    I mentioned ZYNQ because it's not clear what FPGA board the person asking for support is using. You don't need to touch AXI for your ZYNQ designs. I've posted a few alternatives. The Fun with Phasors demo is but one approach. I use a UART in my designs a lot and have found that I do need a wide range of serial settings. While I don't do much in the way of RS-232 is is still a viable alternative to RS-422 for some applications and it's nice to have a UART that can function in such an environment.
  26. @zygot, The AXI-lite wrapper is actually just a lite wrapper around a pair of FIFOs and some lighter UART cores. Indeed, I use those UART cores without AXI all the time. (Actually, I rarely use AXI myself ... which makes it all the more fun every time someone let's me know that my AXI stuff "just works".) Not only that, after building the original pair of cores (rxuart.v and txuart.v), I quickly determined that I had very little need of a UART core that supported changing baud rates or anything protocol other than 8N1. Therefore I have another pair of cores there, rxuartlite.v and txuartlite.v, that are even simpler yet. These can be subcomponents of the AXI-lite core linked above or indeed used independently, as I often do. If you don't need AXI, then don't use it. Your call. On the other hand, if you are using a Zynq (an unsaid background to this post), then AXI is almost a requirement. Dan
  27. zygot

    PMOD I2S2 IP

    @[email protected] I looked at your IP core link. I looks pretty nifty but I have a question. Why in the world would anyone want to put an AXI bus between their logic and an HDL UART? In particular, why would they do that for a soft processor? It seems like hitching a trailer with a couple of mules to the back of your ATV in case you get stuck crossing a creek. Just excess baggage. Anyway, I'm not sure that an AXI-UART is going to simplify life for anyone needing an HDL UART core. For ZYNQ designs the PS has 2 UARTs. Almost all ZYNQ FPGA platforms connect one of them and the other can be connected to PL pins without an HDL UART instantiation. It is a nice demo of your AXI work however. I do think that the link might steer people to a useful discussion on the subject of the AXI bus. I'm a bit less sure of posts to this forum that could be viewed as trolling. Perhaps Digilent needs a special AD warning symbol. RS-232 needs to be designed to work with equipment that might have a significant baud rate error. What's the baud error that your UART tolerates? +/- 15%?
  28. I was able to solve the problem. In the implemented design you need to ensure that the Vcco column doesn't show any 2.5V in i/o bank 35. Mixing LVDS_25 and TMDS_33 in the same bank is possible.
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