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  1. Today
  2. BogdanVanca

    Configuration: XADC

    Hello @theAsker, To accommodate bipolar signals, your analog input must be configured to bipolar mode. Bipolar mode is selected by writing to configuration register 0 from control registers. From what I found, this would be the third register from the 40h to 42h configuration registers (check table 3-4 page.43 from the attached document). I never tried to reconfigure the xadc from SDK, but I'm quite sure that you are not looking into the right header file. Please check this one : xadcps_hw.h. This header file contains identifiers and basic driver functions (or macros) that can be used to access the XADC device through the DeviceConfig Interface of the Zynq. If you go to line 281, you will find this : #define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */. Try to work it from here and tell me if you obtain some results. I am looking forward to hearing from you. cheers, Bogdan Vanca ug480_7Series_XADC.pdf
  3. theAsker

    Configuration: XADC

    Hello everyone! I bought the Zybo Z7-20 board, and my aim is to convert 2 analog signals to digital signals via XADC in an simultaneous wy. For this I want to use the bare-metal programming in bipolar-mode (I am using Vivado IDE & SDK 2017.4). In the library xadcps.h I found nothing about the configuration to bipolar mode. Can anyone help me, telling which functions I need and how do I have to configurate them? Is there an example existing? Thanks for all help!
  4. A time gap occur if the attached vi, also the data is overwritten. I want to acquire many data continuously in LabVIEW without time lag in Analog Discovery 2. Acquire N Scans baba2-(ex).vi
  5. bogdan.deac

    Board definition file of Zybo Z7-20 for SDx

    https://github.com/Digilent/SDSoC-Zybo-Z7-20
  6. theAsker

    Program code on PetaLinux

    I want to map the XADC from user space. I use for this: #define START_ADDRESS_XADC 0x43C00000 int fd = open("/dev/mem", O_RDWR|O_SYNC); char *ptr = (char *)mmap(NULL, 0x10000, PROT_READ | PROT_WRITE, MAP_SHARED, fd, START_ADDRESS_XADC); when I want to write now to the registers like: ptr[ 0x40 ] = 0x8200; And I read the address before writing, it returns a 0. After writing, also a 0. So I think, a don't have permissions to write to this address. Why and how do I fix that?
  7. Poseidon

    Patterns 1

    Hi @attila, Thank you for your time. I've written my code using the SDK. For a time it was working then everything suddenly didn't work. What I noticed is when I do a FDwfDigitalOutInternalClockInfo it tells me the internal clock is 0. How do I set the internal clock? I can't seem to find the API in the SDK manual.
  8. Yesterday
  9. ArKay99

    Board definition file of Zybo Z7-20 for SDx

    I think you mean the .pfm file referenced in the custom platform generation tutorial video? The ones from Xilinx are at Xilinx\SDx\2018.2\platforms. However, I too would like to know where the Digilent ones are that are referred to in the video at 1:11 here https://www.xilinx.com/video/soc/sdsoc-custom-platform-generation.html I also, have not been able to find them...they may not exist which would mean they have to be created from scratch as a custom platform.
  10. fandrei

    Zybot + USB WIFI Adapter (RALink 5370)

    I wonder if you can share any up-to-date instruction how to do that?
  11. Piotr Rzeszut

    Acquiring data until an event occurs

    I think triggering in normal mode on that data with correct trigger position i.e. long enough pre-trigger time/correct position. See Mode: record
  12. Hi. I have a Digital Discovery debugging an old microprocessor, so I have 16 address lines in a bus and 8 data line in a bus. What I would like to know is what the microprocessor is doing when it decides to access a particular address. So I'd like to like to click Run, start acquiring data, and then have it stop when the bad address is accessed, so that I have the data leading up to that event. It's sort of like a trigger that stops acquisition instead of starting acquisition. Is there a way to do this? Thank you, Bob
  13. Piotr Rzeszut

    Python digital continuous record (AD2/DD)

    Well, I figured out somehow following code: """ DWF Python Example Author: Digilent, Inc. Revision: 11/24/2014 Requires: Python 2.7, numpy, """ from ctypes import * from dwfconstants import * import math import sys import time import matplotlib as mpl import matplotlib.pyplot as plt if sys.platform.startswith("win"): dwf = cdll.dwf elif sys.platform.startswith("darwin"): dwf = cdll.LoadLibrary("/Library/Frameworks/dwf.framework/dwf") else: dwf = cdll.LoadLibrary("libdwf.so") # declare ctype variables hdwf = c_int() sts = c_byte() cdevices = c_int() devicename = create_string_buffer(64) # print DWF version version = create_string_buffer(16) dwf.FDwfGetVersion(version) print "DWF Version: " + version.value #enumerate and print device information #4 for AD2 dwf.FDwfEnum(c_int(0), byref(cdevices)) print "Number of Devices: "+str(cdevices.value) # open device print "Opening device:" for i in range(0, cdevices.value): dwf.FDwfEnumDeviceName (c_int(i), devicename) if devicename.value == "Digital Discovery": dwf.FDwfDeviceOpen(c_int(i), byref(hdwf)) print "\t", i, " : ", devicename.value if hdwf.value == hdwfNone.value: print "failed to open device" quit() print "Configuring Digital Out / In..." dwf.FDwfAnalogIOChannelNodeSet(hdwf, c_int(0), c_int(1), c_double(3.3)) time.sleep(0.1) dwf.FDwfDigitalInReset(hdwf) #dwf.FDwfDigitalOutReset(hdwf) dwf.FDwfDigitalInInputOrderSet(hdwf, c_bool(False)) # generate counter #for i in range(0, 8): # dwf.FDwfDigitalOutEnableSet(hdwf, c_int(i), c_int(1)) # dwf.FDwfDigitalOutDividerSet(hdwf, c_int(i), c_int(1 << i)) # dwf.FDwfDigitalOutCounterSet(hdwf, c_int(i), c_int(1000), c_int(1000)) #dwf.FDwfDigitalOutConfigure(hdwf, c_int(1)) # set number of sample to acquire nSamples = 200000 rgwSamples = (c_uint8 * nSamples)() cAvailable = c_int() cLost = c_int() cCorrupted = c_int() iSample = 0 fLost = 0 fCorrupted = 0 # in record mode samples after trigger are acquired only dwf.FDwfDigitalInAcquisitionModeSet(hdwf, acqmodeRecord) # sample rate = system frequency / divider, 100MHz/100 = 1MHz dwf.FDwfDigitalInDividerSet(hdwf, c_int(100)) # 16bit per sample format dwf.FDwfDigitalInSampleFormatSet(hdwf, c_int(8)) # number of samples after trigger dwf.FDwfDigitalInTriggerPositionSet(hdwf, c_int(0)) # 50% # number of samples before trigger dwf.FDwfDigitalInTriggerPrefillSet(hdwf, c_int(1)) # enable data compression by select used lines dwf.FDwfDigitalInSampleSensibleSet(hdwf, c_int(0x00FF)) # trigger when all digital pins are low dwf.FDwfDigitalInTriggerSourceSet(hdwf, trigsrcNone) # trigger detector mask: low & hight & ( rising | falling ) # dwf.FDwfDigitalInTriggerSet(hdwf, c_uint(0xFFFF), c_uint(0), c_uint(0), c_uint(0)) # begin acquisition dwf.FDwfDigitalInConfigure(hdwf, c_bool(1), c_bool(1)) print "Starting record" mpl.rcParams['toolbar'] = 'None' ax1 = plt.gca() while True: dwf.FDwfDigitalInStatus(hdwf, c_int(1), byref(sts)) dwf.FDwfDigitalInStatusRecord(hdwf, byref(cAvailable), byref(cLost), byref(cCorrupted)) iSample += cLost.value iSample %= nSamples if cLost.value: fLost = 1 if cCorrupted.value: fCorrupted = 1 iBuffer = 0 while cAvailable.value > 0: cSamples = cAvailable.value # we are using circular sample buffer, make sure to not overflow if iSample + cAvailable.value > nSamples: cSamples = nSamples - iSample dwf.FDwfDigitalInStatusData2(hdwf, byref(rgwSamples, iSample), c_int(iBuffer), c_int(cSamples)) iBuffer += cSamples cAvailable.value -= cSamples iSample += cSamples iSample %= nSamples #print sts.value, " ", iSample if sts.value == DwfStateDone.value: break if not plt.get_fignums(): print "CLOSED" break ax1.clear() ax1.plot(rgwSamples) plt.pause(0.0001) dwf.FDwfDeviceClose(hdwf) print "Recording finished" if fLost: print "Samples were lost! Reduce sample rate" if cCorrupted: print "Samples could be corrupted! Reduce sample rate" f = open("record.csv", "w") for i in range(0, nSamples): iAlign = (i + iSample) % nSamples # first sample in our buffer is at iSample index f.write("%s\n" % rgwSamples[iAlign]) f.close() But quite often I get reading with nasty glitches: The signal is generated using Analog Discovery 2. For a connection I am using High-speed inputs 0..7 of DD and DIO 0..7 for AD2. Configuration of AD2:
  14. First of all, I'm not sure if this is the right forum for this, as this is a question about tool installation and usage. If it is in the wrong place perhaps a mod can move this or provide a suggestion as to the right place to ask this. I had SDoC 2018.1 installed along with Vivado and Vivado HLS and subsequently installed 2016.4 Vivado, SDK, and Vivado HLS to work with the OOB project for my Digilent board. I got that working and was able to go through much of the project all the way to debug and program and verify with the SDK and the contained C code. A few days later I wanted to start utilizing some of the example projects and the xfopencv libs, but was unable to download them. I saw that SDoC 2081.2 was released, so I downloaded and installed that and upon starting SDoC I started having the problem. It appears that when changing focus between the different container objects in the gui that the ui becomes unresponsive for about 20 seconds with the spinning blue circle. Then it will get focus and I can nav around in the container, but after I close it and try to select a menu item or a tab in another container, the ui can't get focus for another 20 seconds. This is really frustrating as it makes even setting up the environment futile. I then fully uninstalled SDoC 2018.2 and re-installed it with a fresh download but got the same issue. Keep in mind that 2018.1 worked just fine. I then did a full uninstall of 2018.1 and 2018.2, then another fresh download and install of 2018.2 with no 2018.1 on the computer. I still observe the same behavior. I should mention that Vivado 2018.2 and the SDK being launched from the Vivado menu seems to work just fine. After a few days of looking around for an answer to this, I've come up short so I'm asking for advice and or help here. I applied for a ticket at the Xilinx Service Portal, but it may take a few days to get through the noise there with no guarantee I will get help due to my non-corporate email address, although I do have an SDoC license. I'm also thinking that if it's a problem with the SDoC ui interacting poorly with eclipse that may be another issue. I have inspected my environment variables, license location, and viability and SDoC does report the license is available in the console when I start it...although sometimes it takes a while to establish that. My internet connection is solid and fast with 100 mbps up and down.
  15. Hi, I want to make an enumeration, with filtering only Digital Discovery devices. Official documentation (pdf file) says nothing about enumfilter values. In files with constants only three values are listed: #ENUMFILTER enumfilterAll = c_int(0) enumfilterEExplorer = c_int(1) enumfilterDiscovery = c_int(2) I have figured out filter for AD2 devices to be 4, but i am not able to find any filter for DD. Also I have noticed that some SDK documentation is missing or very limited.
  16. I recently ported two tutorials for Vivado 2017.4 - the actual Arty-Z7 examples are not fully ported to that version. They are available on github: https://github.com/juergenRe/Arty-Z7-XADC-VHDL https://github.com/juergenRe/ArtyZ7-20-CDMATutorial The XADC demo is originally written in Verilog - because I am usually using VHDL I took this as an occasion to dig deeper into that example. Also, I added a simulation bench (which normally is the first step when creating custom logic) The second project is a port from Xilinx UG1165 tutorial using the centralized DMA IP. This was a bit tricky due to differnt RAM size and a strange error in Vivados connection automation (see that post: Wrong connection on AXI, evtl. somebody might provide ans answer?). I recommend working through UG1165, you'll learn a lot about how to use the SDK even sometimes you'll need to guess how to adapt to the Arty. There are also covered a lot of things concerning IPs and IP Integrator, so I feel, the additional time spent there is worthwhile. Please note that repositories might contain issues, I did not test to the full extend. If theres someting missing, please feel free to add or correct or leave me a message.
  17. MauroChimenti

    Petalinux-Zybo-Z7-20 project fails to build and fetch components

    Hello, I tried to upgrade python3 and git, but nothing is changed: Actually I have: python3.5 3.5.2-2ubuntu0 amd64 Interactive high-level object-oriented lang git 1:2.7.4-0ubunt amd64 fast, scalable, distributed revision contro The global git config is surely a clean empty one, because the VM is brand new (uhmm .. an empty git global config could be the issue). The global and system git configuration were empty. I created a base configuration but nothing is changed. --------------- .gitconfig ---------------------------------- [user] name = Mauro Chimenti email = mauro.chimenti@gmail.com -------------------------------------------------------------------- I'm sure the issue is little configuration detail somewhere. In the Xilinx forum, just like here, no one reported my issue and all describe the same steps i did. I started from a brand new VM (several times), so I really don't understand what I missed. If I try to build the Arty-z7-20 project with the 2018.2 (or 2018.1) petalinux version, i see all fetches go ahead correctly, compile 99% and finally stops with an expected insanity kernel error. All version older than 2018.1 fails (i tried 2017.4, 2017.3, 2017.2 and 2016.4) dpkg list.txt
  18. K, so it looks like you have it nailed down to petalinux 2017.4 not working on your system (since the xilinx-zc702 also seems to fail). Also, whatever issue you are running into seems to have been resolved in 2018.1. I don't like punting people to other places, but at this point I'd recommend reaching out on the Xilinx forums and seeing what they have to say. You should also try opening a support ticket with them. The fact that it seems to have been fixed in 2018.1 suggests that someone over there knows what is going on. Be sure to provide error.txt to them. We can keep trying here too... It looks like yocto has generated an invalid git command for the 5 repos that throw errors. The command tries to fetch a remote branch directly onto the current branch, which is not allowed. Perhaps the git repo is in a different state than yocto expects for some reason. Another possibility is that your git configuration is not compatible with the version of yocto present in 2017.4. Can you provide ~/.gitconfig, and any other git configuration files you might have on your system (you might want to strip them of personal info, your call)? Also, what version of git are you using?
  19. sbobrowicz

    Can't get Digilent/Petalinux-Zybo-Z7-20 to work

    Any flickering on the LEDs, or does DONE go low? What branch and commit are you checked out at? For comparison, try downloading the BSP from the release tab in github and building using that flow.
  20. sbobrowicz

    Program code on PetaLinux

    @theAsker Please provide more information about what you mean when you say you cannot write to the XADC registers. Are you receiving an error? Also, I'm not certain your addresses in the code above are correct. For one, in the commented out line where you try to enable the core, you write to address 0x02, which doesn't make sense since the registers are 32-bits (they should all be 4-byte aligned: 0x00,0x04,0x08,0x0C...)
  21. Last week
  22. William Smith

    Platform studio

    Image processing deals with the raw image which may include editing and adjusting it as well. Whenever I get into problems like this, I always consult with Canon Printer Tech Support and they bring me out with solutions.
  23. Hi, Using python script I want to constantly collect digital data form 6 lines (so 8 lines would be sampled) with a rate of 1MSPS, with transfer to the PC. I have read: And I am not sure if I should use record mode with data compression or scan screen mode. I suppose record mode would be best, but I don't know how to set unlimited number of samples for digital record (there is no function FDwfAnalogInRecordLengthSet for Digital inputs), as the only method to set number of samples is calling dwf.FDwfDigitalInTriggerPositionSet and dwf.FDwfDigitalInTriggerPrefillSet... At the other hand, will scan screen mode allow the sample rate of 1MSPS to be transmitted to PC? I would be grateful for any suggestions @attila. I have searched through the forum but only found mentioned discussion and some materials related to analog acquisition....
  24. Update for @attila at 4:20pm on 6/24: I found out the issue. It was an error on my part. I am sorry for any un-needed effort on solving this. Thank you! Hi @attila I am using the Digilent Electronics Explorer Board. I did check the software version of WaveForms and it is v3.8.2 and I am on a Windows 7 64-bit machine. My apologies I did not include this information earlier.
  25. Header J6, should MOSI and SCK be reversed?
  26. Piotr Rzeszut

    Using Digilent Analog Discovery in Orange Pi PC PLus

    But where from the TL431 takes power? USB of Orange Pi or external power supply? I have AD2 so maybe there is an issue with AD1?
  27. I'm using AD (1), but power supply is not a problem because the isolator use an independent power supply with TL431 and BJT to supply 5V. On windows 7 x64 AD + isolator works well, just with less update because of the USB 1.2 limitation (12mbps).
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