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  1. Today
  2. Ah, thank you @kwilber. That explains why the XADC error shows up at all, but I'm guessing that the XADC part may be a red herring on what is actually going wrong? I seem to get this error even when I completely disable the MIG ip core that I use in my custom VHDL code, but the error goes away when I comment out the port map for either my custom code or microblaze completely.
  3. This link explains why the xadc is being included when you use the mig. https://www.xilinx.com/support/answers/51687.html
  4. Hi, I'm trying to create a project that uses custom HDL code to write to the DDR2 memory on my nexys 4 ddr, and then ultimately uses microblaze to read the memory out over UART. As an intermediate step, I created a vhdl "wrapper" to connect microblaze to ram and instantiate my custom vhdl. At first I want to leave the signals from the custom VHDL that go to ram open/disconnected. My plan was to later add a conditional logic statement that decides which is connected. When I try to leave the pins to memory "open", or even connected to junk placeholder signals I created, I get an implementation error: This doesn't make any sense to me, especially as I am not trying to use the XADC anywhere in the project. I saw this article about leaving pins open, but I believe I followed the solution they have listed but still get the error. I've attached the project folder for this in case anyone may be able to take a look. Since the file is too large to attach, it is at this google drive link. Thank you, Daniel
  5. After downloading and looking at WaveForms software I have a few questions. Is it possible to have a wavegen and also use the Digital I/O at the same time? If possible, any tutorials on how to do this? I have been able to import custom data into the wavegen but can't find a way to set a Digital output. Looking at the SDK it looks like it would be possible to use the Analog output and Digital I/O at the same time? Is there any to sync the Analog output and digital output? For example, I want to send 250ms of analog data, then turn on the output, send another 200ms of analog data and then turn the output off. I have attached a file of what I am looking to do, does the SDK have some way to turn an Output on exactly after 250ms of analog out? I noticed some C++ examples for the SDK, however they appear to only use on feature at a time. Are there any complex examples? Thank you Sheldon
  6. Hi Jon, That makes sense, I guess I shouldn't expect consistent results out of undocumented behaviour. Thanks again for all your help. I think that solves my problem, though in the process of solving this one, another problem came up. I guess thats a topic for another thread... Thanks, Daniel
  7. PoojaN

    Measure Clock on Arty

    Hi @jpeyron Thank you for the answer. I was able to map the clock to the JA1 port using the ODDR, however the port was out of phase and I wanted to buffer this output as I want to interface the outputs of Arty with another chip set. This is the output that I observed on the scope. The yellow trace is the on board oscillator and the blue trace is the output through the ODDR. And just out of curiosity, was your Discovery 2 in scope mode or logic analyzer mode?
  8. Yesterday
  9. Thank you, JColvin! Last night I hooked it up to the Analog Discovery 2 and I read much better values than the "max bouncing" values in the datasheet of that small (6mm x 6mm) push button. It's actually so good that it's hard to start playing with capacitors to make it better. I'll try again later today with the oscilloscope in higher resolution (startup mode of the AD2). Stuk
  10. Hi @dmishins, On page 30 of the reference manual here states: " The red pushbutton labeled “CPU RESET,” on the other hand, generates a high output when at rest and a low output when pressed. The CPU RESET button is intended to be used in EDK designs to reset the processor, but you can also use it as a general purpose pushbutton. Slide switches generate constant high or low inputs depending on their position." So in this case if resets the Microblaze processor. I do not believe pressing the cpu-reset would re-run the application though. If you are wanting to configure the FPGA (including the SDK Application) on power up then you would want to use the QPSI Flash or SD card. best regards, Jon
  11. jpeyron

    pmod wifi

    Hi @harika, The Zynq processor facilitates the hardware connection between the DDR3 and the SD card. The SD folder in the SDK project handles the software portion for communication to the SD Card. What version of Vivado are you currently using? Please attach a screen shot of your block design. I get the following error when the files requested are not on the SD Card as well if the PmodWIFI was connected to the wrong Pmod Port. This is how the SD Card should look. Here is working serial output: Here is a screen shot of the contents of the Application as well as the HTTPServerConfig.h code. You must alter two parts of the HTTPServerConfig.h code You must put your modem login and modem password where it says to in the screen shot. I have attached pictures of my set up as well as screen shots from my phone which was connected to the HTTPServer. My phone needed to be connected to the same WIFI network to be able to access the HTTPServer. Here is a verified and completed for the Zedboard WIFI SD card Vivado 2017.4 project as of this afternoon. Best regards, Jon
  12. Hi Jon, Thank you so much! Your project seems to work fine on my computer, even after I regenerated the IP to update them and regenerated the bitstream. I'm trying to figure out what the difference could be between the projects, and ideally figure out what is wrong without just starting over. The only difference I can see in our block designs is that yours has an axi_smc block to connect to MIG whereas mine connects through the microblaze_axi. Could that be the difference, and is there a way to fix that? EDIT: That was the difference. I redid the tutorial from a new project making sure to follow everything exactly, and It now generates the same design that you got. Any idea what I did wrong before? Also, another thing that changing this brought up, is now pushing the cpu-reset button doesn't seem to reset the CPU. Any idea on why that would change and how to fix that? Thanks, Daniel
  13. In case of the same as AXI clock it is 83.33 MHz, on separate clock it is 66.66Mhz. I will try your example now
  14. Hi @dmishins, Sorry about the additional QSPI functionality in the project. You do not need the QSPI Flash IP Core unless you are planning on configuring the Flash with your project. Here is a completed and verified Nexys 4DDR uart with changing the linker script to the DDR in SDK. I believe the error you are getting is from not exporting the hardware including the bitstream. It might be easier to start with a fresh project. best regards, Jon
  15. Hi @Zhanneta, Glad to hear that you were able to solve the issue. Thank you for sharing what you did to resolve this issue. best regards, Jon
  16. I figured out why it wasn't working...On Digilent github, it said to only copy _pre-built/linux/images/BOOT.BIN_ and _pre-built/linux/images/image.ub_ to the SD card. Instead, I copied all the files in the _pre-built/linux/images/ directory and the bitstream to the SD card. It's working now and I see the boot process in my UART terminal.
  17. Hi Jon, Thanks again for your help. Is it necessary to include the QSPI in this program? I was planning on loading the program from my computer over usb when running it, and have no need for persistent memory, just ram. I tried adding the DDR2 connection from the board port to my design, and reverified the design, then regenerated the outputs, rewrote the bitstream, and now when I try to export the hardware to the SDK to test I get the following common error: I've tried all the suggestions to solve it I've found on the Xilinx forums. Any ideas to go forward? Thanks, Daniel EDIT: Generating the IP for microblaze as "Out of context per IP" as opposed to "Global" seemed to fix the problem. I'm not sure what that did though. I still have the issue where no data is sent through UART if the linker settings are set to mig.
  18. jpeyron

    Measure Clock on Arty

    Hi @PoojaN, Here is project I made in Vivado 2017.4 using the ODDR IP Core. I made two ports by right clicking on the block design. Both are type clock and one direction is input at 100 MHz and the other direction is an output. I connected the appropriate pins from the ODDR to the ports. I then created a wrapper. With the wrapper information I added a xdc using using the pin names in the wrapper. I then generated a bitstream. Next I opened the Hardware Manager and configured the Arty A7 with the bitstream. I then probed the pin 1 on JA (the pin I used for this project) with the Analog Discovery 2. It is showing a 400 KHz signal. I have included screen shots of the process. best regards, Jon
  19. PoojaN

    Measure Clock on Arty

    Hii @jpeyron I followed the same tutorial, but I am not able to understand where to specify my output pin where I will be able to scope my clock.
  20. Both the kernel and u-boot build successfully from within Petalinux projects. That is the main workflow we support. We plan to update u-boot, it's just a matter of prioritizing tasks before we get to it.
  21. Hi @Stuk, I was not able to find a datasheet that listed those sorts of details for the TSA12111 button, but I was able to find a datasheet for the other set of buttons (the smaller set of buttons) that listed maximum bounce times. I have attached that particular datasheet below. Let me know if you have any questions. Thanks, JColvin EVQ-PAE04M datasheet.pdf
  22. jpeyron

    Measure Clock on Arty

    Hi @PoojaN, Here is a xilinx forum that should help you with using the ODDR with the Arty-A7. best regards, Jon
  23. Hi @dmishins, Here is a verified and completed Nexys 4DDR Vivado 2018.2 qspi flash project. My boards tab does show that the qspi is connected so that might be the issue. I used 50 MHz from the clocking wizard for the ext_spi_clk on the qspi flash ip core and 200 MHz for the sys_clk_i on the Mig-7. I have attached screen shots of the process. best regards, Jon
  24. @vicentiu I've marked your response as solution as it is the solution to my question. However I'd like to add that some repos, such as u-boot, are too old already, the builder fails in latest ubuntu or debian (using libssl 1.1, maybe there're more problems after this point). I haven't tried the linux repo but I'm afraid similar issues may arise Been Cora a new board customers expect Digilent to provide updated tools and more documentation resources.
  25. PoojaN

    Measure Clock on Arty

    Hi! @hamster Thank you for the answer, but could you please tell me how to ODDR output? I am pretty new to this. Also I am using Arty A7, which has Artix-7 FPGA, and all the information I could get was limited till Spartan-6 FPGAs. Thank You!
  26. Hi @user2051 The Digital-Out (Patterns) can be trigger by a digital line, through the Digital-In (Logic Analyzer) trigger detector like this: dwf.FDwfDigitalInTriggerSet(hdwf, c_int(0), c_int(0), c_int(1<<7), c_int(0)) # DIN7 rising edge dwf.FDwfDigitalOutTriggerSourceSet(hdwf, c_ubyte(3)) # trigsrcDetectorDigitalIn See the related posts: You might be interested in the ROM logic feature too:
  27. Hi @catphish, As an update, our design engineer responded back to me saying that they will look into this further since while the part works is nice, having (potentially) operate out of spec is less ideal, so we are learning if that particular component as per the manufacturer specifications can operate at this voltage or not. Thanks, JColvin
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