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  1. Past hour
  2. zygot

    ethernet communication with pc

    @PhDev Perhaps you'd be willing to provide a simple application to the Project Vault demonstrating your positive experience with these cores that come in the form of pre-compiled netlists. It's been my experience that becoming invested in such IP with very limited documentation is, in the long run, not very productive. There are, obviously, quite a few people out there who just need a quick and dirty solution to solve a problem and don't have long term interest in developing standard Ethernet based projects.
  3. Today
  4. aeon20

    Confusion regarding Xilinx cable drivers

    What exactly are the "cable drivers"? Guides such as and also don't clearly state what it is. Are they loadable kernel modules? Device files under /dev? Are they user space utilities? This is not clear to me. Running the install script prints out some information that doesn't really help me either. For an FPGA beginner like me that can't get this to work, and doesn't even know how the "cable driver" system is intended to work, and with documentation being scarce and sometimes misleading (e.g. referring to readme files that don't exist), this is hard. What should a functional system that has the "cable drivers" look like? What (if any) cable driver related prosesses should be running? What (if any) loadable kernel modules should be present on the system? What does a successfully detected Digilent FPGA device look like when listing USB devices using lsusb? For a modern Linux distro, it is even needed at all to install the cable drivers, with a modern kernel? Again, this question only makes sense once I know what the "cable drivers" are. Are they user space or kernel space related? I've also been told this before: What exactly is the "Digilent runtime", and how does it relate to the cable drivers? What files should I run? There are several available after installing Vivado. I'm an experienced Linux user, if someone could walk me through this that would be very nice and helpful.
  5. mishu

    How to restore FT2232 EEPROM back to factory settings?

    Hi there, As many users, I have a problem with my JTAG SMT3 device, it seems to stop working and to be seen in Vivado, for unknown reasons at this time. I would like to make it work again, so please maybe somebody can send me a PM message with the steps needed to be done to achieve this. Thanks, M.
  6. Kris Persyn

    Digital Twin

    Hey, For a quite challenging project I am planning on using a zybo z7-20 to drive immersive visuals on a HDMI display (probably this monitor Lenovo L27i-28). Simultaneously I would want to collect sensor data through digital pins (digital signals are provided by an external uP) and also interface with matlab (used for speech recognition) via USB. My question thus is: Is this baby powerful enough to deal with all this load? Kg, Kris
  7. I can also add that I've now tried a different physical computer with a fresh Debian 9.7 install. I get the same result: "No devices detected on target". I'm not using an emulated USB controller. The board "partially" shows up though, just as before (same screenshot as above, but identical results, just didn't bother making a new screenshot when there is nothing new):
  8. Cristian.Fatu

    USB Host with Arty Z7 2017.4.1 Prebuilt Images ???

    Hello, We have booted using the bsp you specified. We have used external power (and suggest you to do so), having set the JP5 to REG. The dmesg messages seem similar in our case to the ones you posted. Also, the first item listed by lsusb is identical to yours. Obviously we cannot plug the USB device you use (class-compliant MIDI device). We have tried an USB Flash drive, properly recognized as mass storage device. So, everything seems to be OK on our side. Please read chapter 8 (USB Host) from the reference manual. There are some details about how the USB port behaves. Maybe this is useful for you.
  9. kotra sharmila

    sdsoc_opencv error

    hi, yah i removed that function and doing modifications insert haar cascade but still gort th errors filter2d_cv.cpp
  10. Danny Armstrong

    Pmod library not found in Vivado 2014.4

    Hi Jon, "Add IP" button works! Although I have not got time to implement an FPGA design yet today, I believe it will work with 2014.4, with proper external connection and Pmod constraints. I forgot totally the "Add IP" button, when the board tab did not show the Pmod modules. Thanks Jon. Best Regards, Danny
  11. Ciprian

    Hdmi out from zybo

    Try adding this: &i2c0 { clock-frequency = <100000>; status = "okay"; }; Here: <petalinux_project>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi -Ciprian
  12. bogdan.deac

    sdsoc_opencv error

    As I mentioned here, you cannot use cv::VideoCapture() function to acquire a video stream from the webcam. For this reason you must to start from a sample project that implements video stream acquisition from HDMI/MIPI.
  13. StuE

    Maximum continuous sample rate

    @attila as you suggested I used the python example. For some reason it wasn't working; wouldn't stream off the buffer. Something I did randomly made it work but I'm not entirely sure what I did (although since it's working it doesn't really matter) One thing, though. Looking at the waveform of the data stream running at 100kHz or 200kHz, I can see that there ARE some missed samples. I think I can work around these, but it's worth noting. I did wonder whether I could split my signal across the two AnalogIn channels and pull data down at different times to characterise how much is dropped but haven't tried it yet. Thanks for the advice re doubling the buffer size, that's the first thing I'm going tomorrow while my laser warms up. Thanks for your advice.
  14. @attila thanks, I actually found it after digging around for a while. Sorry to have asked a question without looking into things myself first.
  15. This link: doesn't lead anywhere. I tried removing the "." at the end, same.
  16. aeon20

    How to install and use djtgcfg?

    I'm sorry, I meant that the link you posted in the other thread doesn't go anywhere. I don't know why I replied here, I got confused.
  17. jamesW

    PMOD MTDS text font sizes

    Ah, yes - thanks. I should have paid more attention to the manual! Thank you for looking into this and providing the answer.
  18. MSchleeh

    Pmod MTDS Display dark Display after 10-20min

    Hi @jpeyron I created a custom application, in which i use the PmodMTDS_v1_0 library to load Bitmaps from the micro SD card onto the display. The other parts of my project still works as expected, even when the display screen goes dark. Today i also tested the display with the Demo "" and still get the same effect. (Works fine for 10-15 min, before the screen goes dark) Are there any known issues of the MTDS, that may explain why the display screen goes dark after a while? thank you for your help, Maurice P.s Additionally I installed a ferrite choke around the connection cable between the display and the Zedboard to minimize the interferences of high frequency noises.
  19. Lakshmi Tejas M A

    Error with enabling DIO channel

    Hi @attila thank you on checking on it. We think analog discovery 2 is getting disconnected because of noise entering USB. Not sure. wanted to know if we can close the device which is opened and reopen in this scenario. because WF is not open and some function are running but in middle this scenario is created. This doesn't happen every time. ty LT
  20. kwilber

    artix nexys 4 and keyboard

    There is a companion website for Pong Chu's books here. You can find the source code from the book there. Part IV of the book covers video systems and the VGA interface.
  21. gummadi Teja

    artix nexys 4 and keyboard

    could you please provide a source code for the keyboard interfacing using nexys4 board and vga synchronization sir.
  22. gummadi Teja

    artix nexys 4 and keyboard

    Thank you sir ,(FPGA Prototyping by SystemVerilog Examples: Xilinx MicroBlaze MCS SoC Edition by Pong Chu.) how to get a solutional manual for this book. but we want to implement on monitor using vga synchronization.
  23. Hi @StuE Here you can see the device configuration capabilities: >python DWF Version: b'3.10.2' Number of Devices: 1 ------------------------------ Device 0 : Name:'b'Analog Discovery 2'' b'SN:210321A419AA' Configurations: 0. AnalogIn: 2 x 8192 AnalogOut: 2 x 4096 DigitalIn: 16 x 4096 DigitalOut: 16 x 1024 1. AnalogIn: 2 x 16384 AnalogOut: 2 x 1024 DigitalIn: 16 x 1024 DigitalOut: 0 x 0 2. AnalogIn: 2 x 2048 AnalogOut: 2 x 16384 DigitalIn: 0 x 0 DigitalOut: 0 x 0 3. AnalogIn: 2 x 512 AnalogOut: 2 x 256 DigitalIn: 16 x 16384 DigitalOut: 16 x 16384 4. AnalogIn: 2 x 8192 AnalogOut: 2 x 4096 DigitalIn: 16 x 4096 DigitalOut: 16 x 1024 5. AnalogIn: 2 x 8192 AnalogOut: 4 x 4096 DigitalIn: 16 x 2048 DigitalOut: 8 x 256
  24. attila

    Maximum continuous sample rate

    Hi @StuE In record mode the device buffer is used as a fifo. The scan shift mode returns all the data fetched from the device buffer. It is not mend for recording, does not provide buffer overflow information. Record loop: FDwfAnalogInStatus(HDWF hdwf, BOOL fReadData, DwfState *psts); // fetch status and data FDwfAnalogInStatusRecord(HDWF hdwf, int *pcdDataAvailable, int *pcdDataLost, int *pcdDataCorrupt) cdDataAvailable - how many new samples are available since the last fetch cdDataLost/Corrupt - indicates fifo overflow, try to improve the loop performance, reduce sample rate, for AD select second device configuration to have more buffer Get the new data samples: FDwfAnalogInStatusData(HDWF hdwf, int idxChannel, double *rgdVoltData, int cdData); cdData <= cdDataAvailable
  25. Hi @fonak I thank you for the ideas. I plan to add CV/CC mode which will require auto resistor switching on wider frequency range, mentioned by @kojak
  26. XSCT terminal in xilinx sdk has tcl command mwr(address,data)/mrd(address) which is transmitted over onboard jtag interface. (we are using VCU 118) later we are targeting a synopsis based IP. we bought the JTAG HS-2 in order to prepare our selves for the chip bring up. In the API we already learned and executed samples being able to go into IR and DR state using DjtgPutTmsTdiBits, DjtgPutTmsBits commands. We are missing the part of how to create mwr/mrd commands from IR DR elements. Can someone help providing some more reading material, samples which will help us to have some progress ? we are not sure if we will be able to read registers from xilinx fpga board, will the same code will work on synopsis based chip eventually ? my question is actually is this a generic protocol or each vendor has its own protocol over jtag ? I realize I have some misunderstanding ( being newbie in jtag implementation) hope my questions are clear enough. Thanks, Roy
  27. PhDev

    ethernet communication with pc

    @D@n Yes I think they work great. Very easy to use. I have mostly been using FC1002 with TCP. I have also used FC1003 in a project where UDP (broadcast) was a better choice. I hope they release a FC1004 with RMII: (Both UDP and TCP) DHCP or fix IP works as expected. The remote programmer also works very good. I think it is faster and easier than using XIlinx programming tools. The logic analyzer is also very useful for debugging the system without using the jtag. Only bad thing is that I sometimes need larger sample buffers. I also miss some documentation, however I think I have figured it out most of it now. I really like the AXI-stream. Xilinx has very good components supporting this like clock domain crossing, FIFO, Filters etc.
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