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  3. NetFPGA SUME +FMC

    Hi; I'm trying to connect High Tech Global "4-Port SATA / 4-Port SFP+ FMC Module (Vita57.1) " to NetFPGA SUME to use 4 X SFP+ via FMC. http://www.hitechglobal.com/FMCModules/FMC_x4SFP_x4SATA.htm I connected this FMC module to different FPGA boards and it works fine, but it doesn't work with NetFPGA SUME. I used different implementations such as: I used NetFPGA SUME nic_reference design and changed the constraints based on the fmc_gtwizard constraints file to connect to the FMC module. The modified nic-efrence design is failed to pass the tests and it doesn't receive any packet for all 4 ports. I tried the NetFPGA SUME fmc_gtwizard design . The track_data_out_i signal in ILA for the lines is constantly '0' which indicates that valid data isn't received on the RX side. I tried different options such as lower frequency rate and it doesn't work. Do you have any recorded experience like mine? Could you please advise me what is the issue might be? Best regards; Arash
  4. Hi I'm planning to use the pmod ISNS20 for a project. I want to interface it with nexys4ddr board. The pmod isns20 has 2 interfaces: input : hall effect sensor's input terminals IP+ and IP-; output: ADC's output terminals: SDO; I'm familiar with the usage of the output interface with the nexys4 ddr using the SPI protocol. However, I'm not familiar with the input interface. I want to know if a sense resistor has to be used across the IP+ and IP- terminals? If so, what would be the equation of current? If no sense resistor is used, how to connect the terminals IP+ and IP- to the circuit? And again what is the equation of current being measured? I have seen the datasheets for both adc and hall effect sensor. Did not find any info on how to connect the IP+ and IP- terminals. Any help on this is highly appreciated. Thanks
  5. Hi I'm also planning to use the pmos ISNS20 for a project. I want to interface it with nexys4ddr board. The pmod isns20 has 2 interfaces: input : hall effect sensor's input terminals IP+ and IP-; output: ADC's output terminals: SDO; I'm familiar with the usage of the output interface with the nexys4 ddr using the SPI protocol. However, I'm not familiar with the input interface. I want to know if a sense resistor has to be used across the IP+ and IP- terminals? If so, what would be the equation of current? If no sense resistor is used, how to connect the terminals IP+ and IP- to the circuit? And again what is the equation of current being measured? I have seen the datasheets for both adc and hall effect sensor. Did not find any info on how to connect the IP+ and IP- terminals.
  6. uC32 with Pmod Shield and PmodWifi

    Hello Jon, If I select just "CHIPkit uC32", then example compiles without errors, but I wasn't able to connect to my WiFi hotspot. Regards, Joel
  7. Reading and writing to QSPI on the CMOD A7

    @David1234, If your goal is to have persistent memory, the flash is usually the way to go. While it is possible to use an SD card for the same thing, SD cards take a lot of interaction with their host just to set up. Your other alternative would be to send information from the host (i.e. your PC) to the FPGA. If you have to write flash, there is one thing you *must* ensure, and that is that power cannot be removed from the flash mid-erase or mid-write operation. The problem is that, if power gets pulled, the flash may act right and it may not act right with a random probability. It may act right once, and then not the next time, etc. This has been a thorn in the side of those making flash-based devices, such as thumb drives. The software can come through checking CRC's, and sectors 1-N might pass, so software may declare those sectors good--only to have one of them not-pass later. The same would be true of an SD-card--don't pull power mid-write. The other (easier/simpler) alternative would be to pass the device its configuration from a host machine upon startup. Of course ... that only works if your device will be running in a situation where that's possible. In this case, you'd need to pick some sort of protocol to pass this information along. There are lots of possibilities, I guess. Pick the one that's right for you. Dan
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  9. Stupid Q: What does a loop in a HDL really mean?

    A shift register actually has fairly simple representations in both VHDL/Verilog. sr <= sr(sr'length-1 downto 0) & something; st <= {sr[`SRLEN-1:0], something}; Depending on how optimized the simulation/synthesis tool is, there could be a difference in performance.
  10. Reading and writing to QSPI on the CMOD A7

    I want to use the remaining flash memory to save user settings so that the user's settings persist even if power is lost. Is saving their settings to flash as they are changed the most practical way to save their settings, or is there a smarter, easier way to accomplish the same thing?
  11. Hi @tutu The dwf lib requires files in the firmware path which are the firmware images for various devices. The dwf also depends on the adept runtime. At the moment dwf app bundle options are supported on Windows and OS-X, but I will add for Linux too.
  12. TDM Protocol with Digital Discovery

    Hi @ninjit You could use custom interpreter to decode multiple TDM microphones.
  13. Noise output when changing freq.

    Hi @suktan Changing any option in the Wavegen interface the AWG is restarted, so the earlier running function is suddenly stopped and this could result a steep edge.
  14. Import audio file size limitation

    Hi @suktan The WaveForms application WaveGen "import to play" has a sample limitation of 100M on 64bit and 10M on 32bit system.
  15. Hi @Jonboy Special sub-addressing is only required for read operations. In this process the sub-address write is followed by a restart and read. https://www.i2c-bus.org/repeated-start-condition/ For write operations you can just concatenate the "sub-address" with the array of data you have to write. var a = [1,2] // sub-address var b = [3,4] // data var c = a.concat(b) Protocol.I2C.Write(0x48, c)
  16. Digital Discovery API

    Hi @Souther Just typecast the integer value to floating point for DIOPE/PP, like: FDwfAnalogIOChannelNodeSet(hdwf, 0, 2, c_double(0x00FF)) #DIOPE
  17. Stupid Q: What does a loop in a HDL really mean?

    its just a way of reducing the amount of HDL you have to type Here is an example, say you want to describe a shift register, you have an input and an output data pin, say input_port : std_logic; output_port : std_logic; you are going to need some flipflops for your shift register, lets have 8, you need an input to each flipflop and an output from each flipflop, here are some sigs for that input_signal : std_logic_vector(7 downto 0); output_signal : std_logic_vector(7 downto 0); then you need to describe the flipflops, Process (....) begin if (clk ‘event and clk = ‘1’) then output_signal <= input_signal; end if; end process; Now you have 8 individual flipflops with inputs... input_signal(0) input_signal(1) input_signal(2) input_signal(3) input_signal(4) input_signal(5) input_signal(6) input_signal(7) and outputs.... output_signal(0) output_signal(1) output_signal(2) output_signal(3) output_signal(4) output_signal(5) output_signal(6) output_signal(7) So to get your shift register you will need to connect the output of the first flipfloip to the input of the second flipflop and so on.... Then connect your i/o ports, so something like this input_signal(0) <= input_port input_signal(1) <=output_signal(0) input_signal(2) <=output_signal(1) input_signal(3) <=output_signal(2) input_signal(4) <=output_signal(3) input_signal(5) <=output_signal(4) input_signal(6) <=output_signal(5) input_signal(7) <=output_signal(6) output_port <= output_signal(7) All a loop does is compress the notation, the above would do something like this... i = 1 to 7 input_signal(0) <= input_port input_signal(i) <=output_signal(i-1) output_port <= output_signal(7) Useful notation if the shift register was much bigger, or you wanted to change the size easily, also useful in big repetitive circuits like hand crafted filters. Not helpful when you are working in teams and they are used for something as simple as the above, as you can see its easier to read the long-hand description than a loop.. Hope that helps... Gra
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  19. Stupid Q: What does a loop in a HDL really mean?

    @Tickstart, Gosh, you want examples? Let's see ... I've used loops in FIR filters to describe the logic required at each tap. I've used them within CORDIC's to describe the logic that neeeds to take place in a multi-stage algorithm. I've used them to apply the same I/O logic to multiple bits in a vector. I've used them in loops to bit-reverse vectors. I've used them within my differential pmod-challenge code to look for bit-sync across multiple synchronization possibilities. I've used them to check for the synchronization sequence within an HDMI stream, knowing it could come in at any time and in any offset. I've used loops within initial statements, to initialize any memory that wasn't initialized by my $readmemh command. Dan
  20. Stupid Q: What does a loop in a HDL really mean?

    loops can be used to describe HW. normally this isn't done to describe complex HW though. An example of a loops that can be useful in VHDL are: parity (xor-reduce), any (or-reduce), none (not or-reduce), all (and-reduce), bit-reverse, bit-count (maybe), gf2 inner product, etc... More complex logic like long-division or shift-add multiplication can infer much more logic. very complex logic like a sorting algorithm would result in long synthesis times and likely a large, slow design.
  21. Correct Input and Outputs for PMODI2S?

    Okay, so I've got fully working code for the STM32F411 which has a CS43L22 DAC on the board. Note that this is not the same as the CS4344 that is on the PmodI2S. The CS43L22 has a whole set of initialization steps that the CS4344 does not and also does communication with I2C and I2S. I still want to get the PmodI2S working with my STM32F429. My next steps are going to likely include: Comparing my STM32411/CS43L22 code with my STM32F429/CS4344 code and making tweaks to the latter. Getting DMA to work first with the STM32411/CS43L22 and then hopefully leveraging this information to get DMA to work with the STM32F429/CS4344. If anyone is interested in my ongoing trials and tribulations with the above please let me know.
  22. How to configure a one shot push button

    Hi, Glen Check this, if it does not work for you let me know: ( also, instead of a button you can set a trigger for you SPI ... at protocol tab -> SPI ) Remember to hit Single for this purpose. regards, João Paulo N Bino
  23. Stupid Q: What does a loop in a HDL really mean?

    @Tickstart, Yes. Loops in HDL just generate more logic, not sequential logic. Remember: *everything* runs in parallel. "Sequential" loops in HDL have only the appearance of being sequential--they actually just describe logic. If you can't fit the logic within one clock cycle, then you will fail to meet your timing constraints. Dan
  24. I haven't used loops very much so far for this reason, I don't understand what they are in a hardware description language. In a regular processor they are self explanatory, the processor cycles through the loop and tests the condition, one clock cycle at a time. But in VHDL for example, there is only one clock cycle.. So loops in a VHDL-process are some über-high abstraction thing that generates hardware that does all this seemingly sequential stuff in 1 clock cycle?
  25. Generating project failed

    Hello, It took me awhile to learn a little about Vivado and thanks to your help I finally generate bitstream and program FPGA. But it still doesn't run perfectly. The USB terminal works but HDMI doesn't display anything. I suppose it may be caused by few critical warnings I can't fix, like this: [BD 41-51] Could not find bus definition for the interface: TMDS "create_project.tcl" doesn't create TMDS (clk_n, clk_p, data_n [2-0], data_p [2-0]) ports so I do it manually (by "add new port") but the warnings still don't disappear. Is there a better way? Thanks for any help
  26. Reading and writing to QSPI on the CMOD A7

    David, eqspiflash.v would be the top-level flash component. I suspect you will have other components within your design. You may need to instantiate the STARTUPE2 primitive to get access to the output clock. Since it's shared between Xilinx's load logic, you need to do a little extra work to control it. To request a transaction with the core, set (i_wb_cyc)&&(i_wb_stb). You'll also want to set the address (zero is the beginning of the flash). If you wish to write to the core, set (i_wb_we) and the data you wish to write. The core will control the (o_wb_stall) flag. When (i_wb_cyc)&&(i_wb_stb)&&(!o_wb_stall), a transaction request has been accepted. Drop the i_wb_stb line on the next clock, lest you request multiple transactions when you only want one. (Or keep it raised, and just set the next address ...) The core will respond to your transaction request (eventually) by setting the o_wb_data and o_wb_ack lines. At that time, any read data is ready. You can drop i_wb_cyc after you get the ack from your last request. If you drop i_wb_cyc early, the ack will be suppressed. You can find an example wishbone master here, or a discussion of how to build one here. If this is still confusing, check out Fig's 3-6, 3-8, 3-11, and 3-13 of the wishbone spec, version B4. This core, as with all of my cores, uses the pipelined version of the spec. Remember, this is a flash: reading is easy. Writing is harder. There are two steps to any write to a flash. The first is to set any '0' bits to '1's. This is called erasing. You can erase sectors or subsectors, but sadly you cannot erase pages, words, or even bytes. Erases are therefore rather heavy handed. To command an erase, (check the doc's within the core) you'll write to the write protect word in the controller to turn off write protection. You'll then write to this word (again) with the erase command and the address of the area you wish to erase. The flash device will then go out to lunch for many ms (I think the spec says up to 3s), to do this erase. During this time, you can read from the status register of the core to know if it is done or not. Alternatively, once the erase is complete the core will raise an interrupt flag so you can tell it's ready to be used again. The core will turn the write protect flag back on when it is done. That's erasing. The second step to writing. This is the step that you use to turn '1's to '0's. The flash specification calls this "programming". To program a device with this core, first write to the control register to turn off the write protect bit. You can then write to a "page" containing 256 bytes. Do as instructed in the steps above, but also ... write consecutively from one value on the page to the next. The core, and indeed the flash itself, can't handle writes that jump around on the page. Second, keep the i_wb_cyc line high. Once that line goes low, your page write request will be complete, and the device will go off and write. Expect this to take several ms as well. As before, you can either read the status register from the core to know if/when it is done, or you can wait for the interrupt line to go high. If you've never worked with flash memory before .... <grin> it's not like regular memory. Hopefully you understand that by now. While you can treat reading from a flash device like reading from a slow ROM, writing to the device is much harder--so hard that most applications just treat the device like a ROM. Still, it's good for storing configuration data within it. Hope this helps, Dan
  27. Reading and writing to QSPI on the CMOD A7

    Thanks Dan. I saw that entity earlier but discarded it thinking it wouldn't work because the interface didn't seem to match up. Would eqspiflash.v be the top level in a simple, non-softcore-cpu CMOD A7 project? I essentially just want to use this as a really slow memory where I just provide a WR/RD signal, address and data signals. For some reason the CMOD A7 has qspi_cs and qspi_dq[0:3] but no qspi_clk... Is the clock from something else automatically used? In general, what changes need to be made to use this in a simple, non-softcore-cpu CMOD A7 project? Thanks, David
  28. After going through a range of the SDK examples, I'm running into some strange behavior that I'm hoping someone can help explain. The result I'm trying to achieve is sending out a low duty cycle pulse (Digital or Analog but something similar to a TTL) that triggers the repeated acquisition on the Analog Discovery. I can achieve this result using the GUI but would like to insert this process into a python script so I can process and save the data. When I route W1 into CH1 in the following example what I see is expected. However, when I try to route the digital out into CH1 things look extremely wonky. Again, I'd like to see a waveform that would be considered a PWM waveform that has a duty cycle of ~99% low and I'd like to be able to control that duty cycle with a reasonable degree of precision and accuracy. Any help would be appreciated and hope the solution is easy as I've been staring at this entirely too long. Am I just trying to put too many points into the digital out? Another potential solution that I'm not entirely sure how to implement, is loading a custom waveform from a file and running that through the waveform generator. Is there an example for that that would also fit with the DAQ needs? Cheers, Brian AnalogIn_Acquisition_5.py
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