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  2. jpeyron


    Hi @eray, @hamster's MPU6050/Basys 3 is a good start to an interesting project. I would suggest converting audio files to a coe file using something like matlab or a prython script. Then in vivado is a bram with the coe file. Here is a xilinx forum thread that discusses this. best regards, Jon
  3. Hi @birca123, I reached out to one of my co-workers which happens to be currently having a similar issue with the Video Timing Controller on their project. We will be looking into this further but currently havent found a cause. We also would suggest to reach out to Xilinx about the Video Timing Controller hanging as well. best regards, Jon
  4. Hi, I have a Zybo Zynq-Z7-10 board with PMOD PCam-5C I tried the steps in the replies: I setup as well a microSD card 8G using gParted: first partition 1GB type fat16 and the second partition 6.80GB type ext4. After inserting the card in Zybo's slot and switching the jumper to SD , the effect of switching on is that the board lights on the LED red LD13 PGOOD, the connected HDMI Monitor has not signal. I have some questions: which resolution has the HDMI output in Petalinux? The bitstream file of Z7-20 Vivado project with the modifications of the diagram and PWM - how does it get inserted in the Petalinux binaries that get on the SD card? I guess using this command --- petalinux-package --boot --force --fsbl images/linux/zynq_fsbl.elf --fpga images/linux/system_wrapper.bit --u-boot ---- but there is no interdependency set in the previous posts. Should the project run and the HDMI display connected to the output of the Zynq must run even without the bitstream ? The microsd card was formated with gParted, is compulsory using of a dedicated tool to write the rootfs, boot.bin files ? or the commands: cp BOOT.BIN image.ub /dev/sdd1/ is enough ? sudo umount /dev/sdd2 sudo dd if=images/linux/rootfs.ext4 of=/dev/sdd2 sync sudo resize2fs /dev/sdd2 sync should be enough?
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  6. Hi @benl, You should be able to determine what version of firmware you have on the OpenLogger, but going to the Device Manager (main page where you can select the actual OpenLogger or a simulated version), and going to the Configuration Menu for the actual OpenLogger and selecting the "Update Firmware" button under the Firmware section. There you will be able to see the current version as well as be able to select and download and update the OpenLogger to the latest version, which is currently 0.1807.0. I asked another one of our engineers more familiar with the WaveForms Live about this, and while it is technically working (I was able to get it to run for awhile before encountering the same errors as you), latencies introduced by the network cause WaveForms Live to fall behind, producing the errors that we are seeing. They let me know that this can be alleviated by throttling the sampling rate so less data needs to be transmitted between polls. In the future, they are thinking of adding a method to have WaveFormsLive resync with the OpenLogger, but they do not have the time to implement this right now. As for logging errors, you can do this by going into settings (in the upper left dropdown), open the advanced dropdown, change change the logging behavior to have the console log be stored on the console; by default it's set to none. You can then view the error log in the Chrome Dev tools (control shift J) and going to the console tab to view what is being printed to the log. Let me know if you have any questions about this. Thank you, JColvin
  7. Hi @SGY, You could realistically use any version of Vivado to program the Zynq chip on the Zedboard, though some of the projects will expect certain versions of Vivado and Xilinx SDK to be used in order for the projects to work the first time without any modifications. As for the pin requirements, it depends what GPIO functions you need. There are 4 Pmod ports on the Zedboard that are not constrained to any particular usage, but otherwise the Zedboard has 8 switches and 5 buttons as well. However, this only adds up to about 45 GPIO, so the other unassigned GPIO are present on the FMC connector. However, depending on what application you need for your GPIO, you may be hard pressed to find a FMC card that suits your needs. What sort of simple controls are you hoping to do? Thanks, JColvin
  8. Hi @sbellamy, If you are referring to the pins in the schematic, those names tend to be based on what Xilinx dictated the pin names for the Zynq. Otherwise, I would recommend looking at the Avent User Guide that is on the Zedboard Resource Center. Digilent doesn't make the KC705, but it has it's own user guide from Xilinx here that also explains the pin assignments here Thanks, JColvin
  9. Hi @hearos, Are you using the SD card reader that is on the Nexys 4 DDR or a Pmod SD or Pmod MicroSD on pmod port JA? If you are trying to us the SD card reader on the Nexys 4 DDR then you will want to use the onboard Micro SD Slot under external memory on the board tab. I have attached a screen shot of this. If you are using a Pmod Sd or Pmod MicroSD on port JA you should not need a XDC to constrain these pins since the boards files along with the vivado library IP's configure this for you. best regards, Jon
  10. Hi @Cuikun LIN, Here is a forum thread that discusses Labview and AD2 sample code. Here is a forum thread that discusses the WaveForms Runtime/SDK which can be accessed from LabView directly without Python which is on here. The provided examples in the SDK are mostly in Python which you might be helpful. best regards, Jon
  11. Hi @mikeWylie, Unfortunately we have not used the AD9114-DPG2-EBZ with the AD-DAC-FMC-ADP-ND adapter card. FMC's on our boards like the Nexys Video are designed to meet the 57.1 spec. The Nexys Video has a low pin count(LPC) FMC. I would also suggest contacting Analog Devices to get their input as well. best regards, Jon
  12. Thanks Jon - I was stuck and will give this a shot immediately! Reagards, >>Eric
  13. Hi @JColvin, I think I have the correct raster operation - ropScrPaint which 'ORs' the source and destination - as this works fine when both bitmaps are at the same bit depth. So, I think this is indeed expected behaviour. Thanks very much for looking in to it.
  14. @mikeWylie The DAC that you want to use is an older device and uses a DDR interface, so there's hope. I've posted on this type of question numerous times in answer to numerous questions similar to yours. You can see my list of EVM's that I've found useful in the Technical Off-Topic Useful EVMs for FPGA Development Boards post that I started ( I'll update or respond to posts to queries on that post as needed ). I've posted more specific guidance in answering other similar questions but don't have the time top track them all down.... unfortunately, it's difficult to steer people toward a previous post that might answer their questions. The short answer is that you have to trace though all of the signals from the EVM through any adapter boards and through the FPGA development board that you are using to make sure of connectivity. When there are no SERDES involved things are easier and more likely to be possible from a clocking point of view but you still need to make sure that your IO pins have compatible standards. The adapter will complicate timing closure, and depending on signal routing might make an interface much more complicated. Make sure to trace though all power and ground pin assignments. Lastly, and most importantly, make sure that clock signals into or out of your FPGA are assigned to clock capable pins. This commentary is not exhaustive. If you really need one or two channels of high speed DAC or ADC and don't have a big budget to work with I suggest looking a Cyclone based FPGA board with HSMC connectors. Terasic is a good place to look. Opal Kelly has a few Syzygy options for high speed ADC/DAC applications. Otherwise, options are bleak. Trust me that I'm always on the lookout for high sampling rate ( > 10 MHz ) analog <--> digital development platform options. In my post for using EVMs with FPGA development boards I mention the Terasic De0 Nano/LTC1668 board combo that I've found to be useful. Just because a mezzanine card uses an FMC connector that doesn;t mean that it's usable with any FPGA board having an FMC connector. There are two possibilities here that will work: Read the schematics and work out all of the details for yourself before buying anyting Use the advice of a trusted source who has successfully done what you want to do and then do option 1 anyway. You are ultimately responsible for everything. Keep in mind that since the FMC is a high speed interface there's no safety net for boo-boos.... you get it right or the odds are very high that you will destroy your FPGA board.
  15. Hi @mufasir_qureshi, Welcome to the Digilent Forums! Could you attach all of the HDL. Can you be more descriptive about your project. best regards, Jon PS- one of my first verilog SPI controller i missed assigning the signal as an inout. Instead I had assigned it as an input.
  16. I currently have the Nexys Video Artix-7 FPGA board. I can see that the board has the high speed connector that can plug into the AD9114-DPG2-EBZ ( AD9114-DPG2-EBZ ) with an adapter card - AD-DAC-FMC-ADP-ND ( My question is, how do I find out if the evaluation card (AD9114) with adapter board is compatible with the development kit? Analog devices says the evaluation module will work with any DPG2 compatible board, but I can't seem to figure out if the Artix-7 development kit is DPG2 compatible.
  17. Hey @Raghunathan, Thank you for the screenshot here. What I am gathering from this image and your previous posts is that you are possibly running into a network priority issue. There are several things we can do here to see if this is truly the case. A network priority issue may arise when you are connected to multiple networks, say over ethernet and WiFi, or when you are running VPN software. When your machine sends data over the network, it needs to decide which interface it uses first, and this priority is usually established within the OS. So, first: Is your WIN10 machine connected to multiple networks and/or is it running any VPN software? If this is the case, then you may need to reorder the priority within Windows to fix the issue. This guide shows you how to change the interface metric which will affect the interface priority level. If you've tried the above solution to no avail, or it doesn't apply to you then we'll try something else. WFL normally uses the localhost address on port 42135 to communicate with the agent, and I'd like you to try and see if we can use localhost at all. So, secondly, I want you to open your CMD prompt, and enter ping localhost. You should see some output saying 'Pinging <machine-name> with 32 bytes of data' followed by several replies. If you don't see any of those replies then something is blocking you from localhost. If you are blocked from localhost, when connecting to the agent you can replace where it says localhost with This is the IPv4 address of localhost, and WFL should work as if you had localhost and if your problem doesn't persist. If these steps don't fix your issue then there is something else that is giving you trouble. In that case, we'll continue to dig further and see what we can come up with. Let me know if you are running any VPN software or are connected to multiple networks, as well as whether the ping localhost works for you or if using works as well. Regards, AndrewHolzer
  18. Hi @NeedlessBird, Glad to to hear that changing the Vivado version resolved the SDK driver issue. Thank you for sharing what you had to do to resolve this issue. best regards, Jon
  19. Hi @patelviv, I have moved your thread to a section where more experienced embedded linux engineers look. Here is a non digilent tutorial that might be helpful. best regards, Jon
  20. Hi @michaelgood411, Welcome to the Digilent Forums! I have moved your thread to a section where more experienced embedded linux engineers look. best regards, Jon
  21. jpeyron

    CPR 290-006

    Hi @Sergei, Welcome to the Digilent forums! I believe that the 1:19 Gear Ratio DC Motor/Gearbox has 1 pulse per revolution. Here and here are forum thread that discusses the CPR. best regards, Jon
  22. Hi @Arjun, I typically use standalone applications. I would not have a lot of information on this topic. Here and here are xilinx forum threads where they discuss a similar issues. best regards, Jon
  23. Hi zygot: Thanks for your quick reply. Do I need Vivado 2014 or latest Version to develop Zync? My application is simple: we need 70 GPIOs and use CPU to do some simple controls through GPIOs. Is Zedboard suitable for the job? Thanks, Shuguang
  24. Hi @SGY, Welcome to the Digilent Forums! The Zedboard is a collaboration between a few companies. Due to this situation, there are a two places to look for good documentation. Here is the Digilent resource center for the Zedboard. The Avnet site is . The ZYNQ book was written for the Zedboard and the Zybo Zynq boards. The Zedboard OLED demo is written in Verilog. I would also look at the FPGA4FUN and Asic world for more basic non specific board HDL code. The Zedboard has a ZYNQ processor where some of the components like the DDR and USB UART bridge are tied directly to the Arm Core. These components will not be able to be used in the PL with HDL but can be used in the PS using the ZYNQ processor. I have attached an image that should help with visualizing this. best regards, Jon
  25. Hi @eric_holtzclaw, Welcome to the Digilent Forums! In your Vivado_init.tcl I would first try deleting the < in front of the F: and have the full path to the board files. Next, I would erase the "# test" text and have an empty first line of the file. It may help to make put the board files on the same drive that Vivado is on. I have attached my working .tcl file. Some of the older versions of Vivado i have installed requires a different file name(init.tcl). best regards, Jon init.tcl
  26. Have just started playing with the OpenLogger that just arrived. Did a firmware update and calibration via a Windows 10 VM on a macOS machine, and connected the OpenLogger to wifi, all went fine. Is wifi meant to be working? If so, consider the following as a bug report. If not, then what's the ETA looking like? OL firmware version: whatever the latest is (how can I determine this from a running device? the UI should have some method of viewing the connected device's firmware version (e.g. in device manager?)) env: Chrome Version 73.0.3683.103 (Official Build) (64-bit); macOS 10.14.4 (18E226) However when connected to the OpenLogger via wifi I see frequent errors, including - "Error Occurred Starting Or Running Acquisition" when interacting with the timebase and amplitude (i.e. mouse zooming/scrolling) - "Could not set AWG parameters" when interacting with the AWG controls, changing modes There doesn't seem to be anything in the browser dev tools console when these occur. (the console does show a bunch of warnings re. 't' plugin and a CORS policy error just on loading the page, but there's nothing additional when the acquisition error occurs). Repro: 0. OpenLogger connected to wifi 1. go to 2. start streaming 3. interact with the UI - scroll back and forth, zoom in/out 4. in very short order one of the above error messages pops up; at this point the UI becomes unresponsive and a page reload / device reconnect is required Occasionally the device will get itself so confused it won't connect at all (WFL reports "No response received"), and a OL board reset is required. PS: there needs to be some sort of error log mechanism, it's a real pain to try and capture the errors via toasts....
  27. set_param board.repoPaths This is the content of the first line. Vivado_init.tcl
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