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  2. Hi @APDC, I have sent you a PM. Thanks, JColvin
  3. Today
  4. Hi @J995, Based on the readme you attached, I'm guessing you are using Vivado/SDK 2018.2 and the 2018.2-2 release of the Zybo Z7-10 HDMI demo? A co-worker of mine tested the 2018.2-2 release and found that if they start the demo with the HDMI TX unplugged, and then start the demo, they receive the same HDMI unplugged message and upon attempting to change the resolution, the application freezes. If they plug in the cable, the unplugged message does not go away. They were able to get the pre-programmed static images (the blended test pattern and color bar test) to run with the TX cable
  5. Thanks , yea, just too may errors to mention here so I'll pick a specific TCP IP example and run with that in this thread . It seems that most errors I get is when taking the 2018 example IP and code , and import it into 2020 that there is some forward compatibility issues , even when running the update wizards . Some times the project/source code files cant find headers that are in the library even when all directory's are appropriately assigned . So it would be great if someone has a TCT/IP example project they can share ,already configurated for 2020 Vivado /Vitus, deployed and tested on t
  6. Yesterday
  7. Hi @Subbu, I asked other engineers about this issue you are encountering and determined the board you have likely has some sort of issue with the JTAG connectivity, which is not easily fixed. I would recommend contacting whomever you purchased the Arty A7 board from (probably Digilent directly or a distributor) to initiate an RMA. If you purchased the board from Digilent, I can give you some additional instructions in this process. Thanks, JColvin
  8. Yeah, but now that you know how to do it the next time will be easy. I strongly encourage using the XADC for all more serious Series7 projects, fan with heat sink, heat sink without fan or nothing at all. If you don't check on things you are just operating on assumptions. In electronics ignorance is rarely bliss ( for long ), especially of you are pushing your hardware. I kind of agree with you that LUT52% FF68% usage, with minimal or no IO being driven ( I assume ), and clocked at 200 MHz shouldn't cause your platform power supply to roll over and play dead... but that's the nature of th
  9. JColvin

    Fixed Point

    Hi @saad007, Digilent does not have any specific examples for these IPs. The best resource for them would likely be Xilinx's own documentation on their IPs. Thanks, JColvin
  10. Hi @KG1242, I don't believe Digilent has any examples using the Xilinx HDMI IP. There is an example HDMI project in the Nexys Video Resource Center, https://reference.digilentinc.com/reference/programmable-logic/nexys-video/start#example_projects, though I don't think it specifically uses the Xilinx IP. There is also a video processing demo done by a third party (Adam Taylor) for the Nexys Video that is linked on the Nexys Video Resource Center, but it looks like it uses the Digilent made IP as well. Thanks, JColvin
  11. Thanks for your answer @attila I kind of forgot that I posted here so sorry for the late reply! I'm actually not using a BNC adapter, I'm just using the jumpers that are included in the base unit so DC coupling is the only option. I'm quite sure that all the setting are correct and that I'm using it correctly since it worked well before. I think something must have happened with one of the components in channel 2, it kind of looks like there is an inductive connection between 2+ and ground that grounds the probe when the voltage is static. I would guess that there could have been some cu
  12. Hello Delmas, I would ask: what have you tried? But really, help us help you. What issues are you having? Does the host app compile? Do you get link errors? Something involving makefiles? As far as I can tell, Vitis examples don't even know what boards they'll be running on and they add a lot of useless cruft such as the I2C handshake which shouldn't be there (and it isn't compiled as it's guarded by #ifdefs). Do you get to at least complete PHY initialization?
  13. I think we have managed to find a common point, thank you. I don't know how I will do in other chapters of this book but for the time being, I would be happy enough with putting a stop on this issue. Pulling in the XADC measurement took more effort in finding the documentation than the work itself but the process has been straightforward. The first batch of runs I made passively cooled. I tried: 6 stages, no buffers, 100 Mhz - LUT29% FF30%, Vivado estimations 2.415W, 52.9C. Highest tmax reported 54.7C after about 4 hours. 6 stages, full buffer, 200 Mhz - LUT 29% FF39
  14. Hello @attila , I ran the above code in C++(down below) with @RichSCorp utilizing the SDK and it doesn't seem to work. Can you please look it over and help us identify the error. FDwfAnalogInFrequencySet(this->hdwf, 1000000); FDwfAnalogOutNodeEnableSet(this->hdwf, this->outBNC1, 0, true); FDwfAnalogOutNodeOffsetSet(this->hdwf, this->outBNC1, 0, 0); FDwfAnalogOutNodeAmplitudeSet(this->hdwf, this->outBNC1, 0, 1.0); FDwfAnalogInTriggerChannelSet(this->hdwf, this->inBNC1); FDwfAnalogInTriggerTypeSet(this->hdwf, trigty
  15. Hi @blipton In the latest beta version you can find "USART PS/2" interpreted for the Logic Analyzer. https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ Could you provide more detail about the protocol ? it sounds similar to SPI without Select signal.
  16. Since you are using the ATLYS I feel that it's appropriate to warn you about those USB Type-B plugs. The only thing holding them onto the board is a thin strip of copper on the mounting surface of the PCB. I've had about a 50% failure rate with these over repeated use; that is the connector, and copper signal traces being ripped off the board. One problem is that some of these have a fairly high insertion force requirement and the surface mount USB connectors just aren't up to the task over time. It isn't only cheap FPGA boards with the problem. I have a couple of 'not cheap' nVidia dev boards
  17. It's kind of a shame that Digilent was historically so sloppy with their PMOD designs on the FPGA boards. Very few PMODs are connected to clock capable pins on the FPGA. A problem is the 12-pin connector... it really limits what you can do with it, and I think that the decision to double the GND and Vcc pins is generally not all that useful and certainly exacerbates the issue. A simple PMOD with holes for an external clock module would make the whole ecosystem better... but what's the point when almost none of the FPGA boards can make use of it? I strongly advise Digilent to reconsider th
  18. TMDS requires 50 termination to function. The HDMI INput connector J3 uses the TMDS141 TMDS re-timer device to accomplish proper termination. You need to be careful with HDMI. Because of those 50 ohm terminators you end up with a path for external devices to pump current into the ATLAS Vccio rails... so the system power-up sequence is important. You don't want to drive current into the FPGA rails before the ATLYS board has been powered an it's own power rails are stable. Just connecting supply rails between two independently powered boards without carefeul current management is scary. Ide
  19. A last question @zygot, please. In case I could not find some clock generator board to clock my atlys, and knowing that the HDMI D plug shares pins with the pmod plug, especially clock pins, what do you think of this : Could I use some video device (for instance, some raspberry pi that I own), configured to display @720p and plugged into Atlys HDMI D port ? Would this, in your opinion, provide a decent 74.25MHz system clock for my scheme ? EDIT : I don't even know why bother use JA Type D HDMI plug, I could simply plug the raspberry into J3 Type A HDMI connector to get clock s
  20. I am programming Genesys2 with Vivado/Vitis 2020.2 and could write and read Quad-SPI using AxI_QUAD_SPI LogiCore and Xilinx library spi_v4_7 ( including xspi.c ). I could use MicroBlaze, HDMI (source and sink), VDMA and MIG. However I could not find a way to wirte and read the SD CARD on the board. I tried xilffs but the functions such as f_mout, f_open and f_read were rejected by the Vitis compiler. I had no problem to read/write SD-CARD with Zybo, Zybo-Zu and Zedboard. I read the article "SDSPI controller specification" introduced by Gisselquest Technology in this forum. Q1) I would li
  21. Quickbooks Error 3371 can be solved by this method also- Recreate all the damaged entitlementDataStore.ECML file & solve the license & registration glitches then fix Microsoft .NET Framework, MSXML, and C++ errors by downloading Quickbooks Tool hub and using Quickbooks Install Diagnostic Tool, Now reinstall by doing a clean installation then run reboot file and update your Quickbooks to the latest version.
  22. Hi @reddish You have the updated manual in a private message. It will be included in the next software build. The deprecated undocumented ones at the end of the dwf.h have alternatives.
  23. Hi @JColvin, I described 3 stages on a "bad" board behaviour: First, I poweron the card, with Digilent adapter USB unconnected from PC. GPIO2 shows low (38mV). Second. I connect Digilent USB to a PC. GPIO2 remains low (38mV). Third. I launch Vivado Hardware manager. Open Digilent adapter and start JTAG scanning. Then GPIO changes to high level (3.338V) Best regards, D. Carrasco
  24. Hi @Jesko, What board are you using? The pins I listed out are specifically for the raspberry PI header. The pins you listed (10-13 anyways) would be for an Arduino styled header. There is some Arduino styled code on the Pmod OLEDrgb Resource Center, https://reference.digilentinc.com/reference/pmod/pmodoledrgb/start. Thanks, JColvin
  25. Hi @Subbu, I apologize for the delay. I'll have to dig into this some more. From what you posted, the Vivado Hardware Manager is sucessfully able to detect the board and it's serial number (210319AB51BBA) but apparently not able to connect to the downstream FPGA. Adept is seemingly reporting the same details. The cable drivers are what Vivado/Vitis uses (as does Adept; Vivado and Vitis use the same drivers) to communicate the FPGA device over USB. I'm also surprised to see the board running its embedded flash demo at 115200 baud, since I thought most of those projects were inste
  26. Hi @Daniel Carrasco, I am a bit confused. You stated two different times that the GPIO2 (PS_SRST_B) are at logic low levels (30 mV), but then say that GPIO2 is found to be at logic high level (3.3 V)? Which voltage value is found on GPIO2 (pin 7 on the JTAG SMT2-NC module)? Thanks, JColvin
  27. Last week
  28. I have tested it with and without the BNC extender board. When the when the WaveForms software is started an error appears on the screen saying no device found. The Green LED at the center of the module never flashes. I've tried multiple USB cables and PC's. MikeC
  29. Hi @PoroCYon, welcome to the forums! An option that resembles the first you proposed: you can create an AXI peripheral with its ports either grouped into a GPIO interface or just on four-bit _i, _o, and _t buses, then use the Pmod Bridge IP from our vivado-library repo (latest released download here) to handle the constraints, connecting your IP to the bridge in a block design. I've attached a screenshot of how this could be wired up in the block design below (it uses an RTL module where your AXI IP would fit in). Connecting a Pmod interface to a board-flow port requires some additio
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