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  1. Yesterday
  2. Hello from Paris France, I've just received a nice Basys3 and Pmod I2S2. I plan to use these for sound synthesis. I'm quite confident with DSP and synthesis stuff as I experiment my algorithms on the Axoloti (an Arm based plateform). I plan to use the Artix 7 as a sidekick for the Axoloti. It will be dedicated to a rather simple, yet usually CPU intensive, algorithm such as Additive Synthesis or Formantic Waveform Synthesis. Well, that's my long run project. For the moment, I'm back to FPGA/VHDL 101 and blinking leds. I've already browsed the Forums and i want to thank everybody for their insight :D
  3. harika

    pmod wifi

    1) But how the board is connected to router? 2)while working in sdk when we create new application the jumpers must be in SD mode,when we program fpga jumpers must be in Jtag mode am i right please correct me if i am wrong.
  5. Last week
  6. Hello! In pattern generator. When I set "Duty" for "Clock" signal to small value like 0.01% ... 0.1% preview turns to noise. Also happen with "Pulse". But the signal is good like described by settings. With best regards, Mikhail.
  7. Hi @jpeyron I had improved my code and now i am sending the data from Zybo to Arduino successfully but now the problem is that i am receiving that data on Arduino serial monitor continuously. What could be the problem? Actually I am sending the ASCII value of character 'U' and receiving the "U" at Serial Monitor of Arduino but it i am receiving that character continuously which i don't want. regards, AQ
  8. Hi digilent. Is it possible to log the following values ( DC , TRUE RMS , AC RMS ) for each channels every second, a little like, but only by using python ??? Thanks Michael.
  9. Yacov Cohen


    My question is if there are some news when trying to measure 8 inputs?
  10. Hi, I just got an Arty S7 board, and I'm writing a DDR3 controller. The schematic for this board says that it has a MT41K128M16JT-125:K (a 1.35V DDR3 chip). The manual also states that the DDR3 runs at 1.35V and suggests using 1.35V IO. However the board I have received contains a PMF511816FBR-KADN. According to its datasheet, this is a 1.5V DDR3 chip. My initial experiments show that this RAM works, but I am concerned about the voltage mismatch. Please could someone confirm the situation? Thanks!
  11. harika

    Pmod wifi

    Sir, do we need to place ethernet cable to zedboard from router to get ip address? Can u please make a video regarding this project on zedboard as fast as possible because the suggested video is about arty board and also they are using pmod sd
  12. Hi @RedMercury, I have reached back out to our layout engineer to find out this detail for you. Thanks, JColvin
  13. After spending more time digging around on this, I discovered that this is an issue with residual files in the pycache after a python version update, and has nothing to do with the WaveForms SDK. If anyone else encounters this error, clear the cache and see this post for more details:>
  14. Hi @spri, I have moved your question to a more appropriate section of the forum where the engineer much more familiar with WaveForms SDK will be able to see and respond to your question. Thanks, JColvin
  15. Hello, I am currently working on a Project involving a Microblaze core on an Arty A7 board. Everything works fine by programming the board nonpermantly from Vivado and SDK. I am using 2018.3 and even tried 2019.1 today. However, there is a problem with the startup of the firmware, when I upload it to the flash memory following the "How To Store Your SDK Project in SPI Flash" tutorial. First of all, when I power the device, the FPGA is initialized which I can see by an LED lighting up as it is hardwired to a constant 1. "Done" LED also lights up. The problem is, that the bootloader does not load anything. When I debug the bootloader by printing something over UART (verbose mode), there is nothing. When I run the system debugger from SDK with the bootloader code, the bootloader starts and sucessfully reads the flash from Address 0xC00000 and my application starts on the microblaze. What am I doing wrong and what can I do to find the problem? Best regards
  16. Is the distance to the connector the distance to the through hole, or does it take into account the extra leg length for the top row of pins versus the bottom? Im designing a connector with two differential data lanes and a differential clock lane. Thanks!
  17. I just updated Python from version to 3.7.3 (a big jump, I know... but it was time). Now, when I try to run an application I created using the WaveForms SDK, I get the error, from dwfconstants import * ImportError: bad magic number in 'dwfconstants': b'\x03\xf3\r\n' I just updated WaveForms, and the error persists. What does it mean? How do I fix it?
  18. jpeyron

    Pmod wifi

    Hi @harika, What WIFI IP Core example are you currently using? If the example is the HTTPserver please attach screen shots of your HTTPServerConfig.h as well as deWebIOServerSrc.cpp. Please attach screen shots of your Vivado block design along with your SDK. best regards, Jon
  19. @Ahmed Alfadhel, Why not run a simulated sweep through the band and read out what the actual filter response is? Dan
  20. Hi @tmwhitt, To verify the Pmod AD1 is correctly working please use the Pmod DA1 IP Core with the Pmod Port JA using tutorial link above. Using the Pmod Ad1 IP Core are you getting expected results? Also please attach a picture of you physical set up and Verilog code as well if possible. best regards, Jon
  21. The top two are using a 3.3V Vcc, the bottom one is with a 5V Vcc
  22. Whoops, the files were too large and didn't attach correctly, here are the compressed versions of the images.
  23. Thank you for the responses! @JColvin, I am applying from 0-1V to the A0 pin, the signal is just a DC voltage. @jpeyron, currently I am only trying to use one channel in. If I use a 5V Vcc and use two resistors to drop D0 (or SDATA) down to ~3.1V, the Verilog code I have works to read in the values. My issue is when 3.3V is applied, the device doesn't behave as expected. I have attached three images, where the white trace is SCLK, the yellow trace is CS, and the green trace is SDATA. One is using the 5V Vdd, which shows it behaving as expected as I adjust the input voltage. The other two images are with a 3.3V Vdd, where they are at two different input voltages. I do notice that when 3.3V is supplied, sdata is sometimes a 1 during the first couple cycles when it should only be zeros, which is odd to me. Thanks again!
  24. Hi @shahad, I split this thread here so we are not posting on a completed thread. Please attach screen shots of your block design and the top, xdc file. Here is a VHDL Nexys 4 DDR project that uses the USB UART bridge. best regards, Jon
  25. Hi @libswig, Instead of adding the Cora Z7 XDC you should add the XDC file for the ZCU104 found here. I attached a screen shot showing that you will need to expand the associated files to be able to select the xdc for the ZCU104. You should use the Cora Z7 XDC as a reference of what pins will need to be uncommented and how to set up the ZCU104 xdc. I believe you will need to add the clocking wizard from the IP catalog under the flow navigator. Use the settings from the attached screen shots above. best regards, Jon
  26. Hi , According to the Tfilter tool parameters (first attached picture) and the frequency response of FIR IP core (second attached picture) the passband is : 16 kHz to 17 kHz, and stopband1 is: 0 to 15.5 kHz and stopband2 is: 17.5 kHz to 24 kHz . I tested (simulated) the filter with 16 kHz , 24 kHz , 64 kHz, 500 kHz, and 1000 kHz. The simulation results are shown below respectively. 16 kHz 24 kHz 64 kHz 500 kHz 1000 kHz I noticed there is no attenuation in each of 24 kHz, 64 kHz !!! While 500 kHz, 1000 kHz appeared attenuated. The question is: why the FIR filter doesn't attenuate the frequencies that are located in the stopband? Note :in each attached picture the first sinewave is the input to the FIR Filter, while the second one is the output (filtered). Thanks.
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