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  2. Hi I wonder how is it possible to fill the 1Gb of DDR memory at Zynq 7000 with the samples captured from ZMOD ADC 1410 at 100 MSa/sec. I read the documentation of ZMODadc14110axi and find that the module use a circular buffer which can't be read and write at the same time. However, my inclination is that for real-time signal processing the buffer should be able to read and write at the same time. Or, you have ping pong buffer that one is reading while the other one is writing. Also, another question is that the data processing speed is faster than data acquisition speed? I mean the time
  3. Today
  4. Hi @Kvass, I'll have to look into this some more. I have a vague recollection about there being something weird about FMC JTAG connectivity, but I don't recall the details well enough at the moment to provide any useful detail. Thanks, JColvin
  5. Yesterday
  6. Hi @CuriousRF, Welcome to the Forums! If you haven't seen them already, these two threads might be of interest to you: Thanks, JColvin
  7. I love happy resolutions to frustrating problems. Digilent could be more proactively helpful for basic customer issues. Perhaps a FAQ section or topical list of problem resolutions that customers could sift through on the web site? We all know that trying to update all documentation to keep up with problems caused by Xilinx tools version releases isn't feasible. But there has to be a better way, right?
  8. So, I uninstalled Vivado 2019.2, and installed 2018.3. The CMOD A7 connects in the hardware manager and I was able to program it through USB. Thanks so much zygot.
  9. Most of Digilent's FPGA boards use an FTDI USB bridge device that can have 2 or more endpoints, all using one cable. One is used for JTAG and one as a UART. Vivado Hardware Manager communicates through the JTAG endpoint, so COM4 isn't what you are looking for. If you look under Universal Serial Bus Controllers in Deevice Manager you should see a USB Serial Converter show up when you plug in a cable attached to your board. The CMOD-A7 uses the same cable for programming and UART communications so a COMxx device will also show up. So how do you know what device goes with your cable? Look at
  10. Hi @rmccormack1, There's an not-yet-fully-released version of the board files that helps to fix it available here: The solution is to reconfigure the MIG to accept a 100 MHz system clock (avoiding the upstream clocking wizard entirely, and just connecting the system clock to the 100 MHz clock pin) and produce it's own reference clock. This also entails constraining the sys_clk_i port in an XDC and, in the case of the USB104, either tying off the sys_reset or connecting it to a button through an inverter m
  11. So I have a block design that I have created. I go through the synthesis and implementation and I get no errors. When it comes time to generate bitstream, I get this error: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are design_1_i/clk_wiz_1/inst/clk_out2. I want to know why I am getting this error?
  12. Has this issue been fixed? I am running into this problem as well.
  13. CC17

    CORA Z7 CAD file

    Hi, I am trying to create a model of an enclosure including the CORA Z7 board. Is there any way that a CAD file like a step file could be generated for that? If so, could it be provided? Thanks
  14. Thank you, thank you, thank you, for answering, and not only answering but providing some very plausible solutions that I shall begin to undertake right after this reply. I suppose I did a mini rant there, but I see you might be a ranter, as well. To answer you questions: Windows 10 A device shows up on COM4, but I am not certain that is it. I am just doing FPGA, so I don't use Vitis. I will try an earlier version of Vivado. Thanks again for your insight and helpfulness in my mini crisis.
  15. The JTAG cable is not being read at all when anything is connected to the FMC-LPC connector. I have a new Genesys-ZU 3EG board which I am programming with Vitis. I am using the JTAG HS1 adapter to load my program into the board. This works when nothing else is connected to the board. For my project, I connect another board to the FMC connector. I am using this board. When the FMC card is connected, my PC stops recognizing the JTAG connection. The connection is invisible to both Vitis and Vivado. I have nothing else connected to the Genesys board nor to the FMC adapter. A
  16. Let's see if we can solve this. What OS is Vivado running on? Have you queried the OS tools to see if any USB devices get enumerated when you plug in the USB cables ( and for the Basys3 have the board powered on? ). For Windows this would be Device Manager ( usbview.exe is more helpful ) and for Linux it would be : dmesg | grep usb lsusb lsusb has command line options for more verbose replies. Vivado 2019.2 isn't the best version to use as it was the first time Xilinx abandoned the SDK tools and forced everyone to use Vitis. I still use Vivado 2019.1 for normal FPGA de
  17. Caveat to my own post. I have followed the connection guide provided by Digilent, to no avail. Also, the guide is severely outdated as all the Vivado screenshots are from older versions. I am using Vivado 2019.2. Is anyone else having this issue? Has anyone else that has had this issue resolved it? How? And, can someone at Digilent please update the connection guide to reflect the newer version of Vivado? Please?!!!! OMG, how frustrating, because it should work!
  18. Hello, I have two FPGA boards from Digilent, both with Xilinx Arty A7; Basys3 and CMOD A7 15T. Neither one will connect through the hardware manager on Vivado. I am able to use the Basys3 by generating a raw bit file and saving it to a USB memory stick and inserting it into the Basys3, but the CMOD A7 does not have a USB port for raw bit files. How frustrating that the hardware manager does not connect to any board I plug into my computer. I have seen a few forums that outline the same issue, with NO ANSWERS. This is unsatisfactory! How can I have two different boards and neither will con
  19. Would it be possible to do a stress test on the DD with the python SDK? For example send data at a faster rate than it can receive/send back and measure at what rate does that happen?
  20. I was using an Ubuntu Virtual Machine running on Windows. Solved by using WIndows.
  21. If you are on external power already, then you are hitting most probably the current limit of one of the power supplies. Since it sounds like you are increasing the frequency of the programmable logic, most probably the VCCINT supply (1.0V) is getting limited. Since power consumption is project-dependent, do a power analysis in Vivado with the implemented project. However, only very complex designs should be hitting the 2.6A current limit on the 1.0V rail. Your project might not even meet timing constraints anymore with high logic utilization and high operating frequency. In other words, you m
  22. HI, I am trying to test how fast I can read and write to the Digital Discovery using the Python SDK. I am using the DigitalIO example. I timed the FDwfDigitalIOStatus and FDwfDigitalIOInputStatusnoticed functions and got the following: FDwfDigitalIOStatus, (fetch info from device): 0.6s FDwfDigitalIOInputStatusnoticed, (read pins): 0.7s Is seems like a long time, is this as expected?
  23. Hi @Alejandro-Dev See the earlier mentioned SDK manual pdf
  24. Hi, recently bought one FPGA Arty A7-35T. I had built out some simple projects by using this FPGA board and they are successful. However, when I reconnect it to my computer, the Vivado hardware manager cannot auto detect the board. I had tried uninstall the driver and reinstall the driver. But, the board still cannot be detected. When it is connected to the computer by using the usb port, the power up led (LD11) and program led (LD8) are light up. Besides, the LED LD9 & LD10 also been light up. For my understanding, LD9 & LD10 is the transmit and receive indicator for the UART connecti
  25. I'm not sure if this is the right place to report what I think is a bug in waveforms. I'm using version 3.16.3 64-bit on windows 10. I was having difficulty using averaging in the scope timebase controls to eliminate some noise. When I click on 'single' acquisition, the scope appears to trigger the appropriate number of times (e.g., 100) before displaying a new trace. But the noise is not reduced, as if the scope is showing me just the trace from the first (or maybe the last) trigger. Clicking on 'run' similarly counts the appropriate number of triggers and then displays a new trac
  26. Hi Guys, I am using the Analog discovery 2 board and I want to generate a custom signal with a sampling of 100 Hz. I have modified the record code provided in the SDK and it is working perfectly , but code isn't working with sampling frequencies (hzAcq) lower than 1 kHz, it simply doesn't go into acquisition and doesn't give anything. Could you pelase let me know what is the issue. Below is the code: #declare ctype variables hdwf = c_int() sts = c_byte() hzAcq =c_double(1000) #sampling freq nSamples = 4096 rgdSamples = (c_
  27. Last week
  28. I can confirm that Vivado 2019.1 works as per the Nexys 4 DDR example instructions. When I have some spare time I will have compare the code generated by the two different versions to see what gets changed.
  29. Right now I'm trying to consume digital Input measurements and use them in a C++ (Linux) application. Currently, I'm writing to file from the Waveforms application. Then running the c++ application which reads from the file which waveforms is writing to. Is there a better way to do this? Any Ideas would be appreciated . if there is a way for waveforms to send udp packets that might also work for this application... EDIT: I see there's a way to do this with the sdk but I'm having trouble linking the library with CMAKE. Has anyone used CLION+CMAKE with this dwf dynam
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