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  1. Today
  2. Hi @Regindt There is no option to flip the x axis but you can also the Scope to capture such data. To capture more data than the device buffer size (8/16k on AD) the Record mode can be used.
  3. Thank you for this information. Looks interessting and I am curious about more details.
  4. Hey When i use the logger program inside Waveforms, then it works as it should, but the x-axis is reverse. As you can se in the picture, then I logged for almost 30 min, but point 0 for the data is at 0 min and the 0 min is when i shot of the logger. So now all my data is reverse. Is there some way for to solve this problem?
  5. Hi @vata The Analog Discovery has two input ranges (gain steps) of about 5 and 50 Vpk2pk https://reference.digilentinc.com/reference/instrumentation/analog-discovery-2/reference-manual#scope_input_divider_and_gain_selection
  6. Hello @mehmet, Vitis does not come with example hardware platform for our boards by default. If you want to reuse the platform multiple times and not have to search for it in Vitis every time, you can add it to Xilinx\Vitis\<your_version>\data\embeddedsw\lib\fixed_hwplatforms. For example, I added a platform named system_wrapper.xsa to the folder and it appeared as in the photo listed below. If you want to try out some existing demos for the Nexys Video that make use of the Microblaze, you can check out these: https://reference.digilentinc.com/reference/programmable-logic/nexys-vide
  7. damrr

    utc time to epoch time

    Hi, i am working on gps to parsing nmea data from gps receiver through uart. i need to convert result (gga) of utc time to epoch time. i am looking for calculation part how to convert. thanks for advance
  8. Thank you for your comments. I'll check web pages you linked! Personally, I was guessing the procedure. -Using any D.L. framework, create a weight file that matches the real configuration (FPGA channel or I/O) -Rewrite it to C++ and put it on FPGA with Micro-blaze (soft CPU) -Based on FPGA input: High/Low, FPGA provides High/Low following the weight file. But, if #of FPGA I/O is not sufficient, a couple/few of FPGA must be used. In that case, how is communication among them done.... Anyway, I have to investigate it. PYNQ is probably helpful to brus
  9. Hi I am using a first generation Analog Discovery. Running through the example AnalogOutIn.py included in the sdk which works ok. The issue I have is when I attempt to adjust the channel range. There is a line in the example dwf.FDwfAnalogInChannelRangeSet(hdwf, c_int(-1), c_double(4)) I adjust the value passed in the second argument but this adjustment e.g. to 0.4 does not clip the signal set to have amplitude 1. Is there any guidance?
  10. I had a technical question about the temperature ratings for the JTAG-SMT2-NC: Surface-mount Programming Module. Why is the minimum storage temperature higher than that of the minimum operating temperature (and likewise, the opposite for the max. temperatures)? The reference I have attached is from the manual PDF, but I also checked the Wiki as well. Thanks
  11. Yesterday
  12. Hi @fp99, Not particularly for this application. Differential signals tend to be routed such that the pairs are together and of very similar lengths, but if your design does not specifically take advantage of this, it will not matter. Let me know if you have any questions about this. Thanks, JColvin
  13. Hi @attila I had already tried that as a solution, the decode is still incorrect. Note the "DIR" bit is "1" but the decoder says "Device: 0".
  14. Hi @anshumantech, Normally I would recommend the Digilent Adept software and an associated programmer like the JTAG HS2, but as noted in the JTAG HS2 reference manual, https://reference.digilentinc.com/reference/programmers/jtag-hs2/reference-manual#supported_target_devices, 9500 series CPLDs are not directly supported as per UG908. I'm not certain why the Spartan 3-AN chip was not able to programmed; the best resource I can point you towards in terms of programming it would be UG332 from Xilinx, https://www.xilinx.com/support/documentation/user_guides/ug332.pdf. Thanks, JColv
  15. Hi @Sid Price I see now... Your signal is active on rising edge so you should use sample on falling: if(clkPrev != 0 && clk == 0)
  16. I have the Arty A7-100T board and I have worked through this QSPI flash boot tutorial: https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start I am using Vivado 2019.1 with SDK as stated in the tutorial. I am able to get this to work as long as I program the application in flash first before I then program the bitstream and bootloader. If I do it in the order as in the tutorial (program the application last), the application never executes. Most likely the bitstream is not loading because the DONE LED does not illuminate. It is as if programming the ap
  17. Gdurand

    Arty Z7-20 USB HOST

    I almost managed to integrate the IP. There is only one AXI clock problem left. In the meantime, I got around the problem by putting a USB UART Pmod driven by an AXI Uart lite. Hopefully you will get this IP finalized soon.
  18. Hi @T.O, Digilent does not have any materials on machine learning, but you might want to look into these pages I found here and here. Thanks, JColvin
  19. JColvin

    Arty Z7-20 USB HOST

    Hi @Gdurand, This IP is not yet completed, as noted in the associated documentation pages available here: https://github.com/Digilent/vivado-library/tree/master/ip/usb2device_v1_0/docs. I do not know the timeline for when this IP will become in a stable release state. Thanks, JColvin
  20. @attilaThe only change I have made is to the output function so I could check what the "DIR" bit value was: function Value2Text(flag, value){ switch(flag){ case 0: return "X" case 1: return "Start" case 2: return (value?"Host: ":"Device: ")+value.toString(2) case 3: return "CMD:"+value.toString(16) // hexadecimal representation case 4: return "Cont:"+value.toString(16) case 5: return "CRC:"+value.toString(16) case 6: return "End:"+value.toString(2) // binary representation default: return value.toString(16) } }
  21. Hi @josif Sorry but I can't help. Additional AC coupling may be in the amplification/filtering stages (if it has such) or in the main IC. Last year I have also ordered something similar. I tried to modify the mono-mic input to be stereo line-in, since the IC in it (and the layout) had such capability but I had no luck. Probably it was disabled with some fuses or it was reprogrammed...
  22. Hi @chrisdoe In about on month ADP3450 see: https://fb.watch/36SpWxtyIn/
  23. Hi @Sid Price The debugger does not receive capture data, but some arbitrary values for basic testing of the script. Could you post your script? I think you have developed it further since the one I posted should not return "Device: 0" only "Host" or "Device"
  24. Hi @Roiberts Such long low pulse is break condition in UART: https://en.wikipedia.org/wiki/Universal_asynchronous_receiver-transmitter#Break_condition
  25. Szia @Andras Thank you for the dwf.cs observation. See the following post:
  26. Hallo Atilla, My students and I are having a project trying to explore WaveForms with USB soundcard to it's maximum. We designed a simple OPAMP adapter and removed the blocking capacitor with the polarizing resistor at the microphone input. We expected to see the complete signal (DC+AC) on the oscilloscope, but the latest USB sound cards we obtained did not pass the DC voltage. An older sound card I had from 3-4 years ago did not block the DC signal. Can you help us with this issue? The old card reported to the "lsusb" command as: 0d8c:000e C-Media Electronics, Inc. Audio Adapte
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