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  2. Hi @JamieRI, If you bought them from Digikey, you would need to contact Digikey directly about a replacement (Digikey will then contact Digilent separately). I do not know Digikey's RMA policy though with regards to time frame, but feel free to reference this thread regarding the probe calibration. Thanks, JColvin
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  4. Hi @BParsons, I have sent you a message about this. Thanks, JColvin
  5. @zygotCorrect. The answer seems to be NO, and I got it fairly early on in this thread. The powers that be will just need to change their requirement. As it was explained to me it stems from the architect's desire to minimize the number of hard-coded dependencies between all components of a finished product, including hardware and software. Thanks all
  6. Hello JColvin, I am also interested in this licensing. Please contact me. Thank you BParsons
  7. It seems to me that by the time you are writing software you have already committed to clock frequencies for your AXI bus and know the frequency of the clock that is driving the AXI bus and IP logic. Voila, you have enough information needed to estimate the hash rate. I don't see how, by the time you have a configuration file you don't have all of the information that you need. As for de-coupling the software from the IP execution rate I don't know the exact requirements but suspect that you will need to add some additional complexity to your IP if knowledge of hash execution time is a securit
  8. Hi @ToddA, I have sent you a PM regarding your options with the Rev E Zedboard. Thank you, JColvin
  9. Further: Here's an example of a component that adjusts itself at synthesis time. The ZYNQ7 Processing System component adjusts its number of external interrupt inputs at synthesis (or is it validation?) time according to the number of incoming signals (the width of the incoming concat component output bus). When first added and connected the block design shows a mismatch between the input signal and port widths, but this is somehow corrected at synthesis and the block diagram updated with the correct widths. This led me to believe there were perhaps some Verilog accessible net or port attri
  10. The first machine's hardware is too new for a 4.19 kernel. It looks like that machine can't run a kernel old enough to make Waveforms happy. I'll have to stick with running waveforms on older machines.
  11. Lots to unpack there. Yes, I did look at the links you provided, and it is indeed it is trivial to measure one clock frequency using another known clock. But that's the problem, at component design time there are no "known" clocks. Ok, Your CV has been noted. I wasn't really looking for a discussion, but rather an answer... but since you asked: Hypothetical: I have a component which implements a generic sha3-256 hash function in a 24 stage pipeline generating one hash per clock. The component is implemented as an AXI slave controlled and queried via a register mapped interfac
  12. Hi Attila, A year ago exactly (I really coincidentally just decided to send you this exactly 1 year from when it was posted ... go figure!!!) you posted the following: Posted September 30, 2019 Hi @iDetect Soon you may find devices at Digilent better suited for your needs. I'm planning to add support for lower latency captures with Analog Discovery, but it will take some time to implement it. Thank you for your post. Such feedback/requests direct the soft/hardware developments. Wondering if there is any news in this 'lower latency' realm? I have an appli
  13. Hi @Liur1996, We have some links on how you can run LabVIEW with the Analog Discovery 2 here: https://forum.digilentinc.com/topic/20241-labview/. Let me know if you have any questions. Thanks, JColvin
  14. You didn't bother to read the project material that I've referenced, but OK I don't care if you don't. Since you are the OPI, if you can't describe this mysterious generic application with no known frequencies then there's not much point in having a discussion about an unknown application with unknown requirements. Measuring an unknown clock period using a known clock period isn't difficult or particularly innovative. I've been doing logic design for a long time and have never needed to address a problem the way you seem to want to. The way that synthesis and place and route works i
  15. I am the OP! I think you're missing the point. The component is generic, intended for use in various designs and at various frequencies. I don't care how and who generates the fixed frequency input cock, I just need to know its frequency. Sure, measure it on the fly, but then I'd need a known reference clock to measure it against.
  16. That's not the same thing. If you want an example of an HDL design that uses a programmable clock module to change the operating frequency on the fly and a way to measure the clock frequency in HDL and software as it's running see the source code for this project: https://forum.digilentinc.com/topic/2898-differential-pmod-challenge/ I think that I'll wait for the original poster of this question to explain what it is that he means. I'm really arguing that the idea that you need to create a solution to a problem without some a priori knowledge of the clock frequency is wrong, and unn
  17. It is a simple requirement. Questioning it doesn't answer the question. The requirement could be based on something as basic as needing to report the operating frequency of a given component to software via a mapped register interface.
  18. Indeed, that is exactly the question, better expressed. Yes, I presently use a module parameter to manually specify the component's input clock frequency. There doesn't seem to be a way to automate this!
  19. Oh... so perhaps the question is whether or not one should try to design a 'universal' component or module IP that covers any possible use case. I would think that the answer to that question is no. But you and I are engaging in speculation; unless you know more than I do about what @W.Dis trying to accomplish.
  20. @W.D, The latest picture is certainly an improvement. I think that the question you really want answered is why doesn't the displayed waveform look like your conception of your idealized clock? The first question to resolve might be "how much of the displayed image can I assume to be a realistic representation of the actual signal being measured?". There are a number of ways to address that question. The first would be to look at how your scope is assembling the picture. Most scopes have the ability to display raw sampler data as dots instead of sin(x)/x. this would be the most faith
  21. The udev rules were there, and were doing what they were supposed to be doing (detaching the ftdi_sio driver). I think that another change that happened since waveforms worked on this machine is that the kernel got updated from 4.19 to 5.4. I _thought_ that waveforms was working on another very similar installation (same 5.4 kernel version). But, although the device was detected/opened, the application has a _lot_ of problems actually running. It hangs for 5-10 seconds a time (ignoring mouse/keyboard input). Starting/stopping the scope takes many seconds. That was with kernel 5.4
  22. That's the essence of the question - how do you find out what that "known" frequency is if you're designing a component which is meant to connect to external clock which you have no control over?
  23. Hi @mati, You have a private message. Regards, Bianca
  24. Hi @JColvin, Thanks for the reply. I've never heard of Vitis so I don't think I'm using that. This project was "completed" a couple years ago but now needs minor updates, so if Vitis is a new feature then I certainly haven't used it. I did use the SDK to write the code that was loaded into ARTY's flash memory. Thanks for looking into the serial connection issue.
  25. Perhaps someone slipped me some decaf this morning because to my way of thinking counting the clock cycles of a known frequency is knowing elapsed time. I've done more than a few SDRAM controller and DDR designs and that's how refresh intervals are determined. This doesn't involve a any mystery. Perhaps, DDR isn't the best example. I really can't think of a design case that couldn't be handled by normal static generic or parameter HDL statements.
  26. Hello, I have the same problem. Could you send me the firmware? Thanks!
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