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  1. Today
  2. Hello, I have an ADP3450. If I connect it both through USB and Ethernet, the device is found twice during device enumeration; but as far as I can tell the enumeration tAPI provides no documented way to distinguish between both connection types. The Waveforms software is able to do it, somehow, however. How does it do that? Second, I'm running some stress tests to see if I will be using USB or Ethernet for my application. Our application involves streaming playback data to the analog-out device. Using USB this is reliable (I can have it running for many hours on end without iss
  3. I accidentally erased my JTAG-SMT3-NC. Can you please PM me the instructions how to fix it?
  4. Hi @JColvin, Thank you for your answer. I gave a try with Arty Z7-20 and Vivado 2020.2 Linux. Seems to work properly: with just the Zynq IP, no strange things after running automation, generation of BD, synthesis and implementation are running flawless. See screenshot of the clocks: no error with ENET0. I couldn't test it for real: I don't have any Arty. About the Zybo: it works fine with Zybo, error is on both ZyboZ7-10 and Z7-20. We have to admit that the bug is specific to the Linux version, but it's quite frightening that such weird behavior can happen from one version
  5. Bummer. In that case, as already suggested by another user in this forum, would you consider releasing the PIC24 code you used on the NEXYS 3/4 boards to do the USB>PS/2 conversion? Thanks, Ruben.
  6. Hey attila, thanks for the reply! The thing is, I cant just create a pulse because I want the pulse lenght to vary within the same signal. And I did see the custom examples, but I just dont understand how they put the bits to create the signal they wished for. I hope you can help me with that.
  7. If I only copy the files to their destinations stated in the spec file, LabVIEW segfaults due to a nullpointer deref when using any of the Digilent VIs. There's a postinstall VI in the package, but this wants to use the registry functions, which are only available under Windows. What I have seen so far LabVIEW is best supported and works best on Windows and with its current issues I will not try and use it under Linux anymore. But thanks for helping.
  8. I tried searching the boards for this particular issue and couldn't quite find a similar threads. Some came close (like the X1 Carbon Gen 7 unable to use TrackPoint buttons with trackpad without suffering a momentary delay), but none hit the mark. Problem: Pressing Left and Right click TrackPoint Buttons simultaneously does not register as left and right click at the same time. Use case: Left and Right click pressed simultaneously is a popular command to move characters forward in MMOs. It is also used in many FPS's where right clicking acts as a zoom, and left click would act as fir
  9. Yesterday
  10. Hi @epsilon, I didn't update this thread, but I did learn back when I asked two years ago about this that Digilent had considered making such a product many years ago (2011-2012 timeframe) and that the Pmod itself had even gotten through most of the prototyping work, but the various higher-ups at the time decided to discontinue working on this product. In theory, I guess this product could be brought to light (I don't know if the design files and firmware still exist or not), but the hurdle that needs overcome is customer interest since 3 or 4 people asking about it on a couple of Fo
  11. Hi, I’d like to carry out capacitance-voltage measurements using analog discovery. I’d need to apply small AC amplitude and sweep DC voltage within the range of + - 10 V. I’ve realized the DC sweep is limited with + - 5V for the beta version of waveforms. Is there anyway that I can increase this limit? Thank you.
  12. Then you shouldn't be supplying any transceiver pin location constraints. The IP setup specifies the MGT location and supplies it's own constraints. You should always look at any constraints that Xilinx IP creates to avoid duplicating or creating conflicting constraints in your toplevel constraints file. I still recommend that you work out ac/dc coupling issues based on the schematics for the Nexys Video and your FMC mezzanine board. Getting a bitstream and obtaining acceptable performance are two different things.
  13. Hi @NAP64, The Genesys 2 has been supported in Vivado for some time. Based on what you described of the "part not found" error, there are two things that I think could have happened. One is when you initially downloaded Vitis+Vivado 2021.1, the Kintex-7 box was left unchecked during the installation process. You can see what parts you have included for that particular version of the Vivado via the Xilinx information Center. The other would be that if you added the Digilent Board files (available for download here: https://github.com/Digilent/vivado-boards) but didn't restart the
  14. Hi @tatheuss Such you could create using the "pulse" mode, see: DigitalOut_Clock.py DigitalOut_Duty.py DigitalOut_Phase.py DigitalOut_Pins.py or the custom examples: DigitalOut_Custom.py DigitalOut_CustomBus.py
  15. Thank you for the information. The problem is found. I use the 7 series FPGAs Transceivers Wizard IP in the project. It may be incorrectly set to cause an error in the synthesis of the IP. It is not a problem with the constraint setting. After I adjusted the 7 series FPGAs Transceivers Wizard IP settings, it can generate bitstream.
  16. Hi @Someone Officially the VIs are only supported under Windows but I've also used it under Linux and MacOS. The vip package is basically a zip archive. This can be extracted and installed/copied manually.
  17. Hello, I have another question. The problem this time is, that I dont fully understand how to create custom data array for custom signals with the pattern generator in my custom application. There is a little chart in the waveformsdk manual, where they specify the bits and so on. I don't know where to set the bits to actually get the signal that I want. My goal is to create a signal that starts high, goes immediately to low, stays low for 10 microseconds, switches to high and stays there for 26 microseconds. I hope you can help me out!
  18. @[email protected]'t seem to be inclined to respond to this question. Perhaps Dan personally, has developed a relationship with some one at Xilinx , but what exactly can he point to as a concrete example of something that has been corrected? After close to 30 years of using Xilinx tools I can write more than anyone would care to read about why I don't see a Reddit post as very worthwhile. But to save time I'll just present a recent experience. I was, for a couple of weeks, trying to get Vivado to use the correct PCIe MGT resources for a board the Digilent sells. No help from Digilent. I post
  19. Hi, I have posted something about this on the Github page of the project, but I'm not sure it was the right place so I'm posting it again here ... Please let me know if I should remove my post. I am currently trying to modify the OpenLogger source code, in order to add some features. But I can't get the code to compile for now ... The compiler error is attached here in a txt file as it is quite verbose. I haven't touched the code yet, just removed the "-fno-short-double" option from x32-gcc and x32-g++ compiler options, as it was creating some warnings. I
  20. Hi, It's been a while, but if we keep asking maybe some day it'll actually happen 😀: Any progress on a USB HID PMOD board? Cheers, Ruben.
  21. Hi Attila ; Thanks for your Reply. if i open WF for Digital Discovery device ;can let all DIN0~DIN31 PIN compare Ok and Can Set DIO32~DIO39 One pin Active when DIN0~DIN31 Compare ok.
  22. So what do you have connected to those pins in your design? From the Nexys Video Reference Manual: "The gigabit transceiver lane includes a receive pair, a transmit pair, and a reference clock input to the FPGA, all going to MGT bank 216. The transceiver lane is wired to lane 3 (GTPE2_CHANNEL_X0Y7). The reference clock is wired to REFCLK1 of the same bank (GTPE2_COMMON_X0Y1). It is important to keep in mind that bank 216, being the only one available in this FPGA package, is shared between the DisplayPort source and FMC ports. Depending on the exact application, simultaneous usage of the FMC
  23. Hi @jakey No. A WaveForms application can control one device at a time. Multiple devices can be controlled by separate WF app instances or custom app/script. The Digital Discovery has 24 DIN and 16 DIO lines and in Logic Analyzer can use 32bits at a time.
  24. Hi @HK2 Make sure the proper drivers are installed and configured. From software all formats and sample rate up to 384kHz are supported but it depends on the underlaying libraries/drivers/hardware what is natively supported or "emulated". The latest beta version increases the audio-output buffer which is useful at higher rate, bits and more channels: https://forum.digilentinc.com/topic/8908-waveforms-beta-download/
  25. Hi @MLopes The automatic resistor switching is available with CV/CC and custom script but the device has minimum and maximum current limits. In some experiments you may want to stick to a specific resistor.
  26. can used "digital discovery" 2 sets.for One user "windows 10" pc to test the logic analyzer with more than 32 ports at the same time
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