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  2. So, I have run the 2020 vitis zipped file from this is working. However, only question is: Why are the drivers for Vitis different from the drivers from Vivado? (also dma, intc, verbose not output when using vivado export hardware) I am concerned i cannot recompile the vivado and create a working project. Please advise.
  3. Additional: I compared 2018 and 2020 project. In 2018, Ising SDK, I am finding supporting C-files and main script which clearly should be driving the peripheral devices attached to Zynq. In 2020 project: I did not find "main.c" file. I am using Vitis (not SDK in 2020) Going form Vivado to Vitis, the hardware only outputs drivers for AudioStream_PWM, rgb_led, user_io. I don't have exported hardware for intc.h, dma.h, and verbose.h These were referenced in 2018 sdk main. I have att
  4. Hi Could someone point me to a reference design which uses a microblaze, ddr3, flash on the ARTY 7-100 board. I see such designs for the ARTY 7-35 board in Vivado 2015.1 but I have the 100 board. I took the gpio design (which has a microblaze, flash, ddr) for the arty7-35 board and I get a bit file. I then went and changed the board to arty7-100 and I get errors on the qspi_flash_sck [DRC UCIO-1] Unconstrained Logical Port: 1 out of 23 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board powe
  5. Hello Out team has downloaded this project "out of box" from your github site. We are using Artix Z7-20 board, Vivado 2020.1 and Vitis. We are able to generate the bitstream, export the hardware, configure platform / application and program FPGA. After doing so, and running the "Hello World" application, the HDMI-In and Out are both working. We see "Hello World" printed on teraterm console so seems to be functioning. However, buttons and switched are not having any effect on board LEDs. The RGB are not c
  6. Hello everyone. I'm working on a project wtih my friend. To accomplish it, we need to get 12 bit data from microphone and observe the output on LEDs. We couldn't figure out what is wrong with the code...spi_master.vhd mic3_xdc.xdc mic3.vhd spi_master_cs.vhd
  7. I am trying to implement my pmod mic3 on Basys3 board. My code seems true but I couldn't read any data. I mentioned my code in below. There are 3 modules: SPI_master, SPI_master_withCS, mic3 SPI_Master.vhd ------------------------------------------------------------------------------/ -- Description: SPI (Serial Peripheral Interface) Master -- Creates master based on input configuration. -- Sends a byte one bit at a time on MOSI -- Will also receive byte data one bit at a time on MISO. -- Any data on input byte
  8. Has anyone had success in driver implementation of the PCAM 5C on a Linux platform for zedboard?
  9. Bianca

    Nexys4 DDR

    Hi @Leo_W, So, I will try to explain to you something from that schematic.... I see that you opened a lot of topics, some of them answered by my colleagues. I suggest you keep all the questions related to a board, or to the same problem in the same topic, otherwise, we can't follow up with you. You asked about IC20... That is an LDO that makes the FT3V3 from the USB 5V0... all the FTDI environment is powered by that FT3V3. Like I said previously in a topic, the FTDI has an internal LDO that makes generates the voltage for the core. Initially I thought the FTDI was powered from
  10. Hello this question has been raised and answered many times but my issue still remains the same. I am not able to open the target on any board that we have in the lab. I tried a different programmer and that works but I can't see the target with the XUP Diligent one. That is the only one that will allow me to program the device others fail on that part. So here is what I see in the Hardware manager: and the screenshot of my device manager with the driver details:  Everything was installed as admin, please help me. Would it help if were to re-install Vivad
  11. It was a dumb question, but I'm leaving it up for other people to find the solution if they need it. Just zoom out in waveforms when you're capturing the transmission, then zoom in the look at the details afterwards, like you would with changing the scale on an oscilloscope.
  12. This is probably a stupid question, but I haven't been able to figure it out in the last week and I haven't found the answer on the forums. I have the maximum buffers set to 1k, and the device buffers set to setting 4, 16x16k for logic. I am trying to read I2C data, and the transmission is always cut off after a certain number of commands are sent. For example, I am sending a read command, then a write, then a read. Only the first read and the write appear in waveforms. I assume that this is because I do not have enough buffers. As shown in the screenshot, there are 49 buffers. I cannot i
  13. gamer333

    SPI slave in VHDL

    hi zygot hope you are doing well..I'm here because i had read one of your post related to lan8710a phy ethernet interfacing with a fpga,in my case its a spartan 6 lx75 fpga i have new to this field and also i had come across ethernet ip core in ISE 14.7 and xps with its own lwip and ethernet configuration .But the problem is i dont know how to start and where to start from. IF YOU DONT MIND CAN YOU SHARE YOUR CODE OR GUIDE ME ..HOW CAN I CONTACT YOU ..??? PARDON ME FOR THIS INTERRUPTION FOR THIS THREAD. THANK YOU
  14. Hello, I built the circuit shown here and was able to generate a tone out of the speaker (with only pitch control), but now I want to implement volume control, via an antenna (another soda can?). Would it be as simple as adding another VFO,FFO, Weighted Summer, and Envelope Detector and connecting it to a voltage controlled amplifier? (picture shown below) The linked article says it wouldn't be too hard to implement volume control. What did the author have in mind? Thank you!
  15. Last week
  16. I'm trying to get an Eclypse-Z7 board to boot Linux without any changes to the files in the git repository. Tools are all 2019.1. petalinux-build works... [email protected]:~/Eclypse-Z7/os$petalinux-build [INFO] building project [INFO] generating Kconfig for project [INFO] silentconfig project [INFO] sourcing bitbake [INFO] generating plnxtool conf [INFO] generating meta-plnx-generated layer [INFO] generating machine configuration [INFO] generating bbappends for project . This may take time ! [INFO] generating u-boot configuration files [INFO] generating kerne
  17. Hello: I am trying to get PYNQ onto the Arty Z7-20 by following the steps from this tutorial: I've burned the PYNQ Z1 2.6.0 ISO file (latest version) to a microSD card, but when I go to boot from the SD Card I only get the red LD13, TX/RX, and Ethernet lights to turn on. The six LED's at the bottom do not turn on as well as the done LED to signify the bitstream has been loaded. I switched the booting from to QSPI to shelve the microSD issues, but even after all the appropriate LED's turn on I'm not able to log
  18. pcdeni


    Hi, I have trouble instantiating a MIG and using the DDR on the NetFPGA SUME board. In the acceptance test, the init_calib_complete goes high, however I cannot recreat it in vivado 2020.1 The sources my configurations were based on: NetFPGA SUME live repository's multiple projects OSNT SUME live repository's extmem project Tapasco project. Additionally as the vc709 is similar, I have taken a look on the followings:
  19. There was timing failure when ILA is used. The issue got solved . There are no timing failures now.
  20. Hi @highspeed The supported sample formats are 8, 16, 32 See the following example WF SDK/samples/py.
  21. Hi @alexpeck You could switch with Script the Protocol between I2C and SPI but this may require a few milliseconds in which you could loose your bridge response. To overcome this you would have to add delay in your bridge between I2C reception and SPI transmission. Another way would be using the Protocol with Logic Analyzer, option in top-right edge of the Protocol. Use the events in Logic Analyzer to verify the I2C and/or SPI data. These are returned as array of text (by default hex) that can be parsed like this: var rgMosi = []
  22. Josef

    SPI slave in VHDL

    OK, thanks. Information provided by you is enough for me. And it's what I looked for. Best regards Josef
  23. zygot

    SPI slave in VHDL

    I don't want to lead, or mislead, you in your design approach. You should use either an external clock or MMCM/PLL derived clock for all synchronous logic in your FPGA designs. For your project you have a problem to solve if you want to use an SCLK input as a clock. Even if it is a derived clock it is not always running, and can have an inactive state of either '1' or '0'. As long as your system clocks are higher in frequency than SCLK it's possible to detect edges and phase relationships for the SPI signals. How you do this and what the requirements are for the system clocks and SCL
  24. Hi @brha0386 var rg = String(FileRead("~/Desktop/default.csv")).trim().split('\n') Patterns.Channels.DIO0.custom = rg
  25. Hi @mjacome Yes. I wanted to say in the above example 1- to W2 and 1+ to W1.
  26. Hi @DontP4nic Probably the device runs out of power during initial configuration, the consumption increases and the voltage drops. This could be due to bad USB cable contacts. Have you tried using the original USB cable the device came with or other microUSB cables you have by hand ? You could also try with powered USB hub or 5VDC auxiliary power supply.
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