`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: 威视锐科技有限公司---红色飓风 // Engineer: MR BAO // // Create Date: 15:39:25 01/10/2010 // Design Name: MCB // Module Name: V3_DDR2_TEST_TOP // Project Name: V3_DDR2_MCB_TEST // Target Devices: MT46H64M16 // Tool versions: 11.2 // Description: GOOD ISE THIS 11.2 // // Dependencies: // // Revision: 2010_2_2 // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module V3_DDR2_MT46H64M16 //module V3_DDR2_MT46H64M16 # // // ( // parameter C3_P0_MASK_SIZE = 16, // parameter C3_P0_DATA_PORT_SIZE = 128, // parameter C3_CLK_PERIOD = 20000, // parameter C3_RST_ACT_LOW = 1, // parameter C3_CALIB_SOFT_IP = "FALSE", // parameter C3_MEM_ADDR_ORDER = "ROW_BANK_COLUMN", // parameter C3_NUM_DQ_PINS = 16, // parameter C3_MEM_ADDR_WIDTH = 13, // parameter C3_MEM_BANKADDR_WIDTH = 3, // parameter C3_MC_CALIB_BYPASS = "NO" // ) // ( // inout [C3_NUM_DQ_PINS-1:0] mcb3_dram_dq, // output [C3_MEM_ADDR_WIDTH-1:0] mcb3_dram_a, // output [C3_MEM_BANKADDR_WIDTH-1:0] mcb3_dram_ba,+ inout [15:0] mcb3_dram_dq, output [12:0] mcb3_dram_a, output [2:0] mcb3_dram_ba, output mcb3_dram_ras_n, output mcb3_dram_cas_n, output mcb3_dram_we_n, output mcb3_dram_odt, output mcb3_dram_cke, output mcb3_dram_dm, inout mcb3_dram_udqs, inout mcb3_dram_udqs_n, output mcb3_dram_udm, input sys_clk_ibufg, input c3_sys_rst_n, //output c3_calib_done, inout rzq3, inout zio3, inout mcb3_dram_dqs, inout mcb3_dram_dqs_n, output mcb3_dram_ck, output mcb3_dram_ck_n, output led0, output led1, output led2, output led3, output led4, output led5, input load_data_i, input load_data_ii ); //////////////////INSIDE_USE_define//////////////////// wire c3_clk0; wire c3_rst0; wire c3_p0_arb_en; wire c3_p0_cmd_clk; reg c3_p0_cmd_en; reg [2:0] c3_p0_cmd_instr; reg [5:0] c3_p0_cmd_bl; reg [29:0] c3_p0_cmd_byte_addr; wire c3_p0_cmd_empty; wire c3_p0_cmd_full; ////////////////////////wirte//////////////////////////// wire c3_p0_wr_clk; reg c3_p0_wr_en; // wire [C3_P0_MASK_SIZE - 1:0] c3_p0_wr_mask; // reg [C3_P0_DATA_PORT_SIZE - 1:0] c3_p0_wr_data; wire [15:0] c3_p0_wr_mask; reg [127:0] c3_p0_wr_data; wire c3_p0_wr_full; wire c3_p0_wr_empty; wire [6:0] c3_p0_wr_count; wire c3_p0_wr_underrun; wire c3_p0_wr_error; ////////////////////////read///////////////////////////// wire c3_p0_rd_clk; reg c3_p0_rd_en; // wire [C3_P0_DATA_PORT_SIZE - 1:0] c3_p0_rd_data; wire [128:0] c3_p0_rd_data; wire c3_p0_rd_full; wire c3_p0_rd_empty; wire [6:0] c3_p0_rd_count; wire c3_p0_rd_overflow; wire c3_p0_rd_error; wire selfrefresh_mode; wire c3_calib_done; ////////////////////FPGA_CONTROL_LOGIC////////////////////// localparam IDEL = 4'b0000; localparam WRITE = 4'b0001; localparam CMD_WRITE_PRE = 4'b0010; localparam CMD_WRITE_EN = 4'b0011; localparam CMD_DELAY = 4'b0100; localparam CMD_READ_PRE = 4'b0101; localparam CMD_READ_EN = 4'b0110; localparam READ_WAITE = 4'b0111; localparam READ = 4'b1000; /////////////////////DATA_CONTROL_STATE////////////////////// localparam NO_1 = 2'b00; localparam NO_2 = 2'b01; localparam NO_3 = 2'b10; localparam NO_4 = 2'b11; /////////////////////LOGIC&&DISPLAY_REG////////////////////// reg error_data_display; reg [1:0] State_Find_Wrong; reg [3:0] state_ddr2; //reg [C3_P0_DATA_PORT_SIZE - 1:0] rd_data_display; //reg [C3_P0_DATA_PORT_SIZE - 1:0] rd_data_compare; reg [127:0] rd_data_display; reg [127:0] rd_data_compare; reg [5:0] wr_count; reg [5:0] rd_count; reg load_data_r_0; reg load_data_r_1; reg [5:0] delay_count; reg LED_BEGIN_DISPLAY; reg LED_FINISH_DISPLAY; reg [24:0] LED_CLK_COUNT; always @ (posedge c3_clk0 or posedge c3_rst0) if(c3_rst0)begin load_data_r_0 <= 1'b0; load_data_r_1 <= 1'b0; end else begin load_data_r_0 <= load_data_i; load_data_r_1 <= load_data_ii; end always@ (posedge c3_clk0 or posedge c3_rst0) if(c3_rst0) begin state_ddr2 <= IDEL; rd_data_compare <= 128'b0; State_Find_Wrong<=2'b0; rd_count <=6'b0; c3_p0_wr_data <=128'b0; wr_count <=6'b0; delay_count <= 6'b0; c3_p0_wr_en <= 1'b0; c3_p0_rd_en <= 1'b0; c3_p0_cmd_en <= 1'b0; c3_p0_cmd_instr <= 3'b000; c3_p0_cmd_bl <= 6'b000000; c3_p0_cmd_byte_addr <=30'b00000_00000_00000_00000_00000_00000; end else begin case(state_ddr2) IDEL: begin c3_p0_wr_data <=128'b0; rd_data_compare <= 128'b0; State_Find_Wrong<=2'b0; wr_count <=6'b0; rd_count <=6'b0; c3_p0_wr_en <= 1'b0; c3_p0_rd_en <= 1'b0; c3_p0_cmd_en <= 1'b0; c3_p0_cmd_instr <= 3'b000; c3_p0_cmd_bl <= 6'b000000; delay_count <= 6'b000000; if (c3_p0_cmd_byte_addr ==30'b00000_00000_00000_00000_00000_00000) begin c3_p0_cmd_byte_addr <=30'b00000_00000_00000_00000_00000_00000; if(!c3_p0_wr_full) state_ddr2 <= WRITE; else state_ddr2 <= IDEL; end else c3_p0_cmd_byte_addr<=c3_p0_cmd_byte_addr+1; end WRITE: if(c3_p0_cmd_byte_addr < 30'b00011_11111_11111_11111_10000_00000 )//00011_11111_11111_11111_10000_00000 begin if(wr_count<=6'b011111 ) begin c3_p0_wr_en <= 1'b1; c3_p0_wr_data <= c3_p0_wr_data+1; wr_count <= wr_count+1; state_ddr2 <= WRITE; end else begin c3_p0_wr_en <= 1'b0; wr_count <=6'b0; state_ddr2 <= CMD_WRITE_PRE; end end else begin c3_p0_cmd_byte_addr <=30'b00000_00000_00000_00000_00000_00000; rd_data_compare <= 128'b0; rd_count <=6'b0; state_ddr2 <= CMD_READ_PRE; end CMD_WRITE_PRE: begin if(c3_p0_cmd_empty) begin c3_p0_cmd_instr <= 3'b000; c3_p0_cmd_bl <= 6'b011111; //actel no.32*128 c3_p0_cmd_byte_addr <= c3_p0_cmd_byte_addr+10'b10000_00000;//data write into row_1/column_16/bank_1 state_ddr2 <= CMD_WRITE_EN; end else state_ddr2 <= CMD_WRITE_PRE; end CMD_WRITE_EN: begin delay_count <= 6'b000000; state_ddr2 <= CMD_DELAY; end CMD_DELAY: begin if(delay_count<=6'b111100) begin delay_count <= delay_count+1; state_ddr2 <= CMD_DELAY; if(delay_count < 6'b011111) c3_p0_cmd_en <= 1'b0; else if(delay_count==6'b011111) c3_p0_cmd_en <= 1'b1; else c3_p0_cmd_en <= 1'b0; end else begin if(c3_p0_wr_count==7'b0000000 ) state_ddr2 <= WRITE; else state_ddr2 <= CMD_DELAY; end end CMD_READ_PRE: if(c3_p0_cmd_byte_addr < 30'b00011_11111_11111_11111_10000_00000)//00011_11111_11111_11111_10000_00000 begin if(c3_p0_cmd_empty && c3_p0_wr_count==7'b0000000) begin c3_p0_cmd_instr <= 3'b001; c3_p0_cmd_bl <= 6'b011111; c3_p0_cmd_byte_addr <= c3_p0_cmd_byte_addr+10'b10000_00000;//data write into row_1/column_16/bank_1 delay_count <= 6'b000000; state_ddr2 <= CMD_READ_EN; end else begin state_ddr2 <= CMD_READ_PRE;end end else begin state_ddr2 <= IDEL; end CMD_READ_EN: begin if(delay_count<=6'b111100) begin delay_count <= delay_count+1; state_ddr2 <= CMD_READ_EN; if(delay_count < 6'b011111) c3_p0_cmd_en <= 1'b0; else if(delay_count==6'b011111) c3_p0_cmd_en <= 1'b1; else c3_p0_cmd_en <= 1'b0; end else begin delay_count <= 6'b000000; state_ddr2 <= READ_WAITE; end end READ_WAITE: begin if(!c3_p0_rd_empty && c3_p0_rd_count>=7'b0100000) begin state_ddr2 <= READ; end else state_ddr2 <= READ_WAITE; end READ: begin if(!c3_p0_rd_empty) begin c3_p0_rd_en <= 1'b1; rd_data_display <= c3_p0_rd_data; state_ddr2 <= READ; if( rd_count<=6'b100000 )//one bit delay begin case(State_Find_Wrong) NO_1: begin rd_data_compare <= rd_data_compare+1; rd_count <= rd_count+1; State_Find_Wrong <= NO_2; end NO_2: begin rd_data_compare <= rd_data_compare; rd_count <= rd_count+1; State_Find_Wrong <= NO_3; end NO_3: begin rd_data_compare <= rd_data_compare+1; rd_count <= rd_count+1; State_Find_Wrong <= NO_4; end NO_4: begin rd_data_compare <= rd_data_compare+1; rd_count <= rd_count+1; State_Find_Wrong <= NO_4; end default:State_Find_Wrong <= NO_1; endcase end else begin rd_count <=6'b0; rd_data_compare <= rd_data_compare; end end else begin state_ddr2 <= CMD_READ_PRE; rd_count <=6'b0; State_Find_Wrong <= NO_1; c3_p0_rd_en <= 1'b0; end end default: begin state_ddr2 <= IDEL; end endcase end ////////////////////ERROR_DATA_FIND///////////////// always@ (posedge c3_clk0 or posedge c3_rst0) if(c3_rst0) begin error_data_display <= 1'b0; end else begin if(c3_p0_rd_en)//!c3_p0_rd_empty begin if(rd_data_compare != rd_data_display) error_data_display <= 1'b1; else error_data_display <= 1'b0; end else begin error_data_display <= error_data_display;end end ////////////////////ERROR_DATA_FIND///////////////// always@ (posedge c3_clk0 or posedge c3_rst0) if(c3_rst0) begin LED_BEGIN_DISPLAY <= 1'b0; LED_FINISH_DISPLAY <=1'b0; end else begin LED_CLK_COUNT <= LED_CLK_COUNT +1; if (c3_p0_cmd_byte_addr == 30'b00000_00000_00000_00000_10000_00000)//!c3_p0_rd_empty begin LED_BEGIN_DISPLAY <= ~LED_BEGIN_DISPLAY ; end else if(c3_p0_cmd_byte_addr == 30'b00011_11111_11111_11111_00000_00000) begin LED_FINISH_DISPLAY <=~LED_FINISH_DISPLAY; end else begin LED_BEGIN_DISPLAY <= LED_BEGIN_DISPLAY; LED_FINISH_DISPLAY <= LED_FINISH_DISPLAY; end end //////////////////////////display/////////////////////// assign c3_p0_wr_mask = 16'b0000_0000_0000_0000; assign led0 = LED_BEGIN_DISPLAY; //c3_p0_wr_error assign led1 = LED_FINISH_DISPLAY; //c3_p0_rd_error assign led2 = error_data_display; //c3_p0_wr_underrun assign led3 = c3_calib_done; //c3_p0_rd_overflo assign led4 = !selfrefresh_mode; //!selfrefresh_mode assign led5 = LED_CLK_COUNT[24]; //100M_have_display ////////////////////CHIPSCOPE_WATCH//////////////////// wire [35:0] CONTROL0; ddr2_find_error ddr2_find_error_icon ( .CONTROL0(CONTROL0) // INOUT BUS [35:0] ); ddr2_find_error_ila ddr2_find_error_ila ( .CONTROL(CONTROL0), // INOUT BUS [35:0] // .CLK (c3_calib_clk), // IN c3_clk0 .CLK (c3_clk0), .TRIG0({c3_p0_wr_data,error_data_display,c3_clk0}), // IN BUS [129:0] .TRIG1({rd_data_display,c3_p0_rd_en,c3_clk0}), //c3_p0_rd_data IN BUS [129:0] c3_p0_rd_data .TRIG2({state_ddr2,c3_p0_cmd_empty,c3_p0_rd_empty,wr_count}), // IN BUS [11:0] error_display .TRIG3({c3_p0_cmd_en,c3_p0_cmd_instr,c3_p0_cmd_bl,c3_p0_cmd_byte_addr}), // IN BUS [39:0] .TRIG4({c3_p0_wr_count}), // IN BUS [6:0]//c3_p0_rd_error,c3_p0_wr_underrun,c3_p0_wr_error .TRIG5({c3_p0_rd_count}), // IN BUS [6:0] .TRIG6({rd_data_compare,c3_p0_wr_en,rd_count}) // IN BUS [134:0] ); ddr2_atlys # ( .C3_P0_MASK_SIZE(16), .C3_P0_DATA_PORT_SIZE(128), .DEBUG_EN(0), .C3_MEMCLK_PERIOD(2500), .C3_CALIB_SOFT_IP("TRUE"), .C3_SIMULATION("FALSE"), .C3_RST_ACT_LOW(0), .C3_INPUT_CLK_TYPE("SINGLE_ENDED"), .C3_MEM_ADDR_ORDER("ROW_BANK_COLUMN"), .C3_NUM_DQ_PINS(16), .C3_MEM_ADDR_WIDTH(13), .C3_MEM_BANKADDR_WIDTH(3) ) u_ddr2_atlys ( .c3_sys_clk (sys_clk_ibufg), .c3_sys_rst_i (c3_sys_rst_n), .mcb3_dram_dq (mcb3_dram_dq), .mcb3_dram_a (mcb3_dram_a), .mcb3_dram_ba (mcb3_dram_ba), .mcb3_dram_ras_n (mcb3_dram_ras_n), .mcb3_dram_cas_n (mcb3_dram_cas_n), .mcb3_dram_we_n (mcb3_dram_we_n), .mcb3_dram_odt (mcb3_dram_odt), .mcb3_dram_cke (mcb3_dram_cke), .mcb3_dram_ck (mcb3_dram_ck), .mcb3_dram_ck_n (mcb3_dram_ck_n), .mcb3_dram_dqs (mcb3_dram_dqs), .mcb3_dram_dqs_n (mcb3_dram_dqs_n), .mcb3_dram_udqs (mcb3_dram_udqs), // for X16 parts .mcb3_dram_udqs_n (mcb3_dram_udqs_n), // for X16 parts .mcb3_dram_udm (mcb3_dram_udm), // for X16 parts .mcb3_dram_dm (mcb3_dram_dm), .c3_clk0 (c3_clk0), .c3_rst0 (c3_rst0), .c3_calib_done (c3_calib_done), .mcb3_rzq (rzq3), .mcb3_zio (zio3), .c3_p0_cmd_clk (c3_clk0), .c3_p0_cmd_en (c3_p0_cmd_en), .c3_p0_cmd_instr (c3_p0_cmd_instr), .c3_p0_cmd_bl (c3_p0_cmd_bl), .c3_p0_cmd_byte_addr (c3_p0_cmd_byte_addr), .c3_p0_cmd_empty (c3_p0_cmd_empty), .c3_p0_cmd_full (c3_p0_cmd_full), .c3_p0_wr_clk (c3_clk0), .c3_p0_wr_en (c3_p0_wr_en), .c3_p0_wr_mask (c3_p0_wr_mask), .c3_p0_wr_data (c3_p0_wr_data), .c3_p0_wr_full (c3_p0_wr_full), .c3_p0_wr_empty (c3_p0_wr_empty), .c3_p0_wr_count (c3_p0_wr_count), .c3_p0_wr_underrun (c3_p0_wr_underrun), .c3_p0_wr_error (c3_p0_wr_error), .c3_p0_rd_clk (c3_clk0), .c3_p0_rd_en (c3_p0_rd_en), .c3_p0_rd_data (c3_p0_rd_data), .c3_p0_rd_full (c3_p0_rd_full), .c3_p0_rd_empty (c3_p0_rd_empty), .c3_p0_rd_count (c3_p0_rd_count), .c3_p0_rd_overflow (c3_p0_rd_overflow), .c3_p0_rd_error (c3_p0_rd_error) ); endmodule