`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 02/23/2019 09:51:31 AM
// Design Name: 
// Module Name: test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module test(
       input clk,
       input [31:0] din,
       output reg [31:0] addr,
       output reg rstb,
       output reg en,
       output reg led0,
       output reg led1,
       output reg led2,
       output reg led3,
       output reg [3:0] web
       
   );
   reg [3:0] val;
   initial
   begin
       val <= 0;
   end
   always@(posedge clk)
   begin
   if(val == 4'd0)
   begin
       rstb <= 0;
       web <= 4'b0000;
       val = 1;
       en <= 1;
       addr <= 32'h40000000;
       led0 <= din[0];

   end
    else if(val == 4'd1)
    begin
         rstb <= 0;
         web <= 4'b0000;
         val = 2;   
        en <= 1;
        addr <= 32'h40000001;
        led1 <= din[0];
    end
        else if(val == 4'd2)
        begin
             rstb <= 0;
             web <= 4'b0000;
             val = 3;   
            en <= 1;
            addr <= 32'h40000002;
        led2 <= din[0];
        end
        else if(val == 4'd3)
            begin
                 rstb <= 0;
                 web <= 4'b0000;
                 val = 4;   
                en <= 1;
                addr <= 32'h40000003;
               led3 <= din[0];
            end
end

   
   
endmodule