`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 12/10/2018 10:38:15 AM // Design Name: // Module Name: letter_key // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module letter_key(input clk,input wire [9:0] pixel_x,pixel_y, input blank, output reg[3:0] r,g,b, output wire text_on_a,text_on_b); wire blank; wire clk_25; wire [9:0] pixel_x,pixel_y; wire HS,VS; wire [10:0]rom_addr; reg [6:0] char_addr,char_addr_a,char_addr_b; reg [3:0] row_addr; wire[3:0] row_addr_a,row_addr_b; reg [2:0]bit_addr; wire [2:0] bit_addr_a,bit_addr_b; wire [7:0] font_word; wire font_bit; wire [1:0] letter_on; wire video_on; reg [3:0] r,g,b; font_rom n1(.clk(clk),.addr(rom_addr),.data(font_word)); // for A assign letter_on[0] = (pixel_y [9: 5] == 4) && (pixel_x [9: 4] < 1) ; assign row_addr_a = pixel_y [4: 1] ; assign bit_addr_a = pixel_x [3:1] ; always@* begin case (pixel_x [4]) 1'b1: char_addr_a = 7'h41; //A endcase end // for B assign letter_on[1] = (pixel_y [9: 5] == 3 ) && (pixel_x [9: 4] < 1) ; assign row_addr_b = pixel_y [4: 1] ; assign bit_addr_b = pixel_x [3:1] ; always@* begin case (pixel_x [4]) 1'b1: char_addr_b = 7'h42; //B endcase end always@* begin case(letter_on) 1'b0: begin char_addr = char_addr_a; row_addr = row_addr_a; bit_addr = bit_addr_a; if(font_bit) begin r<=4'b0000; g<=4'b1111; b<=4'b0000; end else begin r<=4'b0000; g<=4'b0000; b<=4'b0000; end end 1'b1: begin char_addr = char_addr_b; row_addr = row_addr_b; bit_addr = bit_addr_b; if(font_bit) begin r<=4'b0000; g<=4'b1111; b<=4'b0000; end else begin r<=4'b0000; g<=4'b0000; b<=4'b0000; end end endcase end assign rom_addr={char_addr,row_addr}; assign font_bit=font_word[~bit_addr]; assign text_on_a=letter_on[0]; assign text_on_b=letter_on[1]; endmodule