-------------------------------START------------------------------ -- Company: UNC Charlotte -- Student: Masoud Arablu -- -- Create Date: 10/17/2018 08:06:14 AM -- Design Name: Discrete Fourier Transform -- Module Name: Top - Behavior -- Project Name: Digital Methods for Phase Extraction in Interferometry -- Target Devices: NEXYS 4 DDR -- Description: -- -- Dependencies: -- -- Revision: -- Revision 7 - Algorithm was expanded to two harmonics of 312.5 kHz. -- Additional Comments: This algorithm reads 12 bit digital data in -- parallel mode at 10 MHz speed and applies digital DFT into it. -- The result of the DFT is shown in Ave_R1 and Ave_R2 as the amplitude -- of Harmonics 1 and 2, respectively. ----------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -----------------------------------------------------------------------------------------end1 entity Top is Port ( CLK : in std_logic; CLK_Reset : in std_logic; D : in std_logic_vector(11 downto 0); Photo_CLK : out std_logic := '0'; dp : out std_logic; seg : out std_logic_vector(6 downto 0); an : out std_logic_vector(7 downto 0); LED : out std_logic_vector(15 downto 0); D_Out : out std_logic_vector(15 downto 0) := ( others=> '0'); Dec_CLK : out std_logic := '0' ); end Top; -----------------------------------------------------------------------------------------end2 architecture Behavior of Top is signal count : integer range 0 to 10000; signal count2 : integer range 0 to 10000; signal dig0 : std_logic_vector(3 downto 0); signal dig1 : std_logic_vector(3 downto 0); signal dig2 : std_logic_vector(3 downto 0); signal dig3 : std_logic_vector(3 downto 0); signal dig4 : std_logic_vector(3 downto 0); signal dig5 : std_logic_vector(3 downto 0); signal dig6 : std_logic_vector(3 downto 0); signal Bin_Data : std_logic_vector(15 downto 0); -------------------------------------------------------- signal MAIN_CLK : std_logic; signal CLK_100MHz : std_logic; signal reset_bcd : std_logic; signal counter1 : integer range 0 to 511 := 0; signal counter2 : integer range 0 to 511 := 0; signal counter3 : integer range 0 to 511 := 0; signal probe_0 : std_logic_vector(11 downto 0):= ( others=> '0'); signal probe_1 : std_logic_vector(0 downto 0):= ( others=> '0'); signal probe_2 : std_logic_vector(0 downto 0):= ( others=> '0'); signal probe_3 : std_logic_vector(0 downto 0):= ( others=> '0'); signal probe_4 : std_logic_vector(15 downto 0):= ( others=> '0'); signal MMCM_Locked : std_logic; signal D_In_Ready : std_logic := '0'; signal D_Out_Ready : std_logic := '0'; signal data : std_logic_vector(11 downto 0) := ( others=> '0'); -------------------------------------------------------- type mem32_12 is array (31 downto 0) of std_logic_vector (11 downto 0); signal data_1 : mem32_12 := (others => ( others=> '0')); -------------------------------------------------------- type mem32_16 is array (31 downto 0) of std_logic_vector (15 downto 0); signal C1 : mem32_16 := ("0111111111111111","0111110110001010","0111011001000010","0110101001101110", "0101101010000010","0100011100011101","0011000011111100","0001100011111001", "0000000000000000","1110011100000111","1100111100000100","1011100011100011", "1010010101111110","1001010110010010","1000100110111110","1000001001110110", "1000000000000000","1000001001110110","1000100110111110","1001010110010010", "1010010101111110","1011100011100011","1100111100000100","1110011100000111", "0000000000000000","0001100011111001","0011000011111100","0100011100011101", "0101101010000010","0110101001101110","0111011001000010","0111110110001010"); signal S1 : mem32_16 := ("0000000000000000","0001100011111001","0011000011111100","0100011100011101", "0101101010000010","0110101001101110","0111011001000010","0111110110001010", "0111111111111111","0111110110001010","0111011001000010","0110101001101110", "0101101010000010","0100011100011101","0011000011111100","0001100011111001", "0000000000000000","1110011100000111","1100111100000100","1011100011100011", "1010010101111110","1001010110010010","1000100110111110","1000001001110110", "1000000000000000","1000001001110110","1000100110111110","1001010110010010", "1010010101111110","1011100011100011","1100111100000100","1110011100000111"); signal C2 : mem32_16 := ("0111111111111111","0111011001000010","0101101010000010","0011000011111100", "0000000000000000","1100111100000100","1010010101111110","1000100110111110", "1000000000000000","1000100110111110","1010010101111110","1100111100000100", "0000000000000000","0011000011111100","0101101010000010","0111011001000010", "0111111111111111","0111011001000010","0101101010000010","0011000011111100", "0000000000000000","1100111100000100","1010010101111110","1000100110111110", "1000000000000000","1000100110111110","1010010101111110","1100111100000100", "0000000000000000","0011000011111100","0101101010000010","0111011001000010"); signal S2 : mem32_16 := ("0000000000000000","0011000011111100","0101101010000010","0111011001000010", "0111111111111111","0111011001000010","0101101010000010","0011000011111100", "0000000000000000","1100111100000100","1010010101111110","1000100110111110", "1000000000000000","1000100110111110","1010010101111110","1100111100000100", "0000000000000000","0011000011111100","0101101010000010","0111011001000010", "0111111111111111","0111011001000010","0101101010000010","0011000011111100", "0000000000000000","1100111100000100","1010010101111110","1000100110111110", "1000000000000000","1000100110111110","1010010101111110","1100111100000100"); -------------------------------------------------------- type mem32_28 is array (31 downto 0) of std_logic_vector (27 downto 0); signal X1_1 : mem32_28 := (others => ( others=> '0')); signal Y1_1 : mem32_28 := (others => ( others=> '0')); signal X2_1 : mem32_28 := (others => ( others=> '0')); signal Y2_1 : mem32_28 := (others => ( others=> '0')); -------------------------------------------------------- type mem16_29 is array (15 downto 0) of std_logic_vector (28 downto 0); signal X1_2 : mem16_29 := (others => ( others=> '0')); signal Y1_2 : mem16_29 := (others => ( others=> '0')); signal X2_2 : mem16_29 := (others => ( others=> '0')); signal Y2_2 : mem16_29 := (others => ( others=> '0')); -------------------------------------------------------- type mem8_30 is array (7 downto 0) of std_logic_vector (29 downto 0); signal X1_3 : mem8_30 := (others => ( others=> '0')); signal Y1_3 : mem8_30 := (others => ( others=> '0')); signal X2_3 : mem8_30 := (others => ( others=> '0')); signal Y2_3 : mem8_30 := (others => ( others=> '0')); -------------------------------------------------------- type mem4_31 is array (3 downto 0) of std_logic_vector (30 downto 0); signal X1_4 : mem4_31 := (others => ( others=> '0')); signal Y1_4 : mem4_31 := (others => ( others=> '0')); signal X2_4 : mem4_31 := (others => ( others=> '0')); signal Y2_4 : mem4_31 := (others => ( others=> '0')); -------------------------------------------------------- type mem2_32 is array (1 downto 0) of std_logic_vector (31 downto 0); signal X1_5 : mem2_32 := (others => ( others=> '0')); signal Y1_5 : mem2_32 := (others => ( others=> '0')); signal X2_5 : mem2_32 := (others => ( others=> '0')); signal Y2_5 : mem2_32 := (others => ( others=> '0')); -------------------------------------------------------- type mem2_33 is array (1 downto 0) of std_logic_vector (32 downto 0); signal X1_6 : mem2_33 := (others => ( others=> '0')); signal Y1_6 : mem2_33 := (others => ( others=> '0')); signal X2_6 : mem2_33 := (others => ( others=> '0')); signal Y2_6 : mem2_33 := (others => ( others=> '0')); -------------------------------------------------------- signal X1 : std_logic_vector(15 downto 0) := ( others=> '0'); signal Y1 : std_logic_vector(15 downto 0) := ( others=> '0'); signal X2 : std_logic_vector(15 downto 0) := ( others=> '0'); signal Y2 : std_logic_vector(15 downto 0) := ( others=> '0'); -------------------------------------------------------- type mem32_33 is array (31 downto 0) of std_logic_vector (32 downto 0); signal Ave1_X1 : mem32_33 := (others => ( others=> '0')); signal Ave1_Y1 : mem32_33 := (others => ( others=> '0')); signal Ave1_X2 : mem32_33 := (others => ( others=> '0')); signal Ave1_Y2 : mem32_33 := (others => ( others=> '0')); -------------------------------------------------------- type mem16_34 is array (15 downto 0) of std_logic_vector (33 downto 0); signal Ave2_X1 : mem16_34 := (others => ( others=> '0')); signal Ave2_Y1 : mem16_34 := (others => ( others=> '0')); signal Ave2_X2 : mem16_34 := (others => ( others=> '0')); signal Ave2_Y2 : mem16_34 := (others => ( others=> '0')); -------------------------------------------------------- type mem8_35 is array (7 downto 0) of std_logic_vector (34 downto 0); signal Ave3_X1 : mem8_35 := (others => ( others=> '0')); signal Ave3_Y1 : mem8_35 := (others => ( others=> '0')); signal Ave3_X2 : mem8_35 := (others => ( others=> '0')); signal Ave3_Y2 : mem8_35 := (others => ( others=> '0')); -------------------------------------------------------- type mem4_36 is array (3 downto 0) of std_logic_vector (35 downto 0); signal Ave4_X1 : mem4_36 := (others => ( others=> '0')); signal Ave4_Y1 : mem4_36 := (others => ( others=> '0')); signal Ave4_X2 : mem4_36 := (others => ( others=> '0')); signal Ave4_Y2 : mem4_36 := (others => ( others=> '0')); -------------------------------------------------------- type mem2_37 is array (1 downto 0) of std_logic_vector (36 downto 0); signal Ave5_X1 : mem2_37 := (others => ( others=> '0')); signal Ave5_Y1 : mem2_37 := (others => ( others=> '0')); signal Ave5_X2 : mem2_37 := (others => ( others=> '0')); signal Ave5_Y2 : mem2_37 := (others => ( others=> '0')); -------------------------------------------------------- type mem2_38 is array (1 downto 0) of std_logic_vector (37 downto 0); signal Ave6_X1 : mem2_38 := (others => ( others=> '0')); signal Ave6_Y1 : mem2_38 := (others => ( others=> '0')); signal Ave6_X2 : mem2_38 := (others => ( others=> '0')); signal Ave6_Y2 : mem2_38 := (others => ( others=> '0')); -------------------------------------------------------- signal Ave_X1 : std_logic_vector(15 downto 0) := ( others=> '0'); signal Ave_Y1 : std_logic_vector(15 downto 0) := ( others=> '0'); signal Ave_X11 : std_logic_vector(15 downto 0) := ( others=> '0'); signal Ave_Y11 : std_logic_vector(15 downto 0) := ( others=> '0'); signal Ave_XY1 : std_logic_vector(31 downto 0) := ( others=> '0'); signal Ave_X2 : std_logic_vector(15 downto 0) := ( others=> '0'); signal Ave_Y2 : std_logic_vector(15 downto 0) := ( others=> '0'); signal Ave_XY2 : std_logic_vector(31 downto 0) := ( others=> '0'); signal Ave_PHI1 : std_logic_vector(15 downto 0) := ( others=> '0'); signal Ave_PHI2 : std_logic_vector(15 downto 0) := ( others=> '0'); signal sqr_Ave_X1 : std_logic_vector(31 downto 0) := ( others=> '0'); signal sqr_Ave_Y1 : std_logic_vector(31 downto 0) := ( others=> '0'); signal sqr_Ave_X2 : std_logic_vector(31 downto 0) := ( others=> '0'); signal sqr_Ave_Y2 : std_logic_vector(31 downto 0) := ( others=> '0'); signal sqr_Ave_R1 : std_logic_vector(32 downto 0) := ( others=> '0'); signal sqr_Ave_R2 : std_logic_vector(32 downto 0) := ( others=> '0'); signal sqr_Ave_R1_2 : std_logic_vector(39 downto 0) := ( others=> '0'); signal sqr_Ave_R2_2 : std_logic_vector(39 downto 0) := ( others=> '0'); signal Ave_R1 : std_logic_vector(23 downto 0) := ( others=> '0'); signal Ave_R2 : std_logic_vector(23 downto 0) := ( others=> '0'); -------------------------------------------------------------------------------------end3-1 component mult_gen_0 port ( A : in std_logic_vector(11 downto 0); B : in std_logic_vector(15 downto 0); CLK : in std_logic; P : out std_logic_vector(27 downto 0) ); end component mult_gen_0; -------------------------------------------------------------------------------------end3-2 component mult_gen_1 port ( A : in std_logic_vector(15 downto 0); B : in std_logic_vector(15 downto 0); CLK : in std_logic; P : out std_logic_vector(31 downto 0) ); end component mult_gen_1; -------------------------------------------------------------------------------------end3-3 component c_addsub_0 port ( A : in std_logic_vector(27 downto 0); B : in std_logic_vector(27 downto 0); CLK : in std_logic; S : out std_logic_vector(28 downto 0) ); end component c_addsub_0; -------------------------------------------------------------------------------------end3-4 component c_addsub_1 port ( A : in std_logic_vector(28 downto 0); B : in std_logic_vector(28 downto 0); CLK : in std_logic; S : out std_logic_vector(29 downto 0) ); end component c_addsub_1; -------------------------------------------------------------------------------------end3-5 component c_addsub_2 port ( A : in std_logic_vector(29 downto 0); B : in std_logic_vector(29 downto 0); CLK : in std_logic; S : out std_logic_vector(30 downto 0) ); end component c_addsub_2; -------------------------------------------------------------------------------------end3-6 component c_addsub_3 port ( A : in std_logic_vector(30 downto 0); B : in std_logic_vector(30 downto 0); CLK : in std_logic; S : out std_logic_vector(31 downto 0) ); end component c_addsub_3; -------------------------------------------------------------------------------------end3-7 component c_addsub_4 port ( A : in std_logic_vector(31 downto 0); B : in std_logic_vector(31 downto 0); CLK : in std_logic; S : out std_logic_vector(32 downto 0) ); end component c_addsub_4; -------------------------------------------------------------------------------------end3-8 component c_addsub_5 port ( A : in std_logic_vector(32 downto 0); B : in std_logic_vector(32 downto 0); CLK : in std_logic; S : out std_logic_vector(33 downto 0) ); end component c_addsub_5; -------------------------------------------------------------------------------------end3-9 component c_addsub_6 port ( A : in std_logic_vector(33 downto 0); B : in std_logic_vector(33 downto 0); CLK : in std_logic; S : out std_logic_vector(34 downto 0) ); end component c_addsub_6; -------------------------------------------------------------------------------------end3-10 component c_addsub_7 port ( A : in std_logic_vector(34 downto 0); B : in std_logic_vector(34 downto 0); CLK : in std_logic; S : out std_logic_vector(35 downto 0) ); end component c_addsub_7; -------------------------------------------------------------------------------------end3-11 component c_addsub_8 port ( A : in std_logic_vector(35 downto 0); B : in std_logic_vector(35 downto 0); CLK : in std_logic; S : out std_logic_vector(36 downto 0) ); end component c_addsub_8; -------------------------------------------------------------------------------------end3-12 component c_addsub_9 port ( A : in std_logic_vector(36 downto 0); B : in std_logic_vector(36 downto 0); CLK : in std_logic; S : out std_logic_vector(37 downto 0) ); end component c_addsub_9; -------------------------------------------------------------------------------------end3-12 component c_addsub_10 port ( A : IN STD_LOGIC_VECTOR(15 DOWNTO 0); CLK : IN STD_LOGIC; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); end component c_addsub_10; -------------------------------------------------------------------------------------end3-13 component ila_0 port ( clk : IN STD_LOGIC; probe0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ); end component ila_0; -------------------------------------------------------------------------------------end3-14 component cordic_0 port ( aclk : in std_logic; s_axis_cartesian_tvalid : in std_logic; s_axis_cartesian_tdata : IN std_logic_vector(39 DOWNTO 0); m_axis_dout_tvalid : out std_logic; m_axis_dout_tdata : out std_logic_vector(23 DOWNTO 0) ); end component; -------------------------------------------------------------------------------------end3-16 component cordic_1 port ( aclk : in std_logic; s_axis_cartesian_tvalid : in std_logic; s_axis_cartesian_tdata : in std_logic_vector(31 DOWNTO 0); m_axis_dout_tvalid : out std_logic; m_axis_dout_tdata : out std_logic_vector(15 DOWNTO 0) ); end component; -------------------------------------------------------------------------------------end3-17 component clk_wiz_0 port ( clk_out1 : out std_logic; clk_out2 : out std_logic; clk_out3 : out std_logic; reset : in std_logic; locked : out std_logic; clk_in1 : in std_logic ); end component; -------------------------------------------------------------------------------------end3-18 component DigitToSeg port ( in1 : in std_logic_vector(3 downto 0); in2 : in std_logic_vector(3 downto 0); in3 : in std_logic_vector(3 downto 0); in4 : in std_logic_vector(3 downto 0); in5 : in std_logic_vector(3 downto 0); in6 : in std_logic_vector(3 downto 0); in7 : in std_logic_vector(3 downto 0); in8 : in std_logic_vector(3 downto 0); mclk : in std_logic; an : out std_logic_vector(7 downto 0); dp : out std_logic; seg : out std_logic_vector(6 downto 0) ); end component DigitToSeg; -------------------------------------------------------------------------------------end3-19 component bin2bcd port( mclk, reset : in std_logic; binary_in : in std_logic_vector(15 downto 0); bcd0, bcd1, bcd2, bcd3, bcd4, bcd5, bcd6 : out std_logic_vector(3 downto 0) ); end component bin2bcd; -------------------------------------------------------------------------------------end3-20 begin multiplier0: for i in 0 to 31 generate -- generates 28 bit data gives_X1_1 : component mult_gen_0 port map ( CLK => MAIN_CLK, A => data_1(i), B => C1(i), P => X1_1(i) ); ---------------------------- gives_Y1_1 : component mult_gen_0 port map ( CLK => MAIN_CLK, A => data_1(i), B => S1(i), P => Y1_1(i) ); ---------------------------- gives_X2_1 : component mult_gen_0 port map ( CLK => MAIN_CLK, A => data_1(i), B => C2(i), P => X2_1(i) ); ---------------------------- gives_Y2_1 : component mult_gen_0 port map ( CLK => MAIN_CLK, A => data_1(i), B => S2(i), P => Y2_1(i) ); end generate multiplier0; -------------------------------------------------------------------------------------end3-21 adder0: for i in 0 to 15 generate -- generates 29 bit data gives_X1_2 : component c_addsub_0 port map ( CLK => MAIN_CLK, A => X1_1(i), B => X1_1(i+16), S => X1_2(i) ); ---------------------------- gives_Y1_2 : component c_addsub_0 port map ( CLK => MAIN_CLK, A => Y1_1(i), B => Y1_1(i+16), S => Y1_2(i) ); ---------------------------- gives_X2_2 : component c_addsub_0 port map ( CLK => MAIN_CLK, A => X2_1(i), B => X2_1(i+16), S => X2_2(i) ); ---------------------------- gives_Y2_2 : component c_addsub_0 port map ( CLK => MAIN_CLK, A => Y2_1(i), B => Y2_1(i+16), S => Y2_2(i) ); end generate adder0; -------------------------------------------------------------------------------------end3-22 adder1: for i in 0 to 7 generate -- generates 30 bit data gives_X1_3 : component c_addsub_1 port map ( CLK => MAIN_CLK, A => X1_2(i), B => X1_2(i+8), S => X1_3(i) ); ---------------------------- gives_Y1_3 : component c_addsub_1 port map ( CLK => MAIN_CLK, A => Y1_2(i), B => Y1_2(i+8), S => Y1_3(i) ); ---------------------------- gives_X2_3 : component c_addsub_1 port map ( CLK => MAIN_CLK, A => X2_2(i), B => X2_2(i+8), S => X2_3(i) ); ---------------------------- gives_Y2_3 : component c_addsub_1 port map ( CLK => MAIN_CLK, A => Y2_2(i), B => Y2_2(i+8), S => Y2_3(i) ); end generate adder1; -------------------------------------------------------------------------------------end3-23 adder2: for i in 0 to 3 generate -- generates 31 bit data gives_X1_4 : component c_addsub_2 port map ( CLK => MAIN_CLK, A => X1_3(i), B => X1_3(i+4), S => X1_4(i) ); ---------------------------- gives_Y1_4 : component c_addsub_2 port map ( CLK => MAIN_CLK, A => Y1_3(i), B => Y1_3(i+4), S => Y1_4(i) ); ---------------------------- gives_X2_4 : component c_addsub_2 port map ( CLK => MAIN_CLK, A => X2_3(i), B => X2_3(i+4), S => X2_4(i) ); ---------------------------- gives_Y2_4 : component c_addsub_2 port map ( CLK => MAIN_CLK, A => Y2_3(i), B => Y2_3(i+4), S => Y2_4(i) ); end generate adder2; -------------------------------------------------------------------------------------end3-24 adder3: for i in 0 to 1 generate -- generates 32 bit data gives_X1_5 : component c_addsub_3 port map ( CLK => MAIN_CLK, A => X1_4(i), B => X1_4(i+2), S => X1_5(i) ); ---------------------------- gives_Y1_5 : component c_addsub_3 port map ( CLK => MAIN_CLK, A => Y1_4(i), B => Y1_4(i+2), S => Y1_5(i) ); ---------------------------- gives_X2_5 : component c_addsub_3 port map ( CLK => MAIN_CLK, A => X2_4(i), B => X2_4(i+2), S => X2_5(i) ); ---------------------------- gives_Y2_5 : component c_addsub_3 port map ( CLK => MAIN_CLK, A => Y2_4(i), B => Y2_4(i+2), S => Y2_5(i) ); end generate adder3; -------------------------------------------------------------------------------------end3-25 gives_X1_6_0 : component c_addsub_4 -- generates 33 bit data port map ( CLK => MAIN_CLK, A => X1_5(0), B => X1_5(1), S => X1_6(0) ); ---------------------------- gives_Y1_6_0 : component c_addsub_4 -- generates 33 bit data port map ( CLK => MAIN_CLK, A => Y1_5(0), B => Y1_5(1), S => Y1_6(0) ); ---------------------------- X1_6(1) <= std_logic_vector(shift_right(signed(X1_6(0)), 12)); -- X1_6(0) should be divided to (16*2^15) 2^19 and saved into X1(16bit). X1 <= X1_6(0)(32) & X1_6(1)(14 downto 0); Y1_6(1) <= std_logic_vector(shift_right(signed(Y1_6(0)), 12)); -- Y1_6(0) should be divided to (16*2^15) 2^19 and saved into Y1(16bit). Y1 <= Y1_6(0)(32) & Y1_6(1)(14 downto 0); ---------------------------- gives_X2_6_0 : component c_addsub_4 -- generates 33 bit data port map ( CLK => MAIN_CLK, A => X2_5(0), B => X2_5(1), S => X2_6(0) ); ---------------------------- gives_Y2_6_0 : component c_addsub_4 -- generates 33 bit data port map ( CLK => MAIN_CLK, A => Y2_5(0), B => Y2_5(1), S => Y2_6(0) ); ---------------------------- X2_6(1) <= std_logic_vector(shift_right(signed(X2_6(0)), 12)); -- X2_6(0) should be divided to (16*2^15) 2^19 and saved into X2(16bit). X2 <= X2_6(0)(32) & X2_6(1)(14 downto 0); Y2_6(1) <= std_logic_vector(shift_right(signed(Y2_6(0)), 12)); -- Y2_6(0) should be divided to (16*2^15) 2^19 and saved into Y2(16bit). Y2 <= Y2_6(0)(32) & Y2_6(1)(14 downto 0); -------------------------------------------------------------------------------------end3-26 ----------------------------- AVERAGE 32 VALUES And Report As Ave_Q values adder5: for i in 0 to 15 generate -- generates 34 bit data gives_Ave2_X1 : component c_addsub_5 port map ( CLK => MAIN_CLK, A => Ave1_X1(i), B => Ave1_X1(i+16), S => Ave2_X1(i) ); ---------------------------- gives_Ave2_Y1 : component c_addsub_5 port map ( CLK => MAIN_CLK, A => Ave1_Y1(i), B => Ave1_Y1(i+16), S => Ave2_Y1(i) ); ---------------------------- gives_Ave2_X2 : component c_addsub_5 port map ( CLK => MAIN_CLK, A => Ave1_X2(i), B => Ave1_X2(i+16), S => Ave2_X2(i) ); ---------------------------- gives_Ave2_Y2 : component c_addsub_5 port map ( CLK => MAIN_CLK, A => Ave1_Y2(i), B => Ave1_Y2(i+16), S => Ave2_Y2(i) ); end generate adder5; -------------------------------------------------------------------------------------end3-28 adder6: for i in 0 to 7 generate -- generates 35 bit data gives_Ave3_X1 : component c_addsub_6 port map ( CLK => MAIN_CLK, A => Ave2_X1(i), B => Ave2_X1(i+8), S => Ave3_X1(i) ); ---------------------------- gives_Ave3_Y1 : component c_addsub_6 port map ( CLK => MAIN_CLK, A => Ave2_Y1(i), B => Ave2_Y1(i+8), S => Ave3_Y1(i) ); ---------------------------- gives_Ave3_X2 : component c_addsub_6 port map ( CLK => MAIN_CLK, A => Ave2_X2(i), B => Ave2_X2(i+8), S => Ave3_X2(i) ); ---------------------------- gives_Ave3_Y2 : component c_addsub_6 port map ( CLK => MAIN_CLK, A => Ave2_Y2(i), B => Ave2_Y2(i+8), S => Ave3_Y2(i) ); end generate adder6; -------------------------------------------------------------------------------------end3-29 adder7: for i in 0 to 3 generate -- generates 36 bit data gives_Ave4_X1 : component c_addsub_7 port map ( CLK => MAIN_CLK, A => Ave3_X1(i), B => Ave3_X1(i+4), S => Ave4_X1(i) ); ---------------------------- gives_Ave4_Y1 : component c_addsub_7 port map ( CLK => MAIN_CLK, A => Ave3_Y1(i), B => Ave3_Y1(i+4), S => Ave4_Y1(i) ); ---------------------------- gives_Ave4_X2 : component c_addsub_7 port map ( CLK => MAIN_CLK, A => Ave3_X2(i), B => Ave3_X2(i+4), S => Ave4_X2(i) ); ---------------------------- gives_Ave4_Y2 : component c_addsub_7 port map ( CLK => MAIN_CLK, A => Ave3_Y2(i), B => Ave3_Y2(i+4), S => Ave4_Y2(i) ); end generate adder7; -------------------------------------------------------------------------------------end3-30 adder8: for i in 0 to 1 generate -- generates 37 bit data gives_Ave5_X1 : component c_addsub_8 port map ( CLK => MAIN_CLK, A => Ave4_X1(i), B => Ave4_X1(i+2), S => Ave5_X1(i) ); ---------------------------- gives_Ave5_Y1 : component c_addsub_8 port map ( CLK => MAIN_CLK, A => Ave4_Y1(i), B => Ave4_Y1(i+2), S => Ave5_Y1(i) ); ---------------------------- gives_Ave5_X2 : component c_addsub_8 port map ( CLK => MAIN_CLK, A => Ave4_X2(i), B => Ave4_X2(i+2), S => Ave5_X2(i) ); ---------------------------- gives_Ave5_Y2 : component c_addsub_8 port map ( CLK => MAIN_CLK, A => Ave4_Y2(i), B => Ave4_Y2(i+2), S => Ave5_Y2(i) ); end generate adder8; -------------------------------------------------------------------------------------end3-31 gives_Ave6_X1_0 : component c_addsub_9 -- generates 38 bit data port map ( CLK => MAIN_CLK, A => Ave5_X1(0), B => Ave5_X1(1), S => Ave6_X1(0) ); ---------------------------- gives_Ave6_Y1_0 : component c_addsub_9 -- generates 38 bit data port map ( CLK => MAIN_CLK, A => Ave5_Y1(0), B => Ave5_Y1(1), S => Ave6_Y1(0) ); ---------------------------- gives_Ave6_X2_0 : component c_addsub_9 -- generates 38 bit data port map ( CLK => MAIN_CLK, A => Ave5_X2(0), B => Ave5_X2(1), S => Ave6_X2(0) ); ---------------------------- gives_Ave6_Y2_0 : component c_addsub_9 -- generates 38 bit data port map ( CLK => MAIN_CLK, A => Ave5_Y2(0), B => Ave5_Y2(1), S => Ave6_Y2(0) ); ---------------------------- Ave6_X1(1) <= std_logic_vector(shift_right(signed(Ave6_X1(0)), 17)); -- Ave6_X1(0) should be divided to (16*32*2^15) 2^24 and saved into Ave_X1(16bit). Ave_X11 <= Ave6_X1(0)(37) & Ave6_X1(1)(14 downto 0); givesAve_X1: component c_addsub_10 port map( A => Ave_X11, CLK => MAIN_CLK, S => Ave_X1 ); Ave6_Y1(1) <= std_logic_vector(shift_right(signed(Ave6_Y1(0)), 17)); -- Ave6_Y1(0) should be divided to (16*32*2^15) 2^24 and saved into Ave_Y1(16bit). Ave_Y11 <= Ave6_Y1(0)(37) & Ave6_Y1(1)(14 downto 0); givesAve_Y1: component c_addsub_10 port map( A => Ave_Y11, CLK => MAIN_CLK, S => Ave_Y1 ); Ave_XY1 <= Ave_X1(15 downto 0) & Ave_Y1(15 downto 0); ---------------------------- Ave6_X2(1) <= std_logic_vector(shift_right(signed(Ave6_X2(0)), 17)); -- Ave6_X2(0) should be divided to (16*32*2^15) 2^24 and saved into Ave_X2(16bit). Ave_X2 <= Ave6_X2(0)(37) & Ave6_X2(1)(14 downto 0); Ave6_Y2(1) <= std_logic_vector(shift_right(signed(Ave6_Y2(0)), 17)); -- Ave6_Y2(0) should be divided to (16*32*2^15) 2^24 and saved into Ave_Y2(16bit). Ave_Y2 <= Ave6_Y2(0)(37) & Ave6_Y2(1)(14 downto 0); Ave_XY2 <= Ave_X2(15 downto 0) & Ave_Y2(15 downto 0); -------------------------------------------------------------------------------------end3-33 gives_Ave_PHI1 :component cordic_1 port map ( aclk => MAIN_CLK, s_axis_cartesian_tvalid => D_In_Ready, s_axis_cartesian_tdata => Ave_XY1, m_axis_dout_tvalid => open, m_axis_dout_tdata => Ave_PHI1 ); ---------------------------- gives_Ave_PHI2 :component cordic_1 port map ( aclk => MAIN_CLK, s_axis_cartesian_tvalid => D_In_Ready, s_axis_cartesian_tdata => Ave_XY2, m_axis_dout_tvalid => open, m_axis_dout_tdata => Ave_PHI2 ); -------------------------------------------------------------------------------------end3-34 gives_sqr_Ave_X1 : component mult_gen_1 -- sqr_Ave_X1 = Ave_X1*Ave_X1 port map ( CLK => MAIN_CLK, A => Ave_X1, B => Ave_X1, P => sqr_Ave_X1 ); ---------------------------- gives_sqr_Ave_Y1 : component mult_gen_1 -- sqr_Ave_Y1 = Ave_Y1*Ave_Y1 port map ( CLK => MAIN_CLK, A => Ave_Y1, B => Ave_Y1, P => sqr_Ave_Y1 ); ---------------------------- gives_sqr_Ave_X2 : component mult_gen_1 -- sqr_Ave_X2 = Ave_X2*Ave_X2 port map ( CLK => MAIN_CLK, A => Ave_X2, B => Ave_X2, P => sqr_Ave_X2 ); ---------------------------- gives_sqr_Ave_Y2 : component mult_gen_1 -- sqr_Ave_Y2 = Ave_Y2*Ave_Y2 port map ( CLK => MAIN_CLK, A => Ave_Y2, B => Ave_Y2, P => sqr_Ave_Y2 ); -------------------------------------------------------------------------------------end3-35 gives_sqr_Ave_R1 : component c_addsub_4 -- calculate sqr_Ave_R1= sqr_Ave_X1+sqr_Ave_Y1 port map ( CLK => MAIN_CLK, A => sqr_Ave_X1, B => sqr_Ave_Y1, S => sqr_Ave_R1 ); sqr_Ave_R1_2 <= "0000000" & sqr_Ave_R1(32 downto 0); ---------------------------------------------------- gives_sqr_Ave_R2 : component c_addsub_4 -- calculate sqr_Ave_R2= sqr_Ave_X2+sqr_Ave_Y2 port map ( CLK => MAIN_CLK, A => sqr_Ave_X2, B => sqr_Ave_Y2, S => sqr_Ave_R2 ); sqr_Ave_R2_2 <= "0000000" & sqr_Ave_R2(32 downto 0); -------------------------------------------------------------------------------------end3-36 gives_Ave_R1 :component cordic_0 -- calculate Ave_R1= sqrt(sqr_Ave_R1) port map ( aclk => MAIN_CLK, s_axis_cartesian_tvalid => D_In_Ready, s_axis_cartesian_tdata => sqr_Ave_R1_2, m_axis_dout_tvalid => D_out_Ready, m_axis_dout_tdata => Ave_R1 ); ---------------------------------------------------- gives_Ave_R2 :component cordic_0 -- calculate Ave_R2= sqrt(sqr_Ave_R2) port map ( aclk => MAIN_CLK, s_axis_cartesian_tvalid => D_In_Ready, s_axis_cartesian_tdata => sqr_Ave_R2_2, m_axis_dout_tvalid => open, m_axis_dout_tdata => Ave_R2 ); -------------------------------------------------------------------------------------end3-37 Clock : clk_wiz_0 port map ( clk_out1 => CLK_100MHz, clk_out2 => MAIN_CLK, clk_out3 => Photo_CLK, reset => CLK_Reset, locked => MMCM_Locked, clk_in1 => CLK ); -------------------------------------------------------------------------------------end3-38 segment1: DigitToSeg port map( in1 => dig0, in2 => dig1, in3 => dig2, in4 => dig3, in5 => dig4, in6 => dig5, in7 => dig6, in8 => "0000", mclk => MAIN_CLK, an => an, dp => open, seg => seg ); dp <= '1'; -------------------------------------------------------------------------------------end3-40 process(MAIN_CLK, MMCM_Locked)-- Read Digital Input begin if rising_edge(MAIN_CLK) then if (CLK_Reset = '1') then counter1 <= 0; counter2 <= 0; counter3 <= 0; end if; counter1 <= counter1 + 1; counter2 <= counter2 + 1; counter3 <= counter3 + 1; if (counter1 = 82) then -- generate 10 MHz clock from 200 HHz MAIN_CLK counter1 <= 63; probe_0(11 downto 0) <= D(11 downto 0); data_1(0)(11 downto 0) <= D(11 downto 0); Ave1_X1(0) <= X1_6(0); Ave1_Y1(0) <= Y1_6(0); Ave1_X2(0) <= X2_6(0); Ave1_Y2(0) <= Y2_6(0); C1(0) <= C1(31); S1(0) <= S1(31); C2(0) <= C2(31); S2(0) <= S2(31); My_loop0: for i in 31 downto 1 loop data_1(i) <= data_1(i-1); C1(i) <= C1(i-1); S1(i) <= S1(i-1); Ave1_X1(i) <= Ave1_X1(i-1); Ave1_Y1(i) <= Ave1_Y1(i-1); C2(i) <= C2(i-1); S2(i) <= S2(i-1); Ave1_X2(i) <= Ave1_X2(i-1); Ave1_Y2(i) <= Ave1_Y2(i-1); end loop My_loop0; end if; if (counter2 = 113) then counter2 <= 94; D_In_Ready <= '1'; probe_1 <= "1"; else D_In_Ready <= '0'; probe_1 <= "0"; end if; if (D_out_Ready = '1') then probe_2 <= "1"; else probe_2 <= "0"; end if; if (counter3 > 127 and counter3 < 138) then -- Send data to LabVIEW @ 5 MHz speed based on a 200 MHz clock Dec_CLK <= '1'; D_Out <= Ave_R1 (15 downto 0); probe_4 <= Ave_R1 (15 downto 0); probe_3 <= "1"; elsif (counter3 > 137 and counter2 < 148) then Dec_CLK <= '0'; D_Out <= Ave_R2 (15 downto 0); probe_4 <= Ave_R2 (15 downto 0); probe_3 <= "0"; if (counter3 = 147) then counter3 <= 128; end if; end if; end if; end process; -------------------------------------------------------------------------------------end3-41 reset_bcd <= NOT MMCM_Locked; --Binary to Decimal conversion gives_digis : component bin2bcd port map ( mclk => MAIN_CLK, reset => reset_bcd, binary_in => Bin_Data , bcd0 => dig0 , bcd1 => dig1 , bcd2 => dig2 , bcd3 => dig3 , bcd4 => dig4 , bcd5 => dig5 , bcd6 => dig6 ); ----------------- process(MAIN_CLK) begin if rising_edge(MAIN_CLK) then --Show data_1(0) in LEDs and 7 Segments count <= count + 1; if (count = 999) then count <= 0; count2 <= count2+1; if(count2 = 4899)then count2 <= 0; Bin_Data <= data_1(0)(11) & "0000" & data_1(0)(10 downto 0); LED <= data_1(0)(11) & "0000" & data_1(0)(10 downto 0); end if; end if; end if; end process; -------------------------------------------------------------------------------------end3-42 ILA: ila_0 port map ( clk => MAIN_CLK, probe0 => probe_0, probe1 => probe_1, probe2 => probe_2, probe3 => probe_3, probe4 => probe_4 ); -------------------------------------------------------------------------------------end3-43 end Behavior; -----------------------------------------------------------------------------------------end3