----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 06/02/2016 01:42:18 PM
-- Design Name: 
-- Module Name: TOP - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TOP is
    Port ( clk : in STD_LOGIC;
           led0 : out STD_LOGIC;
           led1 : out STD_LOGIC;
           led2 : out STD_LOGIC;
           led3 : out STD_LOGIC;
           led4 : out STD_LOGIC;
           led5 : out STD_LOGIC;
           led6 : out STD_LOGIC;
           led7 : out STD_LOGIC;
           led8 : out STD_LOGIC;
           led9 : out STD_LOGIC;
           led10 : out STD_LOGIC;
           led11 : out STD_LOGIC;
           led12 : out STD_LOGIC;
           led13 : out STD_LOGIC;
           led14 : out STD_LOGIC;
           led15 : out STD_LOGIC);
          
           
end TOP;

architecture Behavioral of TOP is
signal rand_sig : std_logic_vector(15 downto 0);
component RandGen is
    port (clk : in STD_LOGIC;
           RandNum : out std_logic_vector (15 downto 0));
    end component;
begin

rand: RandGen
    port map ( clk => clk,
               RandNum => rand_sig);
               
led0 <= rand_sig(0);
led1 <= rand_sig(1);
led2 <= rand_sig(2);
led3 <= rand_sig(3);
led4 <= rand_sig(4);
led5 <= rand_sig(5);
led6 <= rand_sig(6);
led7 <= rand_sig(7);
led8 <= rand_sig(8);
led9 <= rand_sig(9);
led10 <= rand_sig(10);
led11 <= rand_sig(10);
led12 <= rand_sig(12);
led13 <= rand_sig(13);
led14 <= rand_sig(14);
led15 <= rand_sig(15);

               

end Behavioral;