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-- Company: 
-- Engineer: 
-- 
-- Create Date: 05/29/2016 02:58:47 PM
-- Design Name: 
-- Module Name: RandGen - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RandGen is
    Port ( clk : in STD_LOGIC;
           RandNum : out std_logic_vector (15 downto 0));
end RandGen;
architecture Behavioral of RandGen is
signal a : std_logic;
signal b : std_logic;
signal c : std_logic;
signal d : std_logic;
signal RandNum0 : std_logic_vector (3 downto 0);
signal RandNum1 : std_logic_vector (3 downto 0);
signal RandNum2 : std_logic_vector (3 downto 0);
signal RandNum3 : std_logic_vector (3 downto 0);
begin

Rand0: process (clk)
begin
    RandNum0 <= "0011"; 
    if (rising_edge(clk)) then
        a <= RandNum0(0) XOR RandNum0(1);
        RandNum0(0) <= RandNum0(1);
        RandNum0(1) <= RandNum0(2);
        RandNum0(2) <= RandNum0(3);
        RandNum0(3) <= a;
    end if;   
end process;

Rand1: process (clk)
begin
    RandNum1 <= "1010"; 
    if (rising_edge(clk)) then
        b <= RandNum1(0) XOR RandNum1(1);
        RandNum1(0) <= RandNum1(1);
        RandNum1(1) <= RandNum1(2);
        RandNum1(2) <= RandNum1(3);
        RandNum1(3) <= b;
    end if;
end process;

Rand2: process (clk)
begin
    RandNum2 <= "0101"; 
    if (rising_edge(clk)) then
        c <= RandNum2(0) XOR RandNum2(1);
        RandNum2(0) <= RandNum2(1);
        RandNum2(1) <= RandNum2(2);
        RandNum2(2) <= RandNum2(3);
        RandNum2(3) <= c;
    end if;  
end process;

Rand3: process (clk)
begin
    RandNum3 <= "1101"; 
    if (rising_edge(clk)) then
        d <= RandNum3(0) XOR RandNum3(1);
        RandNum3(0) <= RandNum3(1);
        RandNum3(1) <= RandNum3(2);
        RandNum3(2) <= RandNum3(3);
        RandNum3(3) <= d;
    end if;  
end process;

RandNum <= RandNum3 & RandNum2 & RandNum1 & RandNum0;

end Behavioral;