0:      Using B.0 cmod_a7-35t board_file

1.      Launch Vivado 2018.2
2.      "Create Project"
            RTL Project ->
                Do not specify sources at this time
            Board: Cmod A7-35t
3.      Tools -> Run Tcl Script..
            File: user_35t_bd.tcl
4.      Validate Design
5.      Project Manager Settings:
            Bitstream ->
                Select -mask_file, -bin_file, -readback_file, logic_logication_file
            OK
6.      Sources -> Design Sources -> Create HDL Wrapper
            Let Vivado manage Wrapper and auto-update
7.      Sources -> Constraints -> Add Sources
            Add or create constraints
                Add Files..
                    Add Cmod-A7-35T.xdc

                        Contents:
                            set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
                            set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
                            set_property CONFIG_MODE SPIx4 [current_design]

                    Select "Copy constraints files into project"
                Finish
8.      Sources -> Design Sources -> user_35t_wrapper -> Generate Output Products...
            Out of context per IP
                Generate
9.      Generate Bitstream
10.     Open Implementation
11.     Export Hardware
            -> Include bitstream
            -> Export to: <Local to Project>
12.     Launch SDK

# Start: https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start
13.     File -> New -> Application Project
            Project Name: srec_spi_bootloader
        Next ->
            Avaliable Templates: "SREC SPI Bootloader"
        Finish
14.     Modify blconfig.h in srec_spi_bootloader project
            Change From: #define FLASH_IMAGE_BASEADDR  0xF8000000
            Change To:   #define FLASH_IMAGE_BASEADDR  0x00300000
15.     Right Click on srec_spi_bootloader_bsp
            Ensure Xilisf is checked and at version > 5.2 [is at 5.11]
            Go to Overview -> standalone -> xilisf
                Change "serial_flash_family" to 5
                OK
            Note: BSP should rebuild, if not click Re-generate BSP Sources
16.     File -> New -> Application Project
            Project Name: hello_world
        Next ->
            Avaliable Templates: "Hello World"
        Finish
17.     On hello_world project, Right click -> "Generate Linker Script"
            In Basic Tab:
                Change To:
                    Place Code Sections in: axi_emc_0_MEM0_BASEADDR_Mem0
                    Place Data Sections in: axi_emc_0_MEM0_BASEADDR_Mem0
                    Place Heap Sections in: axi_emc_0_MEM0_BASEADDR_Mem0
            Generate
18.     Project -> Build All (Should already be current if automatic building is on)
19.     Xilinx -> Program FPGA
            Software Configuration: Find and select the debug "srec_spi_bootloader.elf"
20.     Xilinx -> Program Flash
            Image File: Find and select the debug "hello_world.elf"
            Offset: 0x00300000
            Flash Type: n25q32-3.3v-spi-x1_x2_x4
            Check "Convert ELF to bootloadable SREC format and program"
            Check "Blank check after erase"
            Check "Verify after flash"
            Program
21.     Xilinx -> Program Flash
            Image File: Find and select "download.bit" under user_35t_wrapper_hw_platform_0
            Offset: 0
            Flash Type: n25q32-3.3v-spi-x1_x2_x4
            Check "Blank check after erase"
            Check "Verify after flash"
            Program
Test

Does not run automatically.  Button must be pressed to start execution.