Synthesis Log
Created on 13:55:31 03/08/2015
Running XST Synthesis...
Please wait...
Release 14.7 - xst P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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rameter TMPDIR set to .
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
--> Parameter xsthdpdir set to c:\My_Designs\Example1\synthesis\xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "sw2led.prj"
Input Format : mixed
Ignore Synthesis Constraint File : no
---- Target Parameters
Output File Name : "sw2led"
Output Format : NGC
Target Device : xc3s100ecp132-5
---- Source Options
Top Module Name : sw2led
Generics, Parameters : { }
Verilog Macros : { }
Automatic FSM Extraction : yes
FSM Encoding Algorithm : Auto
Resource Sharing : yes
FSM Style : lut
RAM Extraction : yes
RAM Style : auto
ROM Extraction : yes
ROM Style : auto
Mux Extraction : yes
Mux Style : auto
Decoder Extraction : yes
Priority Encoder Extraction : yes
Shift Register Extraction : yes
Logical Shifter Extraction : yes
XOR Collapsing : yes
Multiplier Style : auto
Asynchronous To Synchronous : no
Automatic Register Balancing : no
Safe Implementation : no
---- Target Options
Add IO Buffers : yes
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : yes
Equivalent register Removal : yes
Pack IO Registers into IOBs : auto
Slice Packing : yes
Optimize Instantiated Primitives : no
Use Clock Enable : yes
Use Synchronous Set : yes
Use Synchronous Reset : yes
---- General Options
Optimization Goal : speed
Optimization Effort : 1
Global Optimization : allclocknets
RTL Output : yes
Write Timing Constraints : no
Verilog 2001 : yes
Keep Hierarchy : no
Netlist Hierarchy : as_optimized
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Cross Clock Analysis : no
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Read Cores : yes
Auto BRAM Packing : no
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/My_Designs/Example1/compile/sw2led.vhd" in Library swled.
Architecture sw2led of Entity sw2led is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <sw2led> in library <swled> (architecture <sw2led>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <sw2led> in library <swled> (Architecture <sw2led>).
Entity <sw2led> analyzed. Unit <sw2led> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <sw2led>.
Related source file is "C:/My_Designs/Example1/compile/sw2led.vhd".
Unit <sw2led> synthesized.
=========================================================================
HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <sw2led> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block sw2led, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : sw2led.ngr
Top Level Output File Name : sw2led
Output Format : NGC
Optimization Goal : speed
Keep Hierarchy : no
Design Statistics
# IOs : 16
Cell Usage :
# IO Buffers : 16
# IBUF : 8
# OBUF : 8
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s100ecp132-5
Number of Slices: 0 out of 960 0%
Number of IOs: 16
Number of bonded IOBs: 16 out of 83 19%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 4.632ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Delay: 4.632ns (Levels of Logic = 2)
Source: sw<7> (PAD)
Destination: ld<7> (PAD)
Data Path: sw<7> to ld<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.106 0.357 sw_7_IBUF (ld_7_OBUF)
OBUF:I->O 3.169 ld_7_OBUF (ld<7>)
----------------------------------------
Total 4.632ns (4.275ns logic, 0.357ns route)
(92.3% logic, 7.7% route)
=========================================================================
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.77 secs
-->
Total memory usage is 219388 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM
simulation primitives and has to be used with UNISIM library for correct
compilation and simulation.
Synthesis finished successfully.