Implement Log
Created on 17:13:58 03/08/2015
InputFile = c:/My_Designs/Example1/implement/xie0.ini
Executing "C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\ngdbuild.exe" -p 3S100ECP132-5 -aul -sd "c:\My_Designs\Example1\synthesis" -sd "c:\My_Designs\Example1\compile" -sd "c:\My_Designs\Example1\src" -sd "C:\Aldec\Active-HDL Student Edition\vlib\SPARTAN3E\compile" -uc "sw2led.ucf" "sw2led.ngc" "sw2led.ngd"
Release 14.7 - ngdbuild P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -p
3S100ECP132-5 -aul -sd c:\My_Designs\Example1\synthesis -sd
c:\My_Designs\Example1\compile -sd c:\My_Designs\Example1\src -sd
C:\Aldec\Active-HDL Student Edition\vlib\SPARTAN3E\compile -uc sw2led.ucf
sw2led.ngc sw2led.ngd
Reading NGO file "c:/My_Designs/Example1/implement/ver1/rev1/sw2led.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "sw2led.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
INFO:ConstraintSystem:59 - Constraint <NET "btn<3>" LOC = "a7";>
[sw2led.ucf(22)]: NET "btn<3>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "btn<3>" LOC = "a7";> [sw2led.ucf(22)]' could not be found and so the
Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "btn<2>" LOC = "m4";>
[sw2led.ucf(23)]: NET "btn<2>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "btn<2>" LOC = "m4";> [sw2led.ucf(23)]' could not be found and so the
Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "btn<1>" LOC = "c11";>
[sw2led.ucf(24)]: NET "btn<1>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "btn<1>" LOC = "c11";> [sw2led.ucf(24)]' could not be found and so the
Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "btn<0>" LOC = "g12";>
[sw2led.ucf(25)]: NET "btn<0>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "btn<0>" LOC = "g12";> [sw2led.ucf(25)]' could not be found and so the
Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "a_to_g<6>" LOC = "l14" ;>
[sw2led.ucf(28)]: NET "a_to_g<6>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "a_to_g<6>" LOC = "l14" ;> [sw2led.ucf(28)]' could not be found and
so the Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "a_to_g<5>" LOC = "h12" ;>
[sw2led.ucf(29)]: NET "a_to_g<5>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "a_to_g<5>" LOC = "h12" ;> [sw2led.ucf(29)]' could not be found and
so the Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "a_to_g<4>" LOC = "n14" ;>
[sw2led.ucf(30)]: NET "a_to_g<4>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "a_to_g<4>" LOC = "n14" ;> [sw2led.ucf(30)]' could not be found and
so the Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "a_to_g<3>" LOC = "n11" ;>
[sw2led.ucf(31)]: NET "a_to_g<3>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "a_to_g<3>" LOC = "n11" ;> [sw2led.ucf(31)]' could not be found and
so the Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "a_to_g<2>" LOC = "p12" ;>
[sw2led.ucf(32)]: NET "a_to_g<2>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "a_to_g<2>" LOC = "p12" ;> [sw2led.ucf(32)]' could not be found and
so the Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "a_to_g<1>" LOC = "l13" ;>
[sw2led.ucf(33)]: NET "a_to_g<1>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "a_to_g<1>" LOC = "l13" ;> [sw2led.ucf(33)]' could not be found and
so the Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "a_to_g<0>" LOC = "m12" ;>
[sw2led.ucf(34)]: NET "a_to_g<0>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "a_to_g<0>" LOC = "m12" ;> [sw2led.ucf(34)]' could not be found and
so the Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "dp" LOC = "n13" ;>
[sw2led.ucf(35)]: NET "dp" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "dp" LOC = "n13" ;> [sw2led.ucf(35)]' could not be found and so the
Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "an<3>" LOC = "k14";>
[sw2led.ucf(37)]: NET "an<3>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "an<3>" LOC = "k14";> [sw2led.ucf(37)]' could not be found and so the
Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "an<2>" LOC = "m13";>
[sw2led.ucf(38)]: NET "an<2>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "an<2>" LOC = "m13";> [sw2led.ucf(38)]' could not be found and so the
Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "an<1>" LOC = "j12";>
[sw2led.ucf(39)]: NET "an<1>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "an<1>" LOC = "j12";> [sw2led.ucf(39)]' could not be found and so the
Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "an<0>" LOC = "f12";>
[sw2led.ucf(40)]: NET "an<0>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "an<0>" LOC = "f12";> [sw2led.ucf(40)]' could not be found and so the
Locate constraint will be removed.
INFO:ConstraintSystem:59 - Constraint <NET "clk" LOC = "b8";> [sw2led.ucf(43)]:
NET "clk" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<NET "clk" LOC = "b8";> [sw2led.ucf(43)]' could not be found and so the
Locate constraint will be removed.
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 17
Writing NGD file "sw2led.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "sw2led.bld"...
NGDBUILD done.
Executing "C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\map.exe" -p 3S100ECP132-5 -o "map.ncd" -pr off -cm area -ir off -c 100 "sw2led.ngd" "sw2led.pcf"
Release 14.7 - Map P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Using target part "3s100ecp132-5".
Mapping design into LUTs...
Writing file map.ngm...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
Writing design file "map.ncd"...
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Logic Distribution:
Number of Slices containing only related logic: 0 out of 0 0%
Number of Slices containing unrelated logic: 0 out of 0 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Number of bonded IOBs: 16 out of 83 19%
Average Fanout of Non-Clock Nets: 1.00
Peak Memory Usage: 218 MB
Total REAL time to MAP completion: 2 secs
Total CPU time to MAP completion: 1 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "map.mrp" for details.
Executing "C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\trce.exe" -v 3 -s 5 -n 3 -fastpaths "map.ncd" "sw2led.pcf" -o "sw2led_postmap.twr"
Release 14.7 - Trace (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '3s100e.nph' in environment
C:\Xilinx\14.7\ISE_DS\ISE\.
"sw2led" is an NCD, version 3.2, device xc3s100e, package cp132, speed -5
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
--------------------------------------------------------------------------------
Release 14.7 Trace (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -v 3 -s 5 -n 3 -fastpaths
map.ncd sw2led.pcf -o sw2led_postmap.twr
Design file: map.ncd
Physical constraint file: sw2led.pcf
Device,speed: xc3s100e,-5 (PRODUCTION 1.27 2013-10-13)
Report level: verbose report
--------------------------------------------------------------------------------
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a
50 Ohm transmission line loading model. For the details of this model, and
for more information on accounting for different loading conditions, please
see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock Uncertainty
calculation. Please make appropriate modification to SYSTEM_JITTER to
account for the unsupported Discrete Jitter and Phase Error.
Analysis completed Sun Mar 08 17:13:41 2015
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 0
Number of info messages: 7
Total time: 1 secs
Executing "C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\par.exe" -w -ol std -t 1 map.ncd "sw2led.ncd" "sw2led.pcf"
Release 14.7 - par P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Constraints file: sw2led.pcf.
Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
"sw2led" is an NCD, version 3.2, device xc3s100e, package cp132, speed -5
INFO:Par:469 - Although the Overall Effort Level (-ol) for this implementation has been set to Standard, Placer will run
at effort level High. To override this, please set the Placer Effort Level (-pl) to Standard.
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
Device speed data version: "PRODUCTION 1.27 2013-10-13".
Design Summary Report:
Number of External IOBs 16 out of 83 19%
Number of External Input IOBs 8
Number of External Input IBUFs 8
Number of LOCed External Input IBUFs 8 out of 8 100%
Number of External Output IOBs 8
Number of External Output IOBs 8
Number of LOCed External Output IOBs 8 out of 8 100%
Number of External Bidir IOBs 0
Overall effort level (-ol): Standard
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard
Starting initial Timing Analysis. REAL time: 1 secs
Finished initial Timing Analysis. REAL time: 1 secs
Starting Placer
Total REAL time at the beginning of Placer: 2 secs
Total CPU time at the beginning of Placer: 1 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:3b1495f) REAL time: 2 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:3b1495f) REAL time: 2 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:3b1495f) REAL time: 2 secs
Phase 4.2 Initial Clock and IO Placement
Phase 4.2 Initial Clock and IO Placement (Checksum:3b1495f) REAL time: 2 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:3b1495f) REAL time: 2 secs
Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:3b1495f) REAL time: 2 secs
Phase 7.8 Global Placement
Phase 7.8 Global Placement (Checksum:3b1495f) REAL time: 2 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:3b1495f) REAL time: 2 secs
Phase 9.18 Placement Optimization
Phase 9.18 Placement Optimization (Checksum:3b1495f) REAL time: 2 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:3b1495f) REAL time: 2 secs
Total REAL time to Placer completion: 2 secs
Total CPU time to Placer completion: 2 secs
Writing design to file sw2led.ncd
Starting Router
Phase 1 : 8 unrouted; REAL time: 3 secs
Phase 2 : 8 unrouted; REAL time: 3 secs
Phase 3 : 0 unrouted; REAL time: 3 secs
Phase 4 : 0 unrouted; (Par is working to improve performance) REAL time: 4 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 4 secs
Updating file: sw2led.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 4 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 4 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 4 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 4 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 4 secs
Total REAL time to Router completion: 4 secs
Total CPU time to Router completion: 3 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
Timing Score: 0 (Setup: 0, Hold: 0)
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 4 secs
Total CPU time to PAR completion: 3 secs
Peak Memory Usage: 223 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 2
Writing design to file sw2led.ncd
PAR done!
Executing "C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\trce.exe" -v 3 -s 5 -n 3 -fastpaths "sw2led.ncd" "sw2led.pcf" -o "sw2led_postpar.twr"
Release 14.7 - Trace (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '3s100e.nph' in environment
C:\Xilinx\14.7\ISE_DS\ISE\.
"sw2led" is an NCD, version 3.2, device xc3s100e, package cp132, speed -5
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
--------------------------------------------------------------------------------
Release 14.7 Trace (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -v 3 -s 5 -n 3 -fastpaths
sw2led.ncd sw2led.pcf -o sw2led_postpar.twr
Design file: sw2led.ncd
Physical constraint file: sw2led.pcf
Device,speed: xc3s100e,-5 (PRODUCTION 1.27 2013-10-13)
Report level: verbose report
--------------------------------------------------------------------------------
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a
50 Ohm transmission line loading model. For the details of this model, and
for more information on accounting for different loading conditions, please
see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock Uncertainty
calculation. Please make appropriate modification to SYSTEM_JITTER to
account for the unsupported Discrete Jitter and Phase Error.
Analysis completed Sun Mar 08 17:13:50 2015
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 0
Number of info messages: 6
Total time: 1 secs
Executing "C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\netgen.exe" -w -sim -ofmt vhdl -pcf "sw2led.pcf" -tpw 0 -rpw 100 -s 5 -ar Structure -insert_pp_buffers true "sw2led.ncd" "time_sim.vhd"
Release 14.7 - netgen P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: netgen -w -sim -ofmt vhdl -pcf sw2led.pcf -tpw 0 -rpw 100 -s 5
-ar Structure -insert_pp_buffers true sw2led.ncd time_sim.vhd
Read and Annotate design 'sw2led.ncd' ...
Flattening design ...
Processing design ...
Preping design's networks ...
Preping design's macros ...
Writing VHDL netlist 'time_sim.vhd' ...
Writing VHDL SDF file 'time_sim.sdf' ...
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM
simulation primitives and has to be used with SIMPRIM library for correct
compilation and simulation.
INFO:NetListWriters - Xilinx recommends running separate simulations to check
for setup by specifying the MAX field in the SDF file and for hold by
specifying the MIN field in the SDF file. Please refer to Simulator
documentation for more details on specifying MIN and MAX field in the SDF.
INFO:NetListWriters:665 - For more information on how to pass the SDF switches
to the simulator, see your Simulator tool documentation.
Number of warnings: 0
Number of info messages: 3
Total memory usage is 153324 kilobytes
Created netgen log file 'time_sim.nlf'.
Executing "C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\bitgen.exe" -intstyle ise -f "sw2led.ut" "sw2led.ncd" "sw2led" "sw2led.pcf"
Implementation ver1->rev1: 0 error(s), 17 warning(s)
Implementation ended with warning(s).