`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 12/27/2018 02:47:19 PM // Design Name: // Module Name: check // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module check( input clk, inout rx, inout tx, inout cts, inout rts, inout status, inout reset, //input sw0, output reg led0, output reg led1 ); integer char; initial begin led0 <= 0; led1 <=0; char <= rx; // rts <= 0; // cts <= 0; // reset <= 0; end always@(posedge clk) begin if(tx == 1) begin led0 <= 0; led1 <= 0; end else if(tx == 0) begin led0 <= 1; led1 <= 1; // if(tx == 0) // led1 <= 1; // else // led1 <= 0; end end endmodule