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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:02:50 05/12/2016 
-- Design Name: 
-- Module Name:    porte - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

library ieee;
use ieee.std_logic_1164.all;

entity porte is
	port (clk : in std_logic;
	reset : in std_logic;
	keyon : in std_logic;
	keycode : in std_logic_vector(7 downto 0);
	opendoor : out std_logic);
end porte;

architecture synth of porte is

	type typeetat is (S0, S1, S2);
	signal state, next_state : typeetat;
	signal reg : std_logic_vector(31 downto 0);
	signal ld_shift_right_3, shift_left_3 : std_logic;
begin
		shiftreg: process(clk, reset)
		begin
			if reset='1' then 
				reg <= (others=>'0');
			elsif (clk'event and clk='1') then
				if (ld_shift_right_3='1') then 
					reg <= keycode & reg(31 downto 8);
				elsif (shift_left_3='1')
					then reg <= reg(23 downto 0) & "00000000";
				end if;
			end if;
		end process shiftreg;
		
		sync: process(clk, reset)
		begin
			if (reset='1')
				then state <= s0;
			elsif (clk'event and clk='1')
				then state <= next_state;
			end if;
		end process sync;
		
		ctrl: process(state, keycode, keyon, reg)
		begin
		ld_shift_right_3 <= '0';
		shift_left_3 <= '0';
		next_state <= state;
		opendoor <= '0';
		case state is
			when s0 =>
				if (keyon='1') then
					if(keycode="11111111") then 
						shift_left_3 <= '1';
					else 
						ld_shift_right_3 <= '1';
					end if;
					next_state <= s1;
				end if;
				
			when s1 =>
				if (reg="01000010001100110100101101001011") --    K'H'L'L
				then
					opendoor <= '1';
					next_state <= s2;
				elsif (keyon='0') then 
					next_state <= s0;
				end if;
			when s2 =>
			if (keyon='0')
				then next_state <= s0;
			end if;
		end case;
	end process ctrl;
end synth;