#----------------------------------------------------------- # Vivado v2017.4.1 (64-bit) # SW Build 2117270 on Tue Jan 30 15:32:00 MST 2018 # IP Build 2095745 on Tue Jan 30 17:13:15 MST 2018 # Start of session at: Wed Sep 12 06:42:48 2018 # Process ID: 12188 # Current directory: D:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.runs/zybo_z7_20_v_frmbuf_wr_0_0_synth_1 # Command line: vivado.exe -log zybo_z7_20_v_frmbuf_wr_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source zybo_z7_20_v_frmbuf_wr_0_0.tcl # Log file: D:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.runs/zybo_z7_20_v_frmbuf_wr_0_0_synth_1/zybo_z7_20_v_frmbuf_wr_0_0.vds # Journal file: D:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.runs/zybo_z7_20_v_frmbuf_wr_0_0_synth_1\vivado.jou #----------------------------------------------------------- source zybo_z7_20_v_frmbuf_wr_0_0.tcl -notrace ****** Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2017.4.1 (64-bit) **** SW Build 2117270 on Tue Jan 30 15:32:00 MST 2018 **** IP Build 2095745 on Tue Jan 30 17:13:15 MST 2018 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source C:/Xilinx/Vivado/2017.4/scripts/vivado_hls/hls.tcl -notrace INFO: [HLS 200-10] Running 'C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/vivado_hls.exe' INFO: [HLS 200-10] For user 'Albert' on host 'z170' (Windows NT_amd64 version 6.2) on Wed Sep 12 06:43:01 +0800 2018 INFO: [HLS 200-10] In directory 'D:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.runs/zybo_z7_20_v_frmbuf_wr_0_0_synth_1' INFO: [HLS 200-10] Creating and opening project 'D:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.runs/zybo_z7_20_v_frmbuf_wr_0_0_synth_1/zybo_z7_20_v_frmbuf_wr_0_0'. INFO: [HLS 200-10] Adding design file 'd:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr_config.h' to the project INFO: [HLS 200-10] Adding design file 'd:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp' to the project INFO: [HLS 200-10] Adding design file 'd:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.h' to the project INFO: [HLS 200-10] Creating and opening solution 'D:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.runs/zybo_z7_20_v_frmbuf_wr_0_0_synth_1/zybo_z7_20_v_frmbuf_wr_0_0/prj'. INFO: [HLS 200-10] Setting target device to 'xc7z020clg400-1' INFO: [SYN 201-201] Setting up clock 'ap_clk' with a period of 10ns. INFO: [HLS 200-10] Analyzing design file 'd:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp' ... INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 99.926 ; gain = 43.922 INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:01 ; elapsed = 00:00:09 . Memory (MB): peak = 99.938 ; gain = 43.934 INFO: [HLS 200-10] Starting code transformations ... INFO: [XFORM 203-603] Inlining function 'hls::AXIGetBitFields<24, ap_uint<8> >.1' into 'hls::AXIGetBitFields<24, ap_uint<8> >' (C:/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_axi_io.h:71). INFO: [XFORM 203-603] Inlining function 'hls::AXIGetBitFields<24, ap_uint<8> >' into 'AXIvideo2MultiPixStream' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:166). INFO: [XFORM 203-603] Inlining function 'hls::AXIGetBitFields<24, ap_uint<8> >' into 'AXIvideo2MultiPixStream' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:167). INFO: [XFORM 203-603] Inlining function 'hls::AXIGetBitFields<24, ap_uint<8> >' into 'AXIvideo2MultiPixStream' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:168). INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 124.656 ; gain = 68.652 INFO: [HLS 200-10] Checking synthesizability ... WARNING: [SYNCHK 200-23] d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:350: variable-indexed range selection may cause suboptimal QoR. INFO: [SYNCHK 200-10] 0 error(s), 1 warning(s). INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 140.645 ; gain = 84.641 INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'Loop-1.1' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:340) in function 'MultiPixStream2Bytes' for pipelining. INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'Loop-2.1' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:376) in function 'MultiPixStream2Bytes' for pipelining. INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'Loop-3.1' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:410) in function 'MultiPixStream2Bytes' for pipelining. INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'loop_width' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:146) in function 'AXIvideo2MultiPixStream' for pipelining. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.1' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:343) in function 'MultiPixStream2Bytes' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.1.1' (C:/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:171) in function 'MultiPixStream2Bytes' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.1.2' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:346) in function 'MultiPixStream2Bytes' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.1.2.1' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:348) in function 'MultiPixStream2Bytes' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-2.1.1' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:379) in function 'MultiPixStream2Bytes' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-2.1.1.1' (C:/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:171) in function 'MultiPixStream2Bytes' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-2.1.1.2' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:382) in function 'MultiPixStream2Bytes' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-3.1.1' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:413) in function 'MultiPixStream2Bytes' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-3.1.1.1' (C:/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:171) in function 'MultiPixStream2Bytes' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-3.1.1.2' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:416) in function 'MultiPixStream2Bytes' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-2.1.1' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:159) in function 'AXIvideo2MultiPixStream' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-2.1.1.1' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:161) in function 'AXIvideo2MultiPixStream' completely. INFO: [XFORM 203-102] Automatically partitioning streamed array 'img.V.val.V' . INFO: [XFORM 203-101] Partitioning array 'pix.val.V' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:215) in dimension 1 completely. INFO: [XFORM 203-101] Partitioning array 'tmp.val.V' in dimension 1 completely. INFO: [XFORM 203-101] Partitioning array 'tmp.val.V.1' in dimension 1 completely. INFO: [XFORM 203-101] Partitioning array 'tmp.val.V.2' in dimension 1 completely. INFO: [XFORM 203-101] Partitioning array 'pix.val.V' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:121) in dimension 1 completely. INFO: [XFORM 203-101] Partitioning array 'map' in dimension 1 completely. INFO: [XFORM 203-712] Applying dataflow to function 'v_frmbuf_wr', detected/extracted 5 process function(s): 'Block_._crit_edge26_proc' 'AXIvideo2MultiPixStream' 'Block_._crit_edge268_proc' 'MultiPixStream2Bytes' 'Bytes2AXIMMvideo'. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (C:/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_axi_io.h:49:14) to (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:145:53) in function 'AXIvideo2MultiPixStream'... converting 4 basic blocks. INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 180.453 ; gain = 124.449 WARNING: [XFORM 203-631] Renaming function 'Block_._crit_edge26_proc' to 'Block_._crit_edge26_' WARNING: [XFORM 203-631] Renaming function 'Block_._crit_edge268_proc' to 'Block_._crit_edge268' WARNING: [XFORM 203-631] Renaming function 'AXIvideo2MultiPixStream' to 'AXIvideo2MultiPixStr' (d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:49:9) INFO: [XFORM 203-811] Inferring bus burst write of variable length on port 'dstImg.V'. INFO: [XFORM 203-811] Inferring bus burst write of variable length on port 'dstImg.V'. WARNING: [XFORM 203-631] Renaming function 'Block_._crit_edge26_4' to 'Block_._crit_edge26_' INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 241.309 ; gain = 185.305 INFO: [HLS 200-10] Starting hardware synthesis ... INFO: [HLS 200-10] Synthesizing 'v_frmbuf_wr' ... WARNING: [SYN 201-103] Legalizing function name 'Block_._crit_edge26_' to 'Block_crit_edge26_s'. WARNING: [SYN 201-103] Legalizing function name 'reg' to 'reg_unsigned_short_s'. WARNING: [SYN 201-103] Legalizing function name 'Block_._crit_edge268' to 'Block_crit_edge268'. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'Block_crit_edge26_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 13.209 seconds; current allocated memory: 190.855 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.078 seconds; current allocated memory: 190.997 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'reg_unsigned_short_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.078 seconds; current allocated memory: 191.044 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.042 seconds; current allocated memory: 191.077 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'AXIvideo2MultiPixStr' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'loop_wait_for_start'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1. INFO: [SCHED 204-61] Pipelining loop 'loop_width'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'loop_wait_for_eol'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.156 seconds; current allocated memory: 191.411 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.459 seconds; current allocated memory: 191.810 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'Block_crit_edge268' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.518 seconds; current allocated memory: 191.903 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.05 seconds; current allocated memory: 191.964 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'MultiPixStream2Bytes' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'loop_Y_UV8_Y_UV8_420.1'. INFO: [SCHED 204-61] Pipelining result : Target II = 8, Final II = 8, Depth = 10. INFO: [SCHED 204-61] Pipelining loop 'loop_UYVY8.1'. INFO: [SCHED 204-61] Pipelining result : Target II = 4, Final II = 4, Depth = 6. INFO: [SCHED 204-61] Pipelining loop 'loop_YUYV8.1'. INFO: [SCHED 204-61] Pipelining result : Target II = 4, Final II = 4, Depth = 6. WARNING: [SCHED 204-21] Estimated clock period (8.89975ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns). WARNING: [SCHED 204-21] The critical path consists of the following: fifo read on port 'tmp_8_loc' (3.63 ns) 'add' operation ('tmp_12_i_i', d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:397->d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:100) (2.08 ns) 'add' operation ('tmp_15_i_i', d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:415->d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/src/v_frmbuf_wr.cpp:100) (2.04 ns) blocking operation 1.15 ns on control path) INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.731 seconds; current allocated memory: 193.805 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 1.469 seconds; current allocated memory: 194.946 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'Bytes2AXIMMvideo' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'loop_Bytes2AXIMMvideo_2planes.1'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3. INFO: [SCHED 204-61] Pipelining loop 'loop_Bytes2AXIMMvideo_2planes.2'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 1.688 seconds; current allocated memory: 196.215 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.735 seconds; current allocated memory: 197.183 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'v_frmbuf_wr' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.661 seconds; current allocated memory: 197.379 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.362 seconds; current allocated memory: 197.999 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'Block_crit_edge26_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SYN 201-210] Renamed object name 'Block_crit_edge26_s_BYTES_PER_PIXEL' to 'Block_crit_edge26bkb' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'Block_crit_edge26_s_MEMORY2LIVE' to 'Block_crit_edge26cud' due to the length limit 20 INFO: [RTGEN 206-100] Finished creating RTL model for 'Block_crit_edge26_s'. INFO: [HLS 200-111] Elapsed time: 0.252 seconds; current allocated memory: 198.269 MB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'reg_unsigned_short_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'reg_unsigned_short_s'. INFO: [HLS 200-111] Elapsed time: 0.112 seconds; current allocated memory: 198.486 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'AXIvideo2MultiPixStr' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'AXIvideo2MultiPixStr'. INFO: [HLS 200-111] Elapsed time: 0.095 seconds; current allocated memory: 199.530 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'Block_crit_edge268' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SYN 201-210] Renamed object name 'v_frmbuf_wr_mul_mul_16s_16s_16_1_1' to 'v_frmbuf_wr_mul_mdEe' due to the length limit 20 INFO: [RTGEN 206-100] Generating core module 'v_frmbuf_wr_mul_mdEe': 1 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'Block_crit_edge268'. INFO: [HLS 200-111] Elapsed time: 0.592 seconds; current allocated memory: 199.730 MB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'MultiPixStream2Bytes' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'MultiPixStream2Bytes'. INFO: [HLS 200-111] Elapsed time: 0.141 seconds; current allocated memory: 201.812 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'Bytes2AXIMMvideo' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'Bytes2AXIMMvideo'. INFO: [HLS 200-111] Elapsed time: 2.003 seconds; current allocated memory: 204.546 MB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'v_frmbuf_wr' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/mm_video' to 'm_axi'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/HwReg_width' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/HwReg_height' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/HwReg_stride' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/HwReg_video_format' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/HwReg_frm_buffer_V' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/HwReg_frm_buffer2_V' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/s_axis_video_V_data_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/s_axis_video_V_keep_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/s_axis_video_V_strb_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/s_axis_video_V_user_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/s_axis_video_V_last_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/s_axis_video_V_id_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'v_frmbuf_wr/s_axis_video_V_dest_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on function 'v_frmbuf_wr' to 's_axilite & ap_ctrl_hs'. INFO: [RTGEN 206-100] Bundling port 'HwReg_width', 'HwReg_height', 'HwReg_stride', 'HwReg_video_format', 'HwReg_frm_buffer_V', 'HwReg_frm_buffer2_V' and 'return' to AXI-Lite port CTRL. INFO: [SYN 201-210] Renamed object name 'start_for_MultiPixStream2Bytes_U0' to 'start_for_MultiPieOg' due to the length limit 20 INFO: [RTGEN 206-100] Finished creating RTL model for 'v_frmbuf_wr'. INFO: [HLS 200-111] Elapsed time: 0.797 seconds; current allocated memory: 205.885 MB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [RTMG 210-279] Implementing memory 'zybo_z7_20_v_frmbuf_wr_0_0_Block_crit_edge26bkb_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'zybo_z7_20_v_frmbuf_wr_0_0_Block_crit_edge26cud_rom' using distributed ROMs. INFO: [RTMG 210-285] Implementing FIFO 'zybo_z7_20_v_frmbuf_wr_0_0_fifo_w32_d3_A' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'zybo_z7_20_v_frmbuf_wr_0_0_fifo_w32_d3_A' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'zybo_z7_20_v_frmbuf_wr_0_0_fifo_w16_d2_A' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'zybo_z7_20_v_frmbuf_wr_0_0_fifo_w8_d2_A' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'zybo_z7_20_v_frmbuf_wr_0_0_fifo_w12_d2_A' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'zybo_z7_20_v_frmbuf_wr_0_0_fifo_w64_d960_B' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'zybo_z7_20_v_frmbuf_wr_0_0_fifo_w64_d960_B' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'zybo_z7_20_v_frmbuf_wr_0_0_start_for_MultiPieOg' using Shift Registers. ERROR: [RTMG 210-101] Couldn't open "zybo_z7_20_v_frmbuf_wr_0_0_v_frmbuf_wr_ap_rst_n_if.v": no such file or directory auto_generate error Problem generating v_frmbuf_wr files while executing "source [lindex $::argv 1] " ("uplevel" body line 1) invoked from within "uplevel \#0 { source [lindex $::argv 1] } " INFO: [HLS 200-112] Total elapsed time: 25.53 seconds; peak allocated memory: 205.885 MB. INFO: [Common 17-206] Exiting vivado_hls at Wed Sep 12 06:43:26 2018... compile_c: Time (s): cpu = 00:00:00 ; elapsed = 00:00:27 . Memory (MB): peak = 299.980 ; gain = 0.000 Command: synth_design -top zybo_z7_20_v_frmbuf_wr_0_0 -part xc7z020clg400-1 -mode out_of_context Starting synth_design WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design. D:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/zybo_z7_20_v_frmbuf_wr_0_0.xci Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 12156 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 408.418 ; gain = 99.656 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'zybo_z7_20_v_frmbuf_wr_0_0' [d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/synth/zybo_z7_20_v_frmbuf_wr_0_0.v:58] ERROR: [Synth 8-439] module 'zybo_z7_20_v_frmbuf_wr_0_0_v_frmbuf_wr' not found [d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/synth/zybo_z7_20_v_frmbuf_wr_0_0.v:267] Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32'sb00000000000000000000000000000111 Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32'sb00000000000000000000000000100000 Parameter C_M_AXI_MM_VIDEO_ADDR_WIDTH bound to: 32'sb00000000000000000000000000100000 Parameter C_M_AXI_MM_VIDEO_DATA_WIDTH bound to: 32'sb00000000000000000000000001000000 Parameter C_M_AXI_MM_VIDEO_PROT_VALUE bound to: 32'b00000000000000000000000000000000 Parameter C_M_AXI_MM_VIDEO_CACHE_VALUE bound to: 32'b00000000000000000000000000000011 ERROR: [Synth 8-285] failed synthesizing module 'zybo_z7_20_v_frmbuf_wr_0_0' [d:/sharefolder/reVISION-Zybo-Z7-20-2017.4-3/vivado/zybo_z7_20/zybo_z7_20.srcs/sources_1/bd/zybo_z7_20/ip/zybo_z7_20_v_frmbuf_wr_0_0/synth/zybo_z7_20_v_frmbuf_wr_0_0.v:58] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 459.797 ; gain = 151.035 --------------------------------------------------------------------------------- RTL Elaboration failed INFO: [Common 17-83] Releasing license: Synthesis 3 Infos, 1 Warnings, 0 Critical Warnings and 3 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details INFO: [Common 17-206] Exiting Vivado at Wed Sep 12 06:43:35 2018...