`timescale 1ns / 1ps module UART_tx #(parameter clk_per_bit = 1736) (clk_in, data_in, Rx_ready, Tx_ready, Serial_Tx, Tx_done); input clk_in, Rx_ready; output Tx_ready, Serial_Tx, Tx_done; input [7:0]data_in; reg Tx_ready, Serial_Tx, Tx_done; reg [3:0]index; reg [7:0]data_reg; reg [11:0]clk_counter; reg [1:0]sel_state; parameter Idle = 2'b00; parameter Start_bit = 2'b01; parameter Data_in = 2'b10; parameter Stop_bit = 2'b11; initial begin Tx_ready <= 0; Serial_Tx <= 1; Tx_done <= 0; data_reg <= 8'd0; clk_counter <= 8'd0; index <= 4'd0; end always @(posedge clk_in) begin case(sel_state) Idle: begin Serial_Tx <= 1; Tx_done <= 0; clk_counter <= 8'd0; if(Rx_ready) begin Tx_ready <= 1'b1; data_reg <= data_in; sel_state <= Start_bit; end else sel_state <= Idle; end Start_bit: begin Serial_Tx <= 0; if(clk_counter < clk_per_bit - 1) begin clk_counter <= clk_counter + 1; sel_state <= Start_bit; end else begin clk_counter <= 0; sel_state <= Data_in; end end Data_in: begin Serial_Tx <= data_reg[index]; if(clk_counter < clk_per_bit - 1) begin clk_counter <= clk_counter + 1; sel_state <= Data_in; end else begin clk_counter <= 0; if(index < 8) begin index <= index + 1; sel_state <= Data_in; end else begin index <= 0; sel_state <= Stop_bit; end end end Stop_bit: begin Serial_Tx <= 1'b1; if(clk_counter < clk_per_bit - 1) begin clk_counter <= clk_counter + 1; sel_state <= Stop_bit; end else begin Tx_done <= 1'b1; clk_counter <= 0; Tx_ready <= 0; sel_state <= Idle; end end default: sel_state <= Idle; endcase end endmodule