library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pattern_genrator is
    Port ( x : in  STD_LOGIC_VECTOR (1 downto 0);
           clk: in std_logic;
			  rst : in  STD_LOGIC;
           a1,b1,c1,d1,e1,f1,g1:out std_logic);
end pattern_genrator;

architecture Behavioral of pattern_genrator is
type state is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal pr_state,nxt_state:state;
signal count: integer:=1;
signal tmp : std_logic := '0';
signal clk_out:std_logic;
begin

process(clk,rst) ---------------CLOCK DIVIDER
begin
if(rst='1') then
count<=1;
tmp<='0';
elsif(clk'event and clk='1') then
count <=count+1;
if (count = 100000000) then
tmp <= NOT tmp;
count <= 1;
end if;
clk_out <= tmp;
end if;
end process;
		 
-- Sequential logic
process(clk_out,rst)
begin
 if(rst='1') then
  pr_state <= s0;
 elsif(clk_out'event and clk_out = '1') then
  pr_state <= nxt_state;
 end if;
end process;
	
--combinational logic	
process(x,pr_state)
begin
	case pr_state is
      when s0=>
        a1<='0';b1<='0';c1<='1';d1<='1';e1<='1';f1<='1';g1<='1';--ab 
        if(x="01")then
          nxt_state<=s1;
        elsif(x="10")then
          nxt_state<=s5;
        else nxt_state<=s9;
        end if;

      when s1=>
        a1<='1';b1<='0';c1<='0';d1<='1';e1<='1';f1<='1';g1<='1';--bc
        if(x="01")then
          nxt_state<=s2;
        elsif(x="10")then
          nxt_state<=s0;
        end if;

      when s2=>
        a1<='1';b1<='1';c1<='0';d1<='0';e1<='1';f1<='1';g1<='1';--cd
        if(x="01")then
          nxt_state<=s3;
        elsif(x="10")then
          nxt_state<=s1;
        else nxt_state<=s8;
        end if;

      when s3=>
        a1<='1';b1<='1';c1<='1';d1<='0';e1<='0';f1<='1';g1<='1';--de
        if(x="01")then
          nxt_state<=s4;
        elsif(x="10")then
          nxt_state<=s2;
        else nxt_state<=s2;
        end if;

      when s4=>
        a1<='1';b1<='1';c1<='1';d1<='1';e1<='0';f1<='0';g1<='1';--ef
        if(x="01")then
          nxt_state<=s5;
        elsif(x="10")then
          nxt_state<=s3;
        end if;

      when s5=>
        a1<='0';b1<='1';c1<='1';d1<='1';e1<='1';f1<='0';g1<='1';--af
        if(x="01")then
          nxt_state<=s0;
        elsif(x="10")then
          nxt_state<=s4;
        else nxt_state<=s0;
        end if;
		  
      when s6=>
         a1<='1';b1<='1';c1<='1';d1<='1';e1<='0';f1<='1';g1<='0';--eg
           nxt_state<=s3;
			  
      when s7=>
          a1<='1';b1<='1';c1<='1';d1<='1';e1<='1';f1<='0';g1<='0';--fg
            nxt_state<=s5;
				
      when s8=>
		    a1<='1';b1<='1';c1<='0';d1<='1';e1<='1';f1<='1';g1<='0';--cg
			   nxt_state<=s7;
				
		when s9=>
          a1<='1';b1<='0';c1<='1';d1<='1';e1<='1';f1<='1';g1<='0';--bg
            nxt_state<=s6;

end case;
end process;				
end Behavioral;