start_gui cd D:/Users/paul/Documents/xilinx/Arty-master/Projects/BSD/proj source ./create_project.tcl # if {[info exists ::create_path]} { # set dest_dir $::create_path # } else { # set dest_dir [pwd] # } # puts "INFO: Creating new project in $dest_dir" INFO: Creating new project in D:/Users/paul/Documents/xilinx/Arty-master/Projects/BSD/proj # set proj_name "bsd" # set origin_dir ".." # set orig_proj_dir "[file normalize "$origin_dir/proj"]" # set src_dir $origin_dir/src # set repo_dir $origin_dir/repo # create_project $proj_name $dest_dir INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Software/Xilinx/Vivado/2015.3/data/ip'. # set proj_dir [get_property directory [current_project]] # set obj [get_projects $proj_name] # set_property "default_lib" "xil_defaultlib" $obj # set_property "board_part" "digilentinc.com:arty:part0:1.1" $obj WARNING: [Project 1-153] The current project part 'xc7vx485tffg1157-1' does not match with the 'DIGILENTINC.COM:ARTY:PART0:1.1' board part settings. The project part will be reset to 'DIGILENTINC.COM:ARTY:PART0:1.1' board part. INFO: [Project 1-152] Project part set to artix7 (xc7a35ticsg324-1l) # set_property "simulator_language" "Mixed" $obj # set_property "target_language" "VHDL" $obj # if {[string equal [get_filesets -quiet sources_1] ""]} { # create_fileset -srcset sources_1 # } # if {[string equal [get_filesets -quiet constrs_1] ""]} { # create_fileset -constrset constrs_1 # } # set obj [get_filesets sources_1] # set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj # add_files -quiet $src_dir/hdl # add_files -quiet [glob -nocomplain ../src/ip/*.xci] # add_files -fileset constrs_1 -quiet $src_dir/constraints # update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/Users/paul/Documents/xilinx/Arty-master/Projects/BSD/repo'; Can't find the specified path. If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. # if {[string equal [get_runs -quiet synth_1] ""]} { # create_run -name synth_1 -board_part "digilentinc.com:arty:part0:1.1" -flow {Vivado Synthesis 2015} -strategy "Flow_PerfOptimized_High" -constrset constrs_1 # } else { # set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1] # set_property flow "Vivado Synthesis 2015" [get_runs synth_1] # } # set obj [get_runs synth_1] # set_property "part" "xc7a35ticsg324-1L" $obj # set_property "steps.synth_design.args.fanout_limit" "400" $obj # set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj # set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj # set_property "steps.synth_design.args.resource_sharing" "off" $obj # set_property "steps.synth_design.args.no_lc" "1" $obj # set_property "steps.synth_design.args.shreg_min_size" "5" $obj # current_run -synthesis [get_runs synth_1] # if {[string equal [get_runs -quiet impl_1] ""]} { # create_run -name impl_1 -board_part "digilentinc.com:arty:part0:1.1" -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 # } else { # set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] # set_property flow "Vivado Implementation 2015" [get_runs impl_1] # } # set obj [get_runs impl_1] # set_property "part" "xc7a35ticsg324-1L" $obj # set_property "steps.write_bitstream.args.bin_file" "1" $obj # current_run -implementation [get_runs impl_1] # puts "INFO: Project created:$proj_name" INFO: Project created:bsd # source $origin_dir/src/bd/system.tcl ## set scripts_vivado_version 2015.3 ## set current_vivado_version [version -short] ## if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { ## puts "" ## puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script." ## ## return 1 ## } ## if { [get_projects -quiet] eq "" } { ## puts "ERROR: Please open or create a project!" ## return 1 ## } ## set design_name system ## set errMsg "" ## set nRet 0 ## set cur_design [current_bd_design -quiet] ## set list_cells [get_bd_cells -quiet] ## if { ${design_name} eq "" } { ## # USE CASES: ## # 1) Design_name not set ## ## set errMsg "ERROR: Please set the variable to a non-empty value." ## set nRet 1 ## ## } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { ## # USE CASES: ## # 2): Current design opened AND is empty AND names same. ## # 3): Current design opened AND is empty AND names diff; design_name NOT in project. ## # 4): Current design opened AND is empty AND names diff; design_name exists in project. ## ## if { $cur_design ne $design_name } { ## puts "INFO: Changing value of from <$design_name> to <$cur_design> since current design is empty." ## set design_name [get_property NAME $cur_design] ## } ## puts "INFO: Constructing design in IPI design <$cur_design>..." ## ## } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { ## # USE CASES: ## # 5) Current design opened AND has components AND same names. ## ## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." ## set nRet 1 ## } elseif { [get_files -quiet ${design_name}.bd] ne "" } { ## # USE CASES: ## # 6) Current opened design, has components, but diff names, design_name exists in project. ## # 7) No opened design, design_name exists in project. ## ## set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." ## set nRet 2 ## ## } else { ## # USE CASES: ## # 8) No opened design, design_name not in project. ## # 9) Current opened design, has components, but diff names, design_name not in project. ## ## puts "INFO: Currently there is no design <$design_name> in project, so creating one..." ## ## create_bd_design $design_name ## ## puts "INFO: Making design <$design_name> as current_bd_design." ## current_bd_design $design_name ## ## } INFO: Currently there is no design in project, so creating one... Wrote : INFO: Making design as current_bd_design. ## puts "INFO: Currently the variable is equal to \"$design_name\"." INFO: Currently the variable is equal to "system". ## if { $nRet != 0 } { ## puts $errMsg ## return $nRet ## } ## proc write_mig_file_system_mig_7series_0_0 { str_mig_prj_filepath } { ## ## set mig_prj_file [open $str_mig_prj_filepath w+] ## ## puts $mig_prj_file {} ## puts $mig_prj_file {} ## puts $mig_prj_file {} ## puts $mig_prj_file { system_mig_7series_0_1} ## puts $mig_prj_file { 1} ## puts $mig_prj_file { 1} ## puts $mig_prj_file { OFF} ## puts $mig_prj_file { 1024} ## puts $mig_prj_file { ON} ## puts $mig_prj_file { Disabled} ## puts $mig_prj_file { xc7a35ti-csg324/-1L} ## puts $mig_prj_file { 2.4} ## puts $mig_prj_file { No Buffer} ## puts $mig_prj_file { No Buffer} ## puts $mig_prj_file { ACTIVE LOW} ## puts $mig_prj_file { FALSE} ## puts $mig_prj_file { 1} ## puts $mig_prj_file { 50 Ohms} ## puts $mig_prj_file { 0} ## puts $mig_prj_file { } ## puts $mig_prj_file { DDR3_SDRAM/Components/MT41K128M16XX-15E} ## puts $mig_prj_file { 3000} ## puts $mig_prj_file { 1.8V} ## puts $mig_prj_file { 4:1} ## puts $mig_prj_file { 166.666} ## puts $mig_prj_file { 0} ## puts $mig_prj_file { 666} ## puts $mig_prj_file { 1.000} ## puts $mig_prj_file { 1} ## puts $mig_prj_file { 1} ## puts $mig_prj_file { 1} ## puts $mig_prj_file { 1} ## puts $mig_prj_file { 16} ## puts $mig_prj_file { 1} ## puts $mig_prj_file { 1} ## puts $mig_prj_file { Disabled} ## puts $mig_prj_file { Normal} ## puts $mig_prj_file { FALSE} ## puts $mig_prj_file { } ## puts $mig_prj_file { 14} ## puts $mig_prj_file { 10} ## puts $mig_prj_file { 3} ## puts $mig_prj_file { 1.35V} ## puts $mig_prj_file { 268435456} ## puts $mig_prj_file { BANK_ROW_COLUMN} ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file { 8 - Fixed} ## puts $mig_prj_file { Sequential} ## puts $mig_prj_file { 5} ## puts $mig_prj_file { Normal} ## puts $mig_prj_file { No} ## puts $mig_prj_file { Slow Exit} ## puts $mig_prj_file { Enable} ## puts $mig_prj_file { RZQ/6} ## puts $mig_prj_file { Disable} ## puts $mig_prj_file { Enable} ## puts $mig_prj_file { RZQ/6} ## puts $mig_prj_file { 0} ## puts $mig_prj_file { Disabled} ## puts $mig_prj_file { Enabled} ## puts $mig_prj_file { Output Buffer Enabled} ## puts $mig_prj_file { Full Array} ## puts $mig_prj_file { 5} ## puts $mig_prj_file { Enabled} ## puts $mig_prj_file { Normal} ## puts $mig_prj_file { Dynamic ODT off} ## puts $mig_prj_file { AXI} ## puts $mig_prj_file { } ## puts $mig_prj_file { RD_PRI_REG} ## puts $mig_prj_file { 28} ## puts $mig_prj_file { 128} ## puts $mig_prj_file { 1} ## puts $mig_prj_file { 0} ## puts $mig_prj_file { } ## puts $mig_prj_file { } ## puts $mig_prj_file {} ## ## close $mig_prj_file ## } ## proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } { ## ## if { $parentCell eq "" || $nameHier eq "" } { ## puts "ERROR: create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!" ## return ## } ## ## # Get object for parentCell ## set parentObj [get_bd_cells $parentCell] ## if { $parentObj == "" } { ## puts "ERROR: Unable to find parent cell <$parentCell>!" ## return ## } ## ## # Make sure parentObj is hier blk ## set parentType [get_property TYPE $parentObj] ## if { $parentType ne "hier" } { ## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." ## return ## } ## ## # Save current instance; Restore later ## set oldCurInst [current_bd_instance .] ## ## # Set parent object as current ## current_bd_instance $parentObj ## ## # Create cell and set as current instance ## set hier_obj [create_bd_cell -type hier $nameHier] ## current_bd_instance $hier_obj ## ## # Create interface pins ## create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB ## create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB ## ## # Create pins ## create_bd_pin -dir I -type clk LMB_Clk ## create_bd_pin -dir I -from 0 -to 0 -type rst SYS_Rst ## ## # Create instance: dlmb_bram_if_cntlr, and set properties ## set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ] ## set_property -dict [ list \ ## CONFIG.C_ECC {0} \ ## ] $dlmb_bram_if_cntlr ## ## # Create instance: dlmb_v10, and set properties ## set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ] ## ## # Create instance: ilmb_bram_if_cntlr, and set properties ## set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ] ## set_property -dict [ list \ ## CONFIG.C_ECC {0} \ ## ] $ilmb_bram_if_cntlr ## ## # Create instance: ilmb_v10, and set properties ## set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ] ## ## # Create instance: lmb_bram, and set properties ## set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 lmb_bram ] ## set_property -dict [ list \ ## CONFIG.Memory_Type {True_Dual_Port_RAM} \ ## CONFIG.use_bram_block {BRAM_Controller} \ ## ] $lmb_bram ## ## # Create interface connections ## connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M] ## connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0] ## connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA] ## connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M] ## connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0] ## connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB] ## ## # Create port connections ## connect_bd_net -net SYS_Rst_1 [get_bd_pins SYS_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst] ## connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk] ## ## # Restore current instance ## current_bd_instance $oldCurInst ## } ## proc create_root_design { parentCell } { ## ## if { $parentCell eq "" } { ## set parentCell [get_bd_cells /] ## } ## ## # Get object for parentCell ## set parentObj [get_bd_cells $parentCell] ## if { $parentObj == "" } { ## puts "ERROR: Unable to find parent cell <$parentCell>!" ## return ## } ## ## # Make sure parentObj is hier blk ## set parentType [get_property TYPE $parentObj] ## if { $parentType ne "hier" } { ## puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." ## return ## } ## ## # Save current instance; Restore later ## set oldCurInst [current_bd_instance .] ## ## # Set parent object as current ## current_bd_instance $parentObj ## ## ## # Create interface ports ## set DDR3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3 ] ## set Vaux0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 ] ## set Vaux1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1 ] ## set Vaux2 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux2 ] ## set Vaux4 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux4 ] ## set Vaux5 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux5 ] ## set Vaux6 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux6 ] ## set Vaux7 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux7 ] ## set Vaux9 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux9 ] ## set Vaux10 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux10 ] ## set Vaux12 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux12 ] ## set Vaux13 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux13 ] ## set Vaux14 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux14 ] ## set Vaux15 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux15 ] ## set Vp_Vn [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn ] ## set dip_switches_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 dip_switches_4bits ] ## set eth_mdio_mdc [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 eth_mdio_mdc ] ## set eth_mii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mii_rtl:1.0 eth_mii ] ## set i2c [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 i2c ] ## set i2c_pullups [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 i2c_pullups ] ## set led_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 led_4bits ] ## set push_buttons_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 push_buttons_4bits ] ## set qspi_flash [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 qspi_flash ] ## set rgb_led [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 rgb_led ] ## set shield_dp0_dp19 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 shield_dp0_dp19 ] ## set shield_dp26_dp41 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 shield_dp26_dp41 ] ## set spi [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 spi ] ## set usb_uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 usb_uart ] ## ## # Create ports ## set eth_ref_clk [ create_bd_port -dir O -type clk eth_ref_clk ] ## set reset [ create_bd_port -dir I -type rst reset ] ## set_property -dict [ list \ ## CONFIG.POLARITY {ACTIVE_LOW} \ ## ] $reset ## set sys_clock [ create_bd_port -dir I -type clk sys_clock ] ## set_property -dict [ list \ ## CONFIG.FREQ_HZ {100000000} \ ## CONFIG.PHASE {0.000} \ ## ] $sys_clock ## ## # Create instance: axi_ethernetlite_0, and set properties ## set axi_ethernetlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernetlite:3.0 axi_ethernetlite_0 ] ## set_property -dict [ list \ ## CONFIG.MDIO_BOARD_INTERFACE {eth_mdio_mdc} \ ## CONFIG.MII_BOARD_INTERFACE {eth_mii} \ ## CONFIG.USE_BOARD_FLOW {true} \ ## ] $axi_ethernetlite_0 ## ## # Create instance: axi_gpio_0, and set properties ## set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] ## set_property -dict [ list \ ## CONFIG.C_GPIO_WIDTH {20} \ ## CONFIG.C_INTERRUPT_PRESENT {1} \ ## CONFIG.GPIO_BOARD_INTERFACE {shield_dp0_dp19} \ ## CONFIG.USE_BOARD_FLOW {true} \ ## ] $axi_gpio_0 ## ## # Create instance: axi_gpio_1, and set properties ## set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ] ## set_property -dict [ list \ ## CONFIG.C_GPIO_WIDTH {16} \ ## CONFIG.C_INTERRUPT_PRESENT {1} \ ## CONFIG.GPIO_BOARD_INTERFACE {shield_dp26_dp41} \ ## CONFIG.USE_BOARD_FLOW {true} \ ## ] $axi_gpio_1 ## ## # Create instance: axi_gpio_led, and set properties ## set axi_gpio_led [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_led ] ## set_property -dict [ list \ ## CONFIG.C_ALL_OUTPUTS {1} \ ## CONFIG.C_ALL_OUTPUTS_2 {1} \ ## CONFIG.C_GPIO2_WIDTH {12} \ ## CONFIG.C_GPIO_WIDTH {4} \ ## CONFIG.C_IS_DUAL {1} \ ## CONFIG.GPIO2_BOARD_INTERFACE {rgb_led} \ ## CONFIG.GPIO_BOARD_INTERFACE {led_4bits} \ ## CONFIG.USE_BOARD_FLOW {true} \ ## ] $axi_gpio_led ## ## # Create instance: axi_gpio_pullup, and set properties ## set axi_gpio_pullup [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_pullup ] ## set_property -dict [ list \ ## CONFIG.C_ALL_OUTPUTS {1} \ ## CONFIG.C_GPIO_WIDTH {2} \ ## CONFIG.GPIO_BOARD_INTERFACE {i2c_pullups} \ ## CONFIG.USE_BOARD_FLOW {true} \ ## ] $axi_gpio_pullup ## ## # Create instance: axi_gpio_sw, and set properties ## set axi_gpio_sw [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_sw ] ## set_property -dict [ list \ ## CONFIG.C_ALL_INPUTS {1} \ ## CONFIG.C_ALL_INPUTS_2 {1} \ ## CONFIG.C_GPIO2_WIDTH {4} \ ## CONFIG.C_GPIO_WIDTH {4} \ ## CONFIG.C_INTERRUPT_PRESENT {1} \ ## CONFIG.C_IS_DUAL {1} \ ## CONFIG.GPIO2_BOARD_INTERFACE {push_buttons_4bits} \ ## CONFIG.GPIO_BOARD_INTERFACE {dip_switches_4bits} \ ## CONFIG.USE_BOARD_FLOW {true} \ ## ] $axi_gpio_sw ## ## # Create instance: axi_iic_0, and set properties ## set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ] ## set_property -dict [ list \ ## CONFIG.IIC_BOARD_INTERFACE {i2c} \ ## CONFIG.USE_BOARD_FLOW {true} \ ## ] $axi_iic_0 ## ## # Create instance: axi_mem_intercon, and set properties ## set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ] ## set_property -dict [ list \ ## CONFIG.NUM_MI {1} \ ## CONFIG.NUM_SI {2} \ ## ] $axi_mem_intercon ## ## # Create instance: axi_quad_spi_flash, and set properties ## set axi_quad_spi_flash [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_quad_spi_flash ] ## set_property -dict [ list \ ## CONFIG.C_SCK_RATIO {2} \ ## CONFIG.C_SPI_MEMORY {1} \ ## CONFIG.C_SPI_MODE {2} \ ## CONFIG.C_TYPE_OF_AXI4_INTERFACE {0} \ ## CONFIG.C_USE_STARTUP {0} \ ## CONFIG.C_USE_STARTUP_INT {0} \ ## CONFIG.QSPI_BOARD_INTERFACE {qspi_flash} \ ## CONFIG.USE_BOARD_FLOW {true} \ ## ] $axi_quad_spi_flash ## ## # Create instance: axi_quad_spi_shield, and set properties ## set axi_quad_spi_shield [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_quad_spi_shield ] ## set_property -dict [ list \ ## CONFIG.C_USE_STARTUP {0} \ ## CONFIG.C_USE_STARTUP_INT {0} \ ## CONFIG.QSPI_BOARD_INTERFACE {spi} \ ## CONFIG.USE_BOARD_FLOW {true} \ ## ] $axi_quad_spi_shield ## ## # Create instance: axi_timer_0, and set properties ## set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ] ## ## # Create instance: axi_uartlite_0, and set properties ## set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ] ## set_property -dict [ list \ ## CONFIG.UARTLITE_BOARD_INTERFACE {usb_uart} \ ## CONFIG.USE_BOARD_FLOW {true} \ ## ] $axi_uartlite_0 ## ## # Create instance: clk_wiz_1, and set properties ## set clk_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 clk_wiz_1 ] ## set_property -dict [ list \ ## CONFIG.CLKOUT2_JITTER {118.758} \ ## CONFIG.CLKOUT2_PHASE_ERROR {98.575} \ ## CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {166.667} \ ## CONFIG.CLKOUT2_USED {true} \ ## CONFIG.CLKOUT3_JITTER {114.829} \ ## CONFIG.CLKOUT3_PHASE_ERROR {98.575} \ ## CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {200.000} \ ## CONFIG.CLKOUT3_USED {true} \ ## CONFIG.CLKOUT4_JITTER {175.402} \ ## CONFIG.CLKOUT4_PHASE_ERROR {98.575} \ ## CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25.000} \ ## CONFIG.CLKOUT4_USED {true} \ ## CONFIG.CLK_IN1_BOARD_INTERFACE {sys_clock} \ ## CONFIG.MMCM_CLKIN1_PERIOD {10.0} \ ## CONFIG.MMCM_CLKOUT1_DIVIDE {6} \ ## CONFIG.MMCM_CLKOUT2_DIVIDE {5} \ ## CONFIG.MMCM_CLKOUT3_DIVIDE {40} \ ## CONFIG.MMCM_DIVCLK_DIVIDE {1} \ ## CONFIG.NUM_OUT_CLKS {4} \ ## CONFIG.PRIM_SOURCE {Single_ended_clock_capable_pin} \ ## CONFIG.RESET_BOARD_INTERFACE {reset} \ ## CONFIG.RESET_PORT {resetn} \ ## CONFIG.RESET_TYPE {ACTIVE_LOW} \ ## CONFIG.USE_BOARD_FLOW {true} \ ## ] $clk_wiz_1 ## ## # Create instance: mdm_1, and set properties ## set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ] ## ## # Create instance: microblaze_0, and set properties ## set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 microblaze_0 ] ## set_property -dict [ list \ ## CONFIG.C_CACHE_BYTE_SIZE {16384} \ ## CONFIG.C_DCACHE_BYTE_SIZE {16384} \ ## CONFIG.C_DEBUG_ENABLED {1} \ ## CONFIG.C_D_AXI {1} \ ## CONFIG.C_D_LMB {1} \ ## CONFIG.C_I_LMB {1} \ ## CONFIG.C_USE_DCACHE {1} \ ## CONFIG.C_USE_ICACHE {1} \ ## ] $microblaze_0 ## ## # Create instance: microblaze_0_axi_intc, and set properties ## set microblaze_0_axi_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 microblaze_0_axi_intc ] ## set_property -dict [ list \ ## CONFIG.C_HAS_FAST {1} \ ## ] $microblaze_0_axi_intc ## ## # Create instance: microblaze_0_axi_periph, and set properties ## set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ] ## set_property -dict [ list \ ## CONFIG.NUM_MI {14} \ ## ] $microblaze_0_axi_periph ## ## # Create instance: microblaze_0_local_memory ## create_hier_cell_microblaze_0_local_memory [current_bd_instance .] microblaze_0_local_memory ## ## # Create instance: microblaze_0_xlconcat, and set properties ## set microblaze_0_xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 microblaze_0_xlconcat ] ## set_property -dict [ list \ ## CONFIG.NUM_PORTS {7} \ ## ] $microblaze_0_xlconcat ## ## # Create instance: mig_7series_0, and set properties ## set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 mig_7series_0 ] ## ## # Generate the PRJ File for MIG ## set str_mig_folder [get_property IP_DIR [ get_ips [ get_property CONFIG.Component_Name $mig_7series_0 ] ] ] ## set str_mig_file_name mig_a.prj ## set str_mig_file_path ${str_mig_folder}/${str_mig_file_name} ## ## write_mig_file_system_mig_7series_0_0 $str_mig_file_path ## ## set_property -dict [ list \ ## CONFIG.BOARD_MIG_PARAM {Custom} \ ## CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \ ## CONFIG.RESET_BOARD_INTERFACE {reset} \ ## CONFIG.XML_INPUT_FILE {mig_a.prj} \ ## ] $mig_7series_0 ## ## # Create instance: rst_clk_wiz_1_100M, and set properties ## set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ] ## set_property -dict [ list \ ## CONFIG.RESET_BOARD_INTERFACE {reset} \ ## CONFIG.USE_BOARD_FLOW {true} \ ## ] $rst_clk_wiz_1_100M ## ## # Create instance: rst_mig_7series_0_83M, and set properties ## set rst_mig_7series_0_83M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_mig_7series_0_83M ] ## ## # Create instance: xadc_wiz_0, and set properties ## set xadc_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.2 xadc_wiz_0 ] ## set_property -dict [ list \ ## CONFIG.CHANNEL_ENABLE_TEMPERATURE {true} \ ## CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} \ ## CONFIG.CHANNEL_ENABLE_VAUXP10_VAUXN10 {true} \ ## CONFIG.CHANNEL_ENABLE_VAUXP11_VAUXN11 {false} \ ## CONFIG.CHANNEL_ENABLE_VAUXP12_VAUXN12 {true} \ ## CONFIG.CHANNEL_ENABLE_VAUXP13_VAUXN13 {true} \ ## CONFIG.CHANNEL_ENABLE_VAUXP14_VAUXN14 {true} \ ## CONFIG.CHANNEL_ENABLE_VAUXP15_VAUXN15 {true} \ ## CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 {true} \ ## CONFIG.CHANNEL_ENABLE_VAUXP2_VAUXN2 {true} \ ## CONFIG.CHANNEL_ENABLE_VAUXP4_VAUXN4 {true} \ ## CONFIG.CHANNEL_ENABLE_VAUXP5_VAUXN5 {true} \ ## CONFIG.CHANNEL_ENABLE_VAUXP6_VAUXN6 {true} \ ## CONFIG.CHANNEL_ENABLE_VAUXP7_VAUXN7 {true} \ ## CONFIG.CHANNEL_ENABLE_VAUXP9_VAUXN9 {true} \ ## CONFIG.CHANNEL_ENABLE_VP_VN {true} \ ## CONFIG.ENABLE_RESET {false} \ ## CONFIG.ENABLE_TEMP_BUS {true} \ ## CONFIG.EXTERNAL_MUX_CHANNEL {VP_VN} \ ## CONFIG.INTERFACE_SELECTION {Enable_AXI} \ ## CONFIG.OT_ALARM {false} \ ## CONFIG.SEQUENCER_MODE {Continuous} \ ## CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} \ ## CONFIG.USER_TEMP_ALARM {true} \ ## CONFIG.VCCAUX_ALARM {true} \ ## CONFIG.VCCINT_ALARM {true} \ ## CONFIG.VCCINT_ALARM_LOWER {0.95} \ ## CONFIG.VCCINT_ALARM_UPPER {0.98} \ ## CONFIG.XADC_STARUP_SELECTION {channel_sequencer} \ ## ] $xadc_wiz_0 ## ## # Create interface connections ## connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_ports Vaux0] [get_bd_intf_pins xadc_wiz_0/Vaux0] ## connect_bd_intf_net -intf_net Vaux10_1 [get_bd_intf_ports Vaux10] [get_bd_intf_pins xadc_wiz_0/Vaux10] ## connect_bd_intf_net -intf_net Vaux12_1 [get_bd_intf_ports Vaux12] [get_bd_intf_pins xadc_wiz_0/Vaux12] ## connect_bd_intf_net -intf_net Vaux13_1 [get_bd_intf_ports Vaux13] [get_bd_intf_pins xadc_wiz_0/Vaux13] ## connect_bd_intf_net -intf_net Vaux14_1 [get_bd_intf_ports Vaux14] [get_bd_intf_pins xadc_wiz_0/Vaux14] ## connect_bd_intf_net -intf_net Vaux15_1 [get_bd_intf_ports Vaux15] [get_bd_intf_pins xadc_wiz_0/Vaux15] ## connect_bd_intf_net -intf_net Vaux1_1 [get_bd_intf_ports Vaux1] [get_bd_intf_pins xadc_wiz_0/Vaux1] ## connect_bd_intf_net -intf_net Vaux2_1 [get_bd_intf_ports Vaux2] [get_bd_intf_pins xadc_wiz_0/Vaux2] ## connect_bd_intf_net -intf_net Vaux4_1 [get_bd_intf_ports Vaux4] [get_bd_intf_pins xadc_wiz_0/Vaux4] ## connect_bd_intf_net -intf_net Vaux5_1 [get_bd_intf_ports Vaux5] [get_bd_intf_pins xadc_wiz_0/Vaux5] ## connect_bd_intf_net -intf_net Vaux6_1 [get_bd_intf_ports Vaux6] [get_bd_intf_pins xadc_wiz_0/Vaux6] ## connect_bd_intf_net -intf_net Vaux7_1 [get_bd_intf_ports Vaux7] [get_bd_intf_pins xadc_wiz_0/Vaux7] ## connect_bd_intf_net -intf_net Vaux9_1 [get_bd_intf_ports Vaux9] [get_bd_intf_pins xadc_wiz_0/Vaux9] ## connect_bd_intf_net -intf_net Vp_Vn_1 [get_bd_intf_ports Vp_Vn] [get_bd_intf_pins xadc_wiz_0/Vp_Vn] ## connect_bd_intf_net -intf_net axi_ethernetlite_0_MDIO [get_bd_intf_ports eth_mdio_mdc] [get_bd_intf_pins axi_ethernetlite_0/MDIO] ## connect_bd_intf_net -intf_net axi_ethernetlite_0_MII [get_bd_intf_ports eth_mii] [get_bd_intf_pins axi_ethernetlite_0/MII] ## connect_bd_intf_net -intf_net axi_gpio_0_GPIO2 [get_bd_intf_ports shield_dp0_dp19] [get_bd_intf_pins axi_gpio_0/GPIO] ## connect_bd_intf_net -intf_net axi_gpio_1_GPIO1 [get_bd_intf_ports shield_dp26_dp41] [get_bd_intf_pins axi_gpio_1/GPIO] ## connect_bd_intf_net -intf_net axi_gpio_2_GPIO [get_bd_intf_ports led_4bits] [get_bd_intf_pins axi_gpio_led/GPIO] ## connect_bd_intf_net -intf_net axi_gpio_2_GPIO2 [get_bd_intf_ports rgb_led] [get_bd_intf_pins axi_gpio_led/GPIO2] ## connect_bd_intf_net -intf_net axi_gpio_pullup_GPIO [get_bd_intf_ports i2c_pullups] [get_bd_intf_pins axi_gpio_pullup/GPIO] ## connect_bd_intf_net -intf_net axi_gpio_sw_GPIO [get_bd_intf_ports dip_switches_4bits] [get_bd_intf_pins axi_gpio_sw/GPIO] ## connect_bd_intf_net -intf_net axi_gpio_sw_GPIO2 [get_bd_intf_ports push_buttons_4bits] [get_bd_intf_pins axi_gpio_sw/GPIO2] ## connect_bd_intf_net -intf_net axi_iic_0_IIC [get_bd_intf_ports i2c] [get_bd_intf_pins axi_iic_0/IIC] ## connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins mig_7series_0/S_AXI] ## connect_bd_intf_net -intf_net axi_quad_spi_0_SPI_0 [get_bd_intf_ports spi] [get_bd_intf_pins axi_quad_spi_shield/SPI_0] ## connect_bd_intf_net -intf_net axi_quad_spi_1_SPI_0 [get_bd_intf_ports qspi_flash] [get_bd_intf_pins axi_quad_spi_flash/SPI_0] ## connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_ports usb_uart] [get_bd_intf_pins axi_uartlite_0/UART] ## connect_bd_intf_net -intf_net microblaze_0_M_AXI_DC [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins microblaze_0/M_AXI_DC] ## connect_bd_intf_net -intf_net microblaze_0_M_AXI_IC [get_bd_intf_pins axi_mem_intercon/S01_AXI] [get_bd_intf_pins microblaze_0/M_AXI_IC] ## connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI] ## connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins axi_ethernetlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI] ## connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI] ## connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI] ## connect_bd_intf_net -intf_net microblaze_0_axi_periph_M04_AXI [get_bd_intf_pins axi_quad_spi_shield/AXI_LITE] [get_bd_intf_pins microblaze_0_axi_periph/M04_AXI] ## connect_bd_intf_net -intf_net microblaze_0_axi_periph_M05_AXI [get_bd_intf_pins axi_quad_spi_flash/AXI_LITE] [get_bd_intf_pins microblaze_0_axi_periph/M05_AXI] ## connect_bd_intf_net -intf_net microblaze_0_axi_periph_M06_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M06_AXI] ## connect_bd_intf_net -intf_net microblaze_0_axi_periph_M07_AXI [get_bd_intf_pins axi_gpio_sw/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M07_AXI] ## connect_bd_intf_net -intf_net microblaze_0_axi_periph_M08_AXI [get_bd_intf_pins axi_gpio_led/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M08_AXI] ## connect_bd_intf_net -intf_net microblaze_0_axi_periph_M09_AXI [get_bd_intf_pins axi_gpio_pullup/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M09_AXI] ## connect_bd_intf_net -intf_net microblaze_0_axi_periph_M11_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M11_AXI] ## connect_bd_intf_net -intf_net microblaze_0_axi_periph_M12_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M12_AXI] ## connect_bd_intf_net -intf_net microblaze_0_axi_periph_M13_AXI [get_bd_intf_pins microblaze_0_axi_periph/M13_AXI] [get_bd_intf_pins xadc_wiz_0/s_axi_lite] ## connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG] ## connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB] ## connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB] ## connect_bd_intf_net -intf_net microblaze_0_intc_axi [get_bd_intf_pins microblaze_0_axi_intc/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI] ## connect_bd_intf_net -intf_net microblaze_0_interrupt [get_bd_intf_pins microblaze_0/INTERRUPT] [get_bd_intf_pins microblaze_0_axi_intc/interrupt] ## connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins mig_7series_0/DDR3] ## ## # Create port connections ## connect_bd_net -net axi_ethernetlite_0_ip2intc_irpt [get_bd_pins axi_ethernetlite_0/ip2intc_irpt] [get_bd_pins microblaze_0_xlconcat/In1] ## connect_bd_net -net axi_gpio_sw_ip2intc_irpt [get_bd_pins axi_gpio_sw/ip2intc_irpt] [get_bd_pins microblaze_0_xlconcat/In3] ## connect_bd_net -net axi_iic_0_iic2intc_irpt [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins microblaze_0_xlconcat/In2] ## connect_bd_net -net axi_quad_spi_flash_ip2intc_irpt [get_bd_pins axi_quad_spi_flash/ip2intc_irpt] [get_bd_pins microblaze_0_xlconcat/In4] ## connect_bd_net -net axi_quad_spi_shield_ip2intc_irpt [get_bd_pins axi_quad_spi_shield/ip2intc_irpt] [get_bd_pins microblaze_0_xlconcat/In5] ## connect_bd_net -net axi_timer_0_interrupt [get_bd_pins axi_timer_0/interrupt] [get_bd_pins microblaze_0_xlconcat/In0] ## connect_bd_net -net clk_wiz_1_clk_out2 [get_bd_pins clk_wiz_1/clk_out2] [get_bd_pins mig_7series_0/sys_clk_i] ## connect_bd_net -net clk_wiz_1_clk_out3 [get_bd_pins clk_wiz_1/clk_out3] [get_bd_pins mig_7series_0/clk_ref_i] ## connect_bd_net -net clk_wiz_1_clk_out4 [get_bd_ports eth_ref_clk] [get_bd_pins clk_wiz_1/clk_out4] ## connect_bd_net -net clk_wiz_1_locked [get_bd_pins clk_wiz_1/locked] [get_bd_pins rst_clk_wiz_1_100M/dcm_locked] ## connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/mb_debug_sys_rst] ## connect_bd_net -net microblaze_0_Clk [get_bd_pins axi_ethernetlite_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_led/s_axi_aclk] [get_bd_pins axi_gpio_pullup/s_axi_aclk] [get_bd_pins axi_gpio_sw/s_axi_aclk] [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_mem_intercon/S01_ACLK] [get_bd_pins axi_quad_spi_flash/ext_spi_clk] [get_bd_pins axi_quad_spi_flash/s_axi_aclk] [get_bd_pins axi_quad_spi_shield/ext_spi_clk] [get_bd_pins axi_quad_spi_shield/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins clk_wiz_1/clk_out1] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_intc/processor_clk] [get_bd_pins microblaze_0_axi_intc/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/M05_ACLK] [get_bd_pins microblaze_0_axi_periph/M06_ACLK] [get_bd_pins microblaze_0_axi_periph/M07_ACLK] [get_bd_pins microblaze_0_axi_periph/M08_ACLK] [get_bd_pins microblaze_0_axi_periph/M09_ACLK] [get_bd_pins microblaze_0_axi_periph/M10_ACLK] [get_bd_pins microblaze_0_axi_periph/M11_ACLK] [get_bd_pins microblaze_0_axi_periph/M12_ACLK] [get_bd_pins microblaze_0_axi_periph/M13_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk] [get_bd_pins xadc_wiz_0/s_axi_aclk] ## connect_bd_net -net microblaze_0_intr [get_bd_pins microblaze_0_axi_intc/intr] [get_bd_pins microblaze_0_xlconcat/dout] ## connect_bd_net -net mig_7series_0_mmcm_locked [get_bd_pins mig_7series_0/mmcm_locked] [get_bd_pins rst_mig_7series_0_83M/dcm_locked] ## connect_bd_net -net mig_7series_0_ui_clk [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins rst_mig_7series_0_83M/slowest_sync_clk] ## connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_pins mig_7series_0/ui_clk_sync_rst] [get_bd_pins rst_mig_7series_0_83M/ext_reset_in] ## connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins clk_wiz_1/resetn] [get_bd_pins mig_7series_0/sys_rst] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in] ## connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/bus_struct_reset] ## connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn] ## connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins microblaze_0_axi_intc/processor_rst] [get_bd_pins rst_clk_wiz_1_100M/mb_reset] ## connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins axi_ethernetlite_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_led/s_axi_aresetn] [get_bd_pins axi_gpio_pullup/s_axi_aresetn] [get_bd_pins axi_gpio_sw/s_axi_aresetn] [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_mem_intercon/S01_ARESETN] [get_bd_pins axi_quad_spi_flash/s_axi_aresetn] [get_bd_pins axi_quad_spi_shield/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins microblaze_0_axi_intc/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/M05_ARESETN] [get_bd_pins microblaze_0_axi_periph/M06_ARESETN] [get_bd_pins microblaze_0_axi_periph/M07_ARESETN] [get_bd_pins microblaze_0_axi_periph/M08_ARESETN] [get_bd_pins microblaze_0_axi_periph/M09_ARESETN] [get_bd_pins microblaze_0_axi_periph/M10_ARESETN] [get_bd_pins microblaze_0_axi_periph/M11_ARESETN] [get_bd_pins microblaze_0_axi_periph/M12_ARESETN] [get_bd_pins microblaze_0_axi_periph/M13_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn] [get_bd_pins xadc_wiz_0/s_axi_aresetn] ## connect_bd_net -net rst_mig_7series_0_83M_peripheral_aresetn [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins mig_7series_0/aresetn] [get_bd_pins rst_mig_7series_0_83M/peripheral_aresetn] ## connect_bd_net -net sys_clock_1 [get_bd_ports sys_clock] [get_bd_pins clk_wiz_1/clk_in1] ## connect_bd_net -net xadc_wiz_0_ip2intc_irpt [get_bd_pins microblaze_0_xlconcat/In6] [get_bd_pins xadc_wiz_0/ip2intc_irpt] ## connect_bd_net -net xadc_wiz_0_temp_out [get_bd_pins mig_7series_0/device_temp_i] [get_bd_pins xadc_wiz_0/temp_out] ## ## # Create address segments ## create_bd_addr_seg -range 0x10000 -offset 0x40E00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_ethernetlite_0/S_AXI/Reg] SEG_axi_ethernetlite_0_Reg ## create_bd_addr_seg -range 0x10000 -offset 0x40030000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg ## create_bd_addr_seg -range 0x10000 -offset 0x40040000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_1/S_AXI/Reg] SEG_axi_gpio_1_Reg ## create_bd_addr_seg -range 0x10000 -offset 0x40010000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_led/S_AXI/Reg] SEG_axi_gpio_2_Reg ## create_bd_addr_seg -range 0x10000 -offset 0x40020000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_pullup/S_AXI/Reg] SEG_axi_gpio_pullup_Reg ## create_bd_addr_seg -range 0x10000 -offset 0x40000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_sw/S_AXI/Reg] SEG_axi_gpio_sw_Reg ## create_bd_addr_seg -range 0x10000 -offset 0x40800000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg ## create_bd_addr_seg -range 0x10000 -offset 0x44A10000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_quad_spi_flash/AXI_LITE/Reg] SEG_axi_quad_spi_flash_Reg ## create_bd_addr_seg -range 0x10000 -offset 0x44A00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_quad_spi_shield/AXI_LITE/Reg] SEG_axi_quad_spi_shield_Reg ## create_bd_addr_seg -range 0x10000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg ## create_bd_addr_seg -range 0x10000 -offset 0x40600000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg ## create_bd_addr_seg -range 0x8000 -offset 0x0 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem ## create_bd_addr_seg -range 0x8000 -offset 0x0 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem ## create_bd_addr_seg -range 0x10000 -offset 0x41200000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_axi_intc/s_axi/Reg] SEG_microblaze_0_axi_intc_Reg ## create_bd_addr_seg -range 0x10000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr ## create_bd_addr_seg -range 0x10000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr ## create_bd_addr_seg -range 0x10000 -offset 0x44A20000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs xadc_wiz_0/s_axi_lite/Reg] SEG_xadc_wiz_0_Reg ## ## # Perform GUI Layout ## regenerate_bd_layout -layout_string { ## guistr: "# # String gsaved with Nlview 6.5.5 2015-06-26 bk=1.3371 VDI=38 GEI=35 GUI=JA:1.6 ## # -string -flagsOSRD ## preplace port spi -pg 1 -y 240 -defaultsOSRD ## preplace port shield_dp0_dp19 -pg 1 -y 200 -defaultsOSRD ## preplace port Vp_Vn -pg 1 -y 280 -defaultsOSRD ## preplace port shield_dp26_dp41 -pg 1 -y 220 -defaultsOSRD ## preplace port eth_mii -pg 1 -y 40 -defaultsOSRD ## preplace port qspi_flash -pg 1 -y 180 -defaultsOSRD ## preplace port i2c_pullups -pg 1 -y 160 -defaultsOSRD ## preplace port eth_mdio_mdc -pg 1 -y 20 -defaultsOSRD ## preplace port Vaux0 -pg 1 -y 20 -defaultsOSRD ## preplace port Vaux1 -pg 1 -y 40 -defaultsOSRD ## preplace port sys_clock -pg 1 -y 320 -defaultsOSRD ## preplace port Vaux2 -pg 1 -y 60 -defaultsOSRD ## preplace port usb_uart -pg 1 -y 260 -defaultsOSRD ## preplace port Vaux10 -pg 1 -y 180 -defaultsOSRD ## preplace port push_buttons_4bits -pg 1 -y 300 -defaultsOSRD ## preplace port i2c -pg 1 -y 100 -defaultsOSRD ## preplace port Vaux4 -pg 1 -y 80 -defaultsOSRD ## preplace port DDR3 -pg 1 -y -40 -defaultsOSRD ## preplace port rgb_led -pg 1 -y -60 -defaultsOSRD ## preplace port Vaux12 -pg 1 -y 200 -defaultsOSRD ## preplace port Vaux5 -pg 1 -y 100 -defaultsOSRD ## preplace port eth_ref_clk -pg 1 -y 80 -defaultsOSRD ## preplace port led_4bits -pg 1 -y -80 -defaultsOSRD ## preplace port Vaux13 -pg 1 -y 220 -defaultsOSRD ## preplace port Vaux6 -pg 1 -y 120 -defaultsOSRD ## preplace port Vaux14 -pg 1 -y 240 -defaultsOSRD ## preplace port Vaux7 -pg 1 -y 140 -defaultsOSRD ## preplace port Vaux15 -pg 1 -y 260 -defaultsOSRD ## preplace port reset -pg 1 -y 300 -defaultsOSRD ## preplace port dip_switches_4bits -pg 1 -y 280 -defaultsOSRD ## preplace port Vaux9 -pg 1 -y 160 -defaultsOSRD ## preplace inst rst_mig_7series_0_83M -pg 1 -lvl 1 -y 80 -defaultsOSRD ## preplace inst axi_iic_0 -pg 1 -lvl 4 -y 1210 -defaultsOSRD ## preplace inst mig_7series_0 -pg 1 -lvl 1 -y 1090 -defaultsOSRD ## preplace inst xadc_wiz_0 -pg 1 -lvl 1 -y 480 -defaultsOSRD ## preplace inst axi_gpio_sw -pg 1 -lvl 4 -y 440 -defaultsOSRD ## preplace inst microblaze_0_axi_periph -pg 1 -lvl 2 -y 330 -defaultsOSRD ## preplace inst microblaze_0_xlconcat -pg 1 -lvl 2 -y 1120 -defaultsOSRD ## preplace inst axi_timer_0 -pg 1 -lvl 3 -y 100 -defaultsOSRD ## preplace inst axi_gpio_led -pg 1 -lvl 3 -y -50 -defaultsOSRD ## preplace inst axi_gpio_0 -pg 1 -lvl 4 -y 560 -defaultsOSRD ## preplace inst axi_gpio_1 -pg 1 -lvl 4 -y 680 -defaultsOSRD ## preplace inst microblaze_0_axi_intc -pg 1 -lvl 3 -y 1170 -defaultsOSRD ## preplace inst mdm_1 -pg 1 -lvl 3 -y 770 -defaultsOSRD ## preplace inst axi_quad_spi_flash -pg 1 -lvl 4 -y 1380 -defaultsOSRD ## preplace inst axi_ethernetlite_0 -pg 1 -lvl 4 -y 40 -defaultsOSRD ## preplace inst axi_gpio_pullup -pg 1 -lvl 4 -y 300 -defaultsOSRD ## preplace inst microblaze_0 -pg 1 -lvl 3 -y 900 -defaultsOSRD ## preplace inst axi_uartlite_0 -pg 1 -lvl 3 -y 640 -defaultsOSRD ## preplace inst rst_clk_wiz_1_100M -pg 1 -lvl 2 -y 1540 -defaultsOSRD ## preplace inst axi_quad_spi_shield -pg 1 -lvl 3 -y 260 -defaultsOSRD ## preplace inst microblaze_0_local_memory -pg 1 -lvl 2 -y 880 -defaultsOSRD ## preplace inst clk_wiz_1 -pg 1 -lvl 3 -y 460 -defaultsOSRD ## preplace inst axi_mem_intercon -pg 1 -lvl 4 -y 900 -defaultsOSRD ## preplace netloc microblaze_0_axi_periph_M02_AXI 1 2 1 950 ## preplace netloc axi_gpio_2_GPIO 1 3 2 NJ -80 NJ ## preplace netloc Vaux5_1 1 0 1 -40 ## preplace netloc mig_7series_0_DDR3 1 1 4 450 1010 NJ 1010 NJ -40 NJ ## preplace netloc axi_timer_0_interrupt 1 1 3 570 1000 NJ 1020 1780 ## preplace netloc xadc_wiz_0_temp_out 1 0 2 50 730 390 ## preplace netloc microblaze_0_axi_periph_M03_AXI 1 2 1 1080 ## preplace netloc axi_gpio_pullup_GPIO 1 4 1 2250 ## preplace netloc axi_quad_spi_0_SPI_0 1 3 2 1850 230 NJ ## preplace netloc microblaze_0_axi_periph_M01_AXI 1 2 2 NJ 340 NJ ## preplace netloc axi_gpio_sw_GPIO2 1 4 1 NJ ## preplace netloc sys_clock_1 1 0 3 NJ 720 NJ 720 1000 ## preplace netloc axi_iic_0_IIC 1 4 1 2280 ## preplace netloc microblaze_0_intc_axi 1 2 1 1020 ## preplace netloc microblaze_0_dlmb_1 1 1 3 480 1280 NJ 1280 1750 ## preplace netloc microblaze_0_M_AXI_IC 1 3 1 1890 ## preplace netloc axi_ethernetlite_0_ip2intc_irpt 1 1 4 510 730 NJ 560 NJ -50 2250 ## preplace netloc rst_clk_wiz_1_100M_mb_reset 1 2 1 1070 ## preplace netloc mig_7series_0_mmcm_locked 1 0 2 30 740 390 ## preplace netloc rst_clk_wiz_1_100M_bus_struct_reset 1 1 2 560 1230 910 ## preplace netloc axi_gpio_0_GPIO2 1 4 1 2290 ## preplace netloc axi_quad_spi_shield_ip2intc_irpt 1 1 3 550 1320 NJ 1320 1810 ## preplace netloc mig_7series_0_ui_clk_sync_rst 1 0 2 30 -10 400 ## preplace netloc Vaux12_1 1 0 1 -100 ## preplace netloc microblaze_0_ilmb_1 1 1 3 490 1290 NJ 1290 1740 ## preplace netloc microblaze_0_axi_periph_M12_AXI 1 2 2 NJ 570 1890 ## preplace netloc microblaze_0_axi_periph_M08_AXI 1 2 1 920 ## preplace netloc microblaze_0_interrupt 1 2 2 1080 1070 1720 ## preplace netloc Vaux15_1 1 0 1 -130 ## preplace netloc mdm_1_debug_sys_rst 1 1 3 570 1390 NJ 1390 1790 ## preplace netloc axi_iic_0_iic2intc_irpt 1 1 4 530 1300 NJ 1300 NJ 1280 2260 ## preplace netloc microblaze_0_axi_periph_M13_AXI 1 0 3 20 -50 NJ -50 910 ## preplace netloc axi_quad_spi_flash_ip2intc_irpt 1 1 4 540 1310 NJ 1310 NJ 1300 2260 ## preplace netloc axi_uartlite_0_UART 1 3 2 NJ 210 2270 ## preplace netloc Vaux13_1 1 0 1 -110 ## preplace netloc Vaux7_1 1 0 1 -60 ## preplace netloc microblaze_0_Clk 1 0 4 40 700 460 760 1040 1330 1900 ## preplace netloc axi_quad_spi_1_SPI_0 1 4 1 2310 ## preplace netloc rst_mig_7series_0_83M_peripheral_aresetn 1 0 4 30 790 420 790 NJ 1050 NJ ## preplace netloc axi_gpio_1_GPIO1 1 4 1 2320 ## preplace netloc Vaux2_1 1 0 1 -20 ## preplace netloc Vp_Vn_1 1 0 1 -70 ## preplace netloc axi_ethernetlite_0_MDIO 1 4 1 2280 ## preplace netloc axi_ethernetlite_0_MII 1 4 1 2260 ## preplace netloc Vaux0_1 1 0 1 0 ## preplace netloc microblaze_0_axi_periph_M11_AXI 1 2 2 NJ 550 1890 ## preplace netloc clk_wiz_1_locked 1 1 3 560 1380 NJ 1380 1800 ## preplace netloc microblaze_0_debug 1 2 2 1090 990 1730 ## preplace netloc microblaze_0_axi_periph_M09_AXI 1 2 2 NJ 360 NJ ## preplace netloc microblaze_0_axi_dp 1 1 3 500 970 NJ 1000 1720 ## preplace netloc rst_clk_wiz_1_100M_interconnect_aresetn 1 1 3 470 1340 1040 1340 NJ ## preplace netloc xadc_wiz_0_ip2intc_irpt 1 1 1 430 ## preplace netloc clk_wiz_1_clk_out2 1 0 4 20 780 NJ 780 NJ 1030 1770 ## preplace netloc microblaze_0_axi_periph_M06_AXI 1 2 2 NJ 1270 NJ ## preplace netloc Vaux6_1 1 0 1 -50 ## preplace netloc clk_wiz_1_clk_out3 1 0 4 60 990 NJ 990 NJ 1040 1760 ## preplace netloc Vaux14_1 1 0 1 -120 ## preplace netloc clk_wiz_1_clk_out4 1 3 2 1840 -30 NJ ## preplace netloc Vaux4_1 1 0 1 -30 ## preplace netloc mig_7series_0_ui_clk 1 0 4 10 970 NJ 980 NJ 1060 NJ ## preplace netloc microblaze_0_axi_periph_M04_AXI 1 2 1 960 ## preplace netloc Vaux10_1 1 0 1 -90 ## preplace netloc axi_gpio_2_GPIO2 1 3 2 NJ -60 NJ ## preplace netloc microblaze_0_axi_periph_M07_AXI 1 2 2 NJ 350 NJ ## preplace netloc axi_gpio_sw_GPIO 1 4 1 NJ ## preplace netloc Vaux1_1 1 0 1 -10 ## preplace netloc microblaze_0_M_AXI_DC 1 3 1 1880 ## preplace netloc axi_mem_intercon_M00_AXI 1 0 5 40 710 NJ 710 NJ 710 NJ 750 2250 ## preplace netloc Vaux9_1 1 0 1 -80 ## preplace netloc microblaze_0_intr 1 2 1 910 ## preplace netloc reset_1 1 0 3 -140 750 440 750 NJ ## preplace netloc microblaze_0_axi_periph_M05_AXI 1 2 2 NJ 1350 NJ ## preplace netloc rst_clk_wiz_1_100M_peripheral_aresetn 1 0 4 50 690 410 -60 990 1400 1920 ## preplace netloc axi_gpio_sw_ip2intc_irpt 1 1 4 520 740 NJ 370 NJ 370 2260 ## levelinfo -pg 1 -170 230 750 1500 2120 2370 -top -120 -bot 1630 ## ", ## } ## ## # Restore current instance ## current_bd_instance $oldCurInst ## ## save_bd_design ## } ## create_root_design "" WARNING: [BD 41-176] The physical port 'di' specified in the portmap, is not found on the block! WARNING: [BD 41-176] The physical port 'di' specified in the portmap, is not found on the block! INFO: [Device 21-403] Loading part xc7a35ticsg324-1L Wrote : # set design_name [get_bd_designs] # make_wrapper -files [get_files $design_name.bd] -top -import INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /axi_quad_spi_shield ####################################################################################### INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other. ######################################################################################## INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /axi_quad_spi_flash ####################################################################################### INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other. ######################################################################################## INFO: [xilinx.com:ip:axi_intc:4.1-1] /microblaze_0_axi_intc: The AXI INTC core has been configured to operate with synchronous clocks. INFO: [xilinx.com:ip:microblaze:9.5-16] /microblaze_0: Setting D-cache cacheable area base address C_DCACHE_BASEADDR to 0x80000000 and high address C_DCACHE_HIGHADDR to 0x8FFFFFFF. INFO: [xilinx.com:ip:microblaze:9.5-16] /microblaze_0: Setting I-cache cacheable area base address C_ICACHE_BASEADDR to 0x80000000 and high address C_ICACHE_HIGHADDR to 0x8FFFFFFF. VHDL Output written to : D:/Users/paul/Documents/xilinx/Arty-master/Projects/BSD/proj/bsd.srcs/sources_1/bd/system/hdl/system.vhd VHDL Output written to : D:/Users/paul/Documents/xilinx/Arty-master/Projects/BSD/proj/bsd.srcs/sources_1/bd/system/hdl/system_wrapper.vhd Wrote : WARNING: [Vivado 12-3482] The generated wrapper file has already been imported into the project, the imported file is: 'D:/Users/paul/Documents/xilinx/Arty-master/Projects/BSD/proj/bsd.srcs/sources_1/imports/hdl/system_wrapper.vhd' make_wrapper: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1163.613 ; gain = 30.809 # set obj [get_filesets sources_1] # set_property "top" "${design_name}_wrapper" $obj # puts "INFO: Block design created: $design_name.bd" INFO: Block design created: system.bd # set scripts_vivado_version 2015.3 # set current_vivado_version [version -short] # if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { # puts "" # puts "WARNING: This script was generated in <$scripts_vivado_version> and is being run in <$current_vivado_version>. If any problems occur, retry running this script in Vivado <$scripts_vivado_version>." # # # return 1 # } update_compile_order -fileset sources_1 update_compile_order -fileset sim_1